CN115694512A

CN115694512A - Data conversion circuit, method and memory

Info

Publication number: CN115694512A
Application number: CN202211294436.7A
Authority: CN
Inventors: 刘忠来
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2023-02-03

Abstract

The disclosed embodiment provides a data conversion circuit, a method and a memory, wherein the circuit comprises a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used for receiving a compensation signal, the other end of the adjustment module is respectively connected with the output end of the conversion module and the input end of the transmission module, wherein: the conversion module is used for receiving the initial data signal and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; the adjusting module is used for compensating the intermediate data signal according to the compensation signal so as to reduce the signal swing amplitude of the intermediate data signal; and the transmission module is used for carrying out drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal. The embodiment of the disclosure can reduce the signal swing of the intermediate data signal, increase the signal bandwidth and improve the high-frequency performance of the circuit.

Description

Data conversion circuit, method and memory

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a data conversion circuit, a method, and a memory.

Background

In the Data transmission process, there is often a need to convert parallel Data into serial Data, and in order to obtain a faster Data transmission speed, a series of devices such as memories capable of Double Data Rate (DDR) Data transmission have been developed. However, as data rates increase, for example from 4266 megabits per second (Mbps) for LPDDR 4to 6400Mbps for LPDDR5, due to device performance limitations, for circuits that convert parallel data to serial data, the high frequency performance of the circuit is limited due to the large parasitic capacitance of the data nodes.

Disclosure of Invention

The embodiment of the disclosure provides a data conversion circuit, a data conversion method and a memory.

In a first aspect, an embodiment of the present disclosure provides a data conversion circuit, which includes a conversion module, an adjustment module, and a transmission module, where one end of the adjustment module is configured to receive a compensation signal, and the other end of the adjustment module is connected to an output end of the conversion module and an input end of the transmission module, respectively, where:

the conversion module is used for receiving an initial data signal and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;

the adjusting module is used for performing compensation processing on the intermediate data signal according to a compensation signal so as to reduce the signal swing of the intermediate data signal;

and the transmission module is used for carrying out drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

In some embodiments, the adjusting module includes a transmission gate module, one end of the transmission gate module is configured to receive the compensation signal, the other end of the transmission gate module is connected to the output end of the converting module and the input end of the transmission module, respectively, and a control end of the transmission gate module is configured to receive an enable control signal, where:

when the enable control signal is in an effective state, the transmission gate module is conducted so as to perform compensation processing on the intermediate data signal according to the compensation signal; or when the enable control signal is in an invalid state, the transmission gate module is turned off.

In some embodiments, the enable control signal comprises a first enable control signal and a second enable control signal, wherein:

the transmission gate module comprises an NMOS tube and a PMOS tube, wherein a first end of the NMOS tube is connected with a first end of the PMOS tube to serve as one end of the transmission gate module, and a second end of the NMOS tube is connected with a second end of the PMOS tube to serve as the other end of the transmission gate module;

the control end of the transmission gate module comprises a gate end of the NMOS tube and a gate end of the PMOS tube, the gate end of the NMOS tube is connected with the first enabling control signal, the gate end of the PMOS tube is connected with the second enabling control signal, and the first enabling control signal and the second enabling control signal are opposite-phase signals.

In some embodiments, the adjusting module further includes a first not gate, an input terminal of the first not gate is connected to the gate terminal of the NMOS transistor, an output terminal of the first not gate is connected to the gate terminal of the PMOS transistor, wherein:

the first not gate is used for receiving the first enabling control signal and carrying out reverse phase processing on the first enabling control signal to obtain the second enabling control signal.

In some embodiments, the adjusting module includes a resistor module, one end of the resistor module is configured to receive the compensation signal, and the other end of the resistor module is connected to the output end of the converting module and the input end of the transmitting module, respectively, where:

and the resistance module is used for performing compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal.

In some embodiments, the transmission module comprises a first transmission sub-module and a second transmission sub-module, an input of the first transmission sub-module being connected to an output of the conversion module, an output of the first transmission sub-module being connected to an input of the second transmission sub-module, wherein:

the first transmission submodule is used for carrying out phase reversal processing on the intermediate data signal after compensation processing to obtain an initial target data signal;

and the second transmission submodule is used for carrying out phase reversal processing on the initial target data signal to obtain the target data signal.

In some embodiments, one end of the adjusting module is connected to the output of the first transmission sub-module, and the other end of the adjusting module is connected to the input of the first transmission sub-module, wherein:

the first transmission sub-module is further configured to determine the initial target data signal as the compensation signal.

In some embodiments, the first transmission submodule comprises a second not gate and a first nand gate, the second transmission submodule comprises a third not gate, a first input of the first nand gate is used for receiving a transmission control signal, a second input of the first nand gate is connected with an output of the second not gate and an input of the third not gate, and an output of the first nand gate is connected with an input of the second not gate; the input end of the second not gate is used as the input end of the first transmission submodule, the output end of the second not gate is used as the output end of the first transmission submodule, the input end of the third not gate is used as the input end of the second transmission submodule, and the output end of the third not gate is used as the output end of the second transmission submodule.

In some embodiments, the conversion module comprises a first conversion sub-module, a second conversion sub-module, a third conversion sub-module, and a fourth conversion sub-module, the initial data signal comprises first initial data, second initial data, third initial data, and fourth initial data, wherein:

the first conversion sub-module is configured to receive the first initial data and a first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data;

the second conversion submodule is configured to receive the second initial data and a second clock signal, and perform sampling processing on the second initial data according to the second clock signal to obtain second intermediate data;

the third conversion sub-module is configured to receive the third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

the fourth conversion sub-module is configured to receive the fourth initial data and a fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

wherein phases of the first, second, third, and fourth clock signals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively, and the first, second, third, and fourth intermediate data constitute the intermediate data signal.

In some embodiments, the conversion module comprises a first conversion module and a second conversion module, the initial data signal comprises a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal comprises a first intermediate data signal and a second intermediate data signal, wherein:

the first conversion module is configured to receive the first initial data signal, and perform parallel-to-serial conversion on the first initial data signal to obtain the first intermediate data signal;

the second conversion module is configured to receive the second initial data signal, and perform parallel-to-serial conversion on the second initial data signal to obtain the second intermediate data signal.

In some embodiments, the compensation signal comprises the first intermediate data signal and the second intermediate data signal, wherein:

the adjusting module is configured to perform compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce a signal swing of the second intermediate data signal; and performing compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

In some embodiments, the target data signal comprises a first target data signal and a second target data signal, the transmission module comprises a first transmission module and a second transmission module, wherein:

the first transmission module is configured to perform drive enhancement processing on the compensated first intermediate data signal to obtain the first target data signal;

and the second transmission module is used for performing drive enhancement processing on the compensated second intermediate data signal to obtain the second target data signal.

In some embodiments, one end of the adjusting module is connected to the output end of the first converting module and the input end of the first transmitting module, respectively, and the other end of the adjusting module is connected to the output end of the second converting module and the input end of the second transmitting module, respectively.

In some embodiments, the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.

In a second aspect, an embodiment of the present disclosure provides a data conversion method, including:

receiving an initial data signal through a conversion module, and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;

receiving a compensation signal through an adjusting module, and performing compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing amplitude of the intermediate data signal;

and receiving the intermediate data signal after compensation processing through a transmission module, and performing drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

In a third aspect, an embodiment of the present disclosure provides a memory including the data conversion circuit according to any one of the first aspect.

The disclosed embodiment provides a data conversion circuit, a method and a memory, wherein the circuit comprises a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used for receiving a compensation signal, the other end of the adjustment module is respectively connected with the output end of the conversion module and the input end of the transmission module, wherein: the conversion module is used for receiving the initial data signal and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; the adjusting module is used for compensating the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal; and the transmission module is used for carrying out drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal. Therefore, the adjusting module is arranged in the data conversion circuit and compensates the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, namely the signal swing of a connecting node of the conversion module and the transmission module is reduced, the signal bandwidth is increased, the purpose of transmitting high-frequency data is finally achieved, and the high-frequency performance of the circuit is improved.

Drawings

FIG. 1 is a schematic diagram of a parallel-to-serial circuit;

fig. 2 is a schematic structural diagram of a data conversion circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a data conversion circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a data conversion circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a data conversion circuit according to a fourth embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a data conversion circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram six of a data conversion circuit according to an embodiment of the present disclosure;

fig. 8 is a first specific structural diagram of a data conversion circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a data conversion circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a conversion module according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a signal timing sequence provided by the present disclosure;

fig. 12 is a schematic diagram illustrating a structure of a data conversion circuit according to a seventh embodiment of the present disclosure;

fig. 13 is a third schematic structural diagram of a data conversion circuit according to an embodiment of the present disclosure;

fig. 14 is a schematic flowchart of a data conversion method according to an embodiment of the disclosure;

fig. 15 is a schematic structural diagram of a memory according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and are not limiting of the disclosure. It should be noted that, for the convenience of description, only the parts relevant to the related disclosure are shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to be limiting of the disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

It is noted that the terms "first \ second \ third" and "first \ second \ third" in the embodiments of the present disclosure are used for distinguishing similar objects only and do not denote a particular order or sequence of objects, and it is to be understood that "first \ second \ third" and "first \ second \ third" may be interchanged under certain circumstances or sequences of events to enable embodiments of the present disclosure described herein to be practiced in other than the order shown or described herein.

Before further detailed description of the embodiments of the present disclosure, terms and expressions referred to in the embodiments of the present disclosure are explained, and the terms and expressions referred to in the embodiments of the present disclosure are applicable to the following explanations:

dynamic Random Access Memory (DRAM);

double Data Rate (DDR);

a P-type Metal Oxide semiconductor field effect transistor (PMOS transistor);

an N-type Metal Oxide semiconductor field effect transistor (NMOS tube);

d flip-flop (DFF).

Fig. 1 is a schematic diagram of a parallel-to-serial circuit. As shown in fig. 1, the parallel-to-serial circuit 10 is a circuit for converting four paths of parallel data into serial data, and includes four P2S4tol sub-circuits, where the four P2S4tol sub-circuits respectively receive four paths of parallel data: dataER, dataEF, dataOR, and DataOF, and receives four clock signals: sedCKER, sedCKEF, sedCKOR, and SedCKOF. And the four P2S4tol sub-circuits respectively sample four parallel data according to the four clock signals and output serial data at the PupMid node.

And the serial data of the PupMid node is driven and enhanced through an inverter X1 and an inverter X2, and finally the serial data DataPu is obtained. Meanwhile, the nand gate Xfb is connected in parallel with the inverter X1, and controls whether serial data can be normally transmitted according to the DqRstN signal.

As data rates increase, for example from LPDDR4 4266Mbps to LPDDR5 6400Mbps, the performance of the circuit suffers bottlenecks due to device performance limitations. The main reason is that the PupMid node is connected to not only the four P2S4to1 sub-circuits, but also the output devices X1 and Xfb, which results in a large parasitic capacitance of the PupMid node, thereby limiting the high frequency performance of the circuit. In order to improve the high-frequency performance of the circuit, one method is to reduce the parasitic capacitance of the PupMid node through a layout, but due to structural limitation, the parasitic capacitance cannot be reduced infinitely, and the method can improve the performance but has a bottleneck.

Based on this, the disclosed embodiment provides a data conversion circuit, which includes a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used for receiving a compensation signal, and the other end of the adjustment module is connected to an output end of the conversion module and an input end of the transmission module, respectively, and wherein: the conversion module is used for receiving the initial data signal and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; the adjusting module is used for compensating the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal; and the transmission module is used for carrying out drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal. Therefore, the adjusting module is arranged in the data conversion circuit and compensates the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, namely the signal swing of a connecting node of the conversion module and the transmission module is reduced, the signal bandwidth is increased, the purpose of transmitting high-frequency data is finally achieved, and the high-frequency performance of the circuit is improved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, referring to fig. 2, a first schematic structural diagram of a data conversion circuit provided in an embodiment of the present disclosure is shown. As shown in fig. 2, the data conversion circuit 20 includes a conversion module 201, an adjustment module 202, and a transmission module 203, wherein one end of the adjustment module 202 is used for receiving the compensation signal, and the other end of the adjustment module 202 is connected to an output end of the conversion module 201 and an input end of the transmission module 203, respectively, where:

the conversion module 201 is configured to receive an initial data signal, perform parallel-to-serial processing on the initial data signal, and obtain an intermediate data signal;

the adjusting module 202 is configured to perform compensation processing on the intermediate data signal according to the compensation signal to reduce a signal swing of the intermediate data signal;

and the transmission module 203 is configured to perform drive enhancement processing on the compensated intermediate data signal to obtain a target data signal.

In the data conversion circuit 20, the conversion module 201 receives the parallel initial data signals, converts the parallel initial data signals into the serial intermediate data signals, and the transmission module 203 performs drive enhancement on the serial intermediate data signals to obtain the serial target data signals. That is, in the embodiments of the present disclosure, the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are both serial data signals.

It should be further noted that, as shown in fig. 2, the output terminal of the conversion module 201, the input terminal of the transmission module 203, and one terminal of the adjustment module 202 are connected to the same node, and a signal at the node is an intermediate data signal. Because the number of devices connected with the node is large, the parasitic capacitance of the node is large, and the high-frequency characteristic of the device is limited. At this time, the adjusting module 202 may perform compensation processing on the node according to the received compensation signal to reduce the signal swing of the node, that is, perform compensation processing on the intermediate data signal to reduce the signal swing of the intermediate data signal. Therefore, the signal swing is reduced, so that the signal bandwidth is increased, the high-frequency performance of the circuit can be improved, and the purpose of transmitting high-frequency data is achieved.

It should be noted that the compensation signal is usually a signal with a level state opposite to that of the intermediate data signal, for example, if the intermediate data signal is at a high level and the compensation signal is at a low level, the low-level compensation signal affects the voltage of the intermediate data signal through the adjusting module 202, so that the voltage of the intermediate data signal is slightly lower than the original high level; similarly, when the intermediate data signal is at a low level and the compensation signal is at a high level, the compensation signal pulls up the voltage of the intermediate data signal through the adjusting module 202. Finally, the swing amplitude of the intermediate data signal can be reduced, and high-frequency data transmission is further realized.

As to the adjusting module 202, in a possible implementation manner, as shown in fig. 3, the adjusting module 202 may include a transmission gate module 2021 (also called a transmission gate, a transmission pipe), one end of the transmission gate module 2021 is configured to receive the compensation signal, the other end of the transmission gate module 2021 is connected to the output end of the converting module 201 and the input end of the transmission module 203 respectively, and the control end of the transmission gate module 2021 is configured to receive the enable control signal, where:

when the enable control signal is in an active state, the transmission gate module 2021 is turned on to perform compensation processing on the intermediate data signal according to the compensation signal; alternatively, the pass gate module 2021 is turned off when the enable control signal is in an inactive state.

It should be noted that, as shown in fig. 3, the adjusting module 202 may be implemented by a transmission gate module 2021. At this time, the compensation signal acts on the intermediate data signal through the transmission gate module 2021, so as to reduce the signal swing of the intermediate data signal.

It should be noted that, in the embodiments of the present disclosure, the intermediate data signal is mainly compensated when the high-frequency signal is transmitted, so as to meet the requirement of the circuit for transmitting the high-frequency signal, and the intermediate data signal may not be compensated when the high-frequency signal is not required to be transmitted. Therefore, whether the transmission gate module 2021 is turned on or not can be controlled by the enable control signal, so that the enable control signal is in an active state only when the signal swing of the intermediate data signal needs to be reduced, and at this time, the transmission gate module 2021 is turned on; when the compensation processing for the intermediate data signal is not required, the enable control signal is in an inactive state, and at this time, the transmission gate module 2021 is not turned on, and the intermediate data signal is not compensated.

Therefore, the transmission gate module 2021 is controlled by the enable control signal, so that the signal swing of the intermediate data signal can be reduced to meet the requirement of transmitting high-frequency data, the transmission gate module 2021 can be turned off in other scenes, the power consumption of the circuit is saved, the use requirements of various scenes are met, and flexible control is realized.

Further, as for the transmission gate module 2021, as shown in fig. 4, the transmission gate module 2021 includes an NMOS transistor (N1) and a PMOS transistor (P1), a first end of the NMOS transistor is connected to a first end of the PMOS transistor to serve as one end of the transmission gate module 2021, and a second end of the NMOS transistor is connected to a second end of the PMOS transistor to serve as the other end of the transmission gate module 2021;

the control end of the transmission gate module 2021 includes a gate terminal of an NMOS transistor and a gate terminal of a PMOS transistor, the gate terminal of the NMOS transistor is connected to the first enable control signal, the gate terminal of the PMOS transistor is connected to the second enable control signal, and the first enable control signal and the second enable control signal are opposite-phase signals.

It should be noted that, as shown in fig. 4, the transmission gate module 2021 may be formed by connecting an NMOS transistor and a PMOS transistor. At this time, the gate terminals of the NMOS transistor and the PMOS transistor are respectively used as two control terminals of the transmission gate module 2021, and accordingly, the enable control signal includes a pair of inverted signals: a first enable control signal and a second enable control signal; the first end of the NMOS transistor and the first end of the PMOS transistor are connected as one end of the transmission gate module 2021 for receiving the compensation signal, and the second end of the NMOS transistor and the second end of the PMOS transistor are connected as the other end of the transmission gate module 2021 connected to the output end of the conversion module 201 and the input end of the transmission module 203.

Thus, for the first enable control signal and the second enable control signal, the active state of the first enable control signal may be a high state (logic "1") and the active state of the second enable control signal may be a low state (logic "0"). When the first enabling control signal is in a high level state and/or the second enabling control signal is in a low level state, the NMOS tube and/or the PMOS tube are/is conducted, so that the compensation signal can be transmitted to the node where the intermediate data signal is located, and the compensation processing of the intermediate data signal is realized; when the first enable control signal is in a low level state and the second enable control signal is in a high level state, the NMOS transistor and the PMOS transistor are not turned on, the transmission gate module 2021 is turned off, the compensation signal is not transmitted to the node where the intermediate data signal is located, and at this time, the intermediate data signal is not compensated.

Since the first enable control signal and the second enable control signal are opposite-phase signals, the first enable control signal can be inverted into the second enable control signal through the not gate. Therefore, in some embodiments, based on the circuit shown in fig. 4, as shown in fig. 5, the adjusting module 202 may further include a first not gate 2022, an input terminal of the first not gate 2022 is connected to the gate terminal of the NMOS transistor, and an output terminal of the first not gate 2022 is connected to the gate terminal of the PMOS transistor, wherein:

the first not gate 2022 is configured to receive the first enable control signal and perform inverse processing on the first enable control signal to obtain a second enable control signal.

As shown in fig. 5, the input terminal of the first not gate 2022 is connected to the gate terminal of the NMOS transistor for receiving the first enable control signal, and the output terminal of the first not gate 2022 is connected to the gate terminal of the PMOS transistor, so that the first not gate 2022 can provide the second enable control signal obtained by inverting the first enable control signal to the gate terminal of the PMOS transistor.

It should be noted that, as shown in fig. 5, for the transmission gate module 2021, two control terminals (the gate terminal of the PMOS transistor and the gate terminal of the NMOS transistor) respectively receive the first enable control signal and the second enable control signal, and the adjustment module 202 as a whole only needs to receive one first enable control signal. In this way, the transmission gate module can be turned on only in the high-speed mode of transmitting high-frequency data, so that the level state of the first enable control signal can be controlled, and in the high-speed mode, the first enable control signal is at a high level (logic "1") and is in an effective state, so that the transmission gate module 2021 is turned on, and the reduction of the signal swing of the intermediate data signal is realized; in the non-high-speed mode, the first enable control signal is at a low level (logic "0"), and is in an inactive state, and the transmission gate module 2021 is not turned on, thereby saving power consumption. As can be seen, the first Enable control signal is determined to be active according to whether High frequency data is currently transmitted, so as to turn on or off the transmission gate module 2021, and therefore, the first Enable control signal may also be referred to as a High Speed Enable (HSEn) signal.

It should be further noted that the first not gate 2022 may also be connected as follows: the input end of the first not gate 2022 is connected to the gate end of the PMOS transistor and is used for receiving the second enable control signal, and the output end of the first not gate is connected to the gate end of the NMOS transistor and is used for outputting the first enable control signal. At this time, the whole of the adjusting module 202 only needs to receive a second enable control signal, which is a high-speed enable signal and has an active state of low level (logic "0") and an inactive state of high level (logic "1"). Control of the transmission gate module 2021 may also be achieved.

As for the adjusting module 202, in another possible implementation manner, as shown in fig. 6, the adjusting module 202 may include a resistor module 2023, one end of the resistor module 2023 is used for receiving the compensation signal, and the other end of the resistor module 2023 is connected to the output end of the converting module 201 and the input end of the transmitting module 203, respectively, where:

the resistor module 2023 is configured to perform compensation processing on the intermediate data signal according to the compensation signal to reduce a signal swing of the intermediate data signal.

It should be noted that, as shown in fig. 6, the adjusting module 202 may also be implemented by a resistor module 2023. The function of the resistor module 2023 is similar to that of the transmission gate module 2021, and the resistor module 2023 transmits the compensation signal to the node where the intermediate data signal is located, where the compensation signal is usually opposite to the level state of the intermediate data signal, so that the voltage of the intermediate data signal can be pulled down for a high level, and the voltage of the intermediate data signal can be pulled up for a low level, thereby reducing the signal swing of the intermediate data signal and achieving the purpose of transmitting a high frequency signal.

It should be further noted that the resistor module 2023 may be implemented by a fixed resistor or a variable resistor, or a combination of the fixed resistor and the variable resistor, and is not limited herein. Therefore, the compensation degree of the intermediate data signal can be adjusted by adjusting the resistance value of the variable resistor, and flexible control is realized.

For example, the low frequency, the first-stage high frequency and the second-stage high frequency may be sequentially divided from low to high according to the frequency level of the data, and in a low-frequency scenario, the resistance value of the resistor module 2023 may be set to be very high, so that the compensation signal hardly passes through, which is equivalent to an off state, and thus the intermediate data signal is hardly compensated; in a first-level high-frequency scene, the resistance value of the resistance module 2023 is set to be a first resistance value, so that the compensation signal can pass through but has a certain loss, and the compensation of the intermediate data signal is realized to a certain extent; in the second-stage high-frequency scenario, the resistance value of the resistor module 2023 may be set to be a second resistance value (the second resistance value is smaller than the first resistance value), so that the compensation signal can pass through and the loss is very low, thereby implementing higher-degree compensation on the intermediate data signal.

Further to the transmission module 203, as shown in fig. 7, in some embodiments, the transmission module 203 includes a first transmission sub-module 2031 and a second transmission sub-module 2032, an input of the first transmission sub-module 2031 is connected to an output of the conversion module 201, an output of the first transmission sub-module 2031 is connected to an input of the second transmission sub-module 2032, wherein:

a first transmission sub-module 2031, configured to perform inverse phase processing on the compensated intermediate data signal to obtain an initial target data signal;

the second transmission sub-module 2032 is configured to perform inverse phase processing on the initial target data signal to obtain a target data signal.

It should be noted that, as shown in fig. 7, in the transmission module 203, the first transmission sub-module 2031 is connected to the conversion module 201 and the adjustment module 202, respectively, and is configured to receive the compensated intermediate data signal, perform inverse phase processing on the intermediate data signal to obtain an initial target data signal, and send the initial target data signal to the second transmission sub-module 2032; and after the second transmission submodule receives the initial target data signal, performing phase inversion again, and performing phase inversion on the initial target data signal to obtain a target data signal. Since the intermediate data signal is serial data, the initial target data signal and the target data signal are both serial data signals.

In this way, through the two-stage inversion processing of the first transmission sub-module 2031 and the second transmission sub-module 2032, the level state of the finally obtained target data signal is unchanged compared with the intermediate data signal, but the driving capability is enhanced, which is more beneficial to the transmission of the data signal.

Since the compensation signal is usually a signal having a state opposite to the level state of the intermediate data signal, and the initial target data signal is obtained by performing an inversion process on the intermediate data signal, the initial target data signal can be used as the compensation signal in the embodiment of the present disclosure. Thus, as shown in fig. 7, in some embodiments, one end of the adjustment module 202 is connected to an output of the first transmission sub-module 2031 and the other end of the adjustment module 202 is connected to an input of the first transmission sub-module 2032, where:

the first transmission sub-module 2031 is further configured to determine an initial target data signal as the compensation signal.

It should be noted that, as shown in fig. 7, an output end of the first transmission sub-module 2031 may be connected to one end of the adjusting module 202, where a node where the intermediate data signal is located is referred to as a PupMid node, a node where the initial target data signal is located is referred to as a PupMid node, and the adjusting module 202 is connected between the PupMid node and the PupMid node. Thus, for the data conversion circuit 20, the initial data signal is processed into an intermediate data signal by the conversion module 201, the intermediate data signal is processed into an initial target data signal by the first conversion sub-module 2031 in an inverted phase, the initial target data signal is used as a compensation signal, and the initial target data signal and the intermediate data signal are mutually inverted signals, and the adjustment module 202 performs compensation processing on the intermediate data signal according to the initial target data signal, so that the signal swing of the intermediate data signal is reduced, that is, the signal swing of the PupMid node is reduced, thereby improving the high-frequency performance of the circuit and the speed of the circuit for transmitting data.

Further, fig. 8 is a schematic diagram of a specific structure of a data conversion circuit provided by an embodiment of the present disclosure on the basis of fig. 5, and fig. 9 is a schematic diagram of a specific structure of a data conversion circuit provided by an embodiment of the present disclosure on the basis of fig. 6. The adjusting module 202 in fig. 8 is implemented by a transmission gate module 2021 and a first not gate 2022, and the adjusting module 202 in fig. 9 is implemented by a resistor module 2023.

It should be noted that in fig. 8, the output terminal of the first transmission submodule 2031 is connected to the first terminals of the PMOS transistor and the NMOS transistor (the first terminal of the transmission gate module 2021), and in fig. 9, the output terminal of the first transmission submodule 2031 is connected to one terminal of the resistor module 2023. In this way, the first transmission sub-module 2031 may directly provide the output initial target data signal as a compensation signal to the adjusting module 202 for performing compensation processing on the intermediate data signal.

As shown in fig. 8 or fig. 9, in some embodiments, the first transmission sub-module 2031 comprises a second not-gate 2033 and a first nand-gate 2034, the second transmission sub-module 2032 comprises a third not-gate 2035, a first input of the first nand-gate 2034 is configured to receive the transmission control signal, a second input of the first nand-gate 2034 is connected to an output of the second not-gate 2033 and an input of the third not-gate 2035, and an output of the first nand-gate 2034 is connected to an input of the second not-gate 2033; an input end of the second not gate 2033 is used as an input end of the first transmission sub-module 2031, an output end of the second not gate 2033 is used as an output end of the first transmission sub-module 2031, an input end of the third not gate 2035 is used as an input end of the second transmission sub-module 2032, and an output end of the third not gate 2035 is used as an output end of the second transmission sub-module 2032.

It should be noted that, as shown in fig. 8 or fig. 9, in the first transmission submodule 2031, the first nand gate 2034 and the second not gate 2033 are connected end to end, a second input end of the first nand gate 2034 is connected to the PupMid node, and an output end thereof is connected to the PupMid node.

The first nand gate 2034 receives, via the second input terminal, the initial target data signal output by the second not gate 2033, and also receives, via the first input terminal, a transfer control signal (also called DQ reset N, dqRstN) which can control whether data can be normally transferred by the first transfer submodule 2031. When the transmission control signal is at a high level (logic "1"), data can be normally transmitted, and when the transmission control signal is at a low level (logic "0"), data cannot be normally transmitted. In this way, the embodiment of the disclosure can also control whether the intermediate data signal is normally transmitted as the initial target data signal through the first nand gate 2034 and the transmission control signal, so as to increase the flexibility of data conversion, and avoid the problems of circuit interference and the like caused by data being transmitted incorrectly under the condition that data does not need to be transmitted.

That is, when the level state of the transmission control signal is a high level, the data transmission is not affected, and the first nand gate 2034 and the second nand gate 2033 form one latch to latch data. When the level state of the transmission control signal is low level, the PupMid node is always high level, and data cannot be normally transmitted.

As shown in fig. 8 or 9, in some embodiments, for the conversion module 201, the conversion module 201 may include a first conversion sub-module 2011, a second conversion sub-module 2012, a third conversion sub-module 2013, and a fourth conversion sub-module 2014, and the initial data signal may include first initial data, second initial data, third initial data, and fourth initial data, where:

the first conversion sub-module 2011 is configured to receive the first initial data and the first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data;

the second conversion sub-module 2012 is configured to receive the second initial data and the second clock signal, and perform sampling processing on the second initial data according to the second clock signal to obtain second intermediate data;

the third conversion submodule 2013 is configured to receive third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

the fourth conversion sub-module 2014 is configured to receive the fourth initial data and the fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are respectively 0 degree, 90 degrees, 180 degrees and 270 degrees, and the first intermediate data, the second intermediate data, the third intermediate data and the fourth intermediate data form an intermediate data signal.

It should be noted that, as shown in fig. 8 or fig. 9, taking an example that the initial data signal includes four parallel data paths, at this time, the conversion module 201 correspondingly includes four conversion sub-modules (also referred to as P2S4tol sub-circuits) respectively configured to perform sampling processing on the four parallel data paths to output four intermediate data paths to form an intermediate data signal. The output end of the first conversion submodule 2011, the output end of the second conversion submodule 2012, the output end of the third conversion submodule 2013 and the output end of the fourth conversion submodule 2014 are connected to the PupMid node, and serve as the output end of the conversion module 201, so as to output an intermediate data signal.

It should be further noted that, in each conversion submodule, the clock signal is used to control the sampling time of the corresponding initial data, so as to ensure the timing between the output four intermediate data to form the intermediate data signal. For example, fig. 10 shows a specific structural diagram of a conversion module 201 according to an embodiment of the present disclosure, where the conversion module 201 may further include a clock signal generator 2015, the clock signal generator 2015 receives the first clock signal (SedCKER), the second clock signal (SedCKEF), the third clock signal (SedCKER), and the fourth clock signal (SedCKEF), generates the first clock selection signal (SedCKERN) according to a rising edge of the first clock signal (SedCKER), generates the second clock selection signal (SedCKEFN) according to a rising edge of the second clock signal (SedCKEF), generates the third clock selection signal (SedCKERN) according to a rising edge of the third clock signal (SedCKER), generates the fourth clock selection signal (SedCKEFN) according to a rising edge of the fourth clock signal (SedCKEF), and a pulse width of each clock selection signal is smaller than a pulse width of the corresponding clock signal. The signal timing of each clock signal and the clock selection signal can be referred to fig. 10.

The first conversion sub-module 2011 may include a first flip-flop (DFF 1) and a first switch (S1), the second conversion sub-module 2012 may include a second flip-flop (DFF 2) and a second switch (S2), the third conversion sub-module 2013 may include a third flip-flop (DFF 3) and a third switch (S3), and the fourth conversion sub-module 2014 may include a fourth flip-flop (DFF 4) and a fourth switch (S4).

In the first conversion sub-module 2011, the first flip-flop DFF1 samples the first initial data DataER at a rising edge of the first clock signal SedCKER, and the first switch S1 is closed during a high state of the first selection clock signal SedCKERN, so that the sampled signal obtains the first intermediate data D1' through the first switch S1. Similarly, in the second conversion sub-module 2012, the second flip-flop DFF2 samples the second initial data DataEF at the rising edge of the second clock signal SedCKEF, and during the period that the second selection clock signal SedCKEFN is in the high level state, the second switch S2 is closed, so that the sampled signal obtains the second intermediate data D2' through the second switch S2; in the third conversion submodule 2013, the third flip-flop DFF3 samples the third initial data DataOR at a rising edge of the third clock signal SedCKOR, and during a high state of the third selection clock signal SedCKORN, the third switch S3 is closed, so that the sampled signal gets the third intermediate data D3' through the third switch S3; in the fourth conversion sub-module 2014, the fourth flip-flop DFF4 samples the fourth initial data DataOF at the rising edge of the fourth clock signal SedCKOF, and the fourth switch S4 is closed during the high state of the fourth selection clock signal SedCKOFN, so that the sampled signal obtains the fourth intermediate data D4' through the fourth switch S4.

As shown in fig. 10 and 11, due to the timing difference between the four clock selection signals, after sampling and outputting the parallel first initial data DataER, second initial data DataEF, third initial data DataOR, and fourth initial data DataOF, the four intermediate data may be sequentially output, and finally, a serial intermediate data signal may be obtained at the PupMid node.

Further, the embodiment of the present disclosure can also be applied to a scenario in which a difference exists. As shown in fig. 12, in some embodiments, the conversion module 201 includes a first conversion module 204 and a second conversion module 205, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, wherein:

the first conversion module 204 is configured to receive a first initial data signal, and perform parallel-to-serial conversion on the first initial data signal to obtain a first intermediate data signal;

the second conversion module 205 is configured to receive the second initial data signal, and perform parallel-to-serial processing on the second initial data signal to obtain a second intermediate data signal.

It should be noted that, in the embodiment of the present disclosure, the initial data signal may be a pair of differential signals (or called inverted signals), including a first initial data signal and a second initial data signal, where both the first initial data signal and the second initial data signal are parallel data signals; the first conversion module 204 processes the first initial data signal into a serial first intermediate data signal, and the second conversion module 205 processes the second initial data signal into a serial second intermediate data signal. It is understood that the first intermediate data signal and the second intermediate data signal are also a pair of differential signals, and the level states of the two signals are opposite.

At this time, as shown in fig. 12, one end of the adjustment module 202 is connected to the output terminal of the first conversion module 204, and the other end of the adjustment module 202 is connected to the output terminal of the second conversion module 205. The second intermediate data signal is used as a compensation signal for compensating the first intermediate data signal, and the first intermediate data signal is used as a compensation signal for compensating the second intermediate data signal. That is, the compensation signal includes a first intermediate data signal and a second intermediate data signal, wherein:

the adjusting module 202 is configured to perform compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce a signal swing of the second intermediate data signal; and performing compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

It can be seen that, for an application scenario in which a difference exists, the embodiment of the present disclosure may further connect the adjusting module 202 between two differential signals (the first intermediate data signal and the second intermediate data signal), so as to achieve simultaneous reduction of signal swing of the first intermediate data signal and the second intermediate data signal.

Accordingly, the target data signal comprises a first target data signal and a second target data signal, the transmission module 203 comprises a first transmission module 206 and a second transmission module 207, wherein:

the first transmission module 206 is configured to perform drive enhancement processing on the compensated first intermediate data signal to obtain a first target data signal;

and the second transmission module 207 is configured to perform drive enhancement processing on the compensated second intermediate data signal to obtain a second target data signal.

One end of the adjusting module 202 is connected to the output end of the first converting module 204 and the input end of the first transmitting module 206, respectively, and the other end of the adjusting module 202 is connected to the output end of the second converting module 205 and the input end of the second transmitting module 207, respectively.

As shown in fig. 12, a connection node between the first conversion module 204 and the first transmission module 206 is referred to as a PupMid1 node, and a connection node between the second conversion module 205 and the second transmission module 207 is referred to as a PupMid2 node. The adjusting module 202 is connected between the PupMid1 node and the PupMid2 node, and not only can perform compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal, that is, reduce the signal swing of the PupMid1 node, but also can perform compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal, that is, reduce the signal swing of the PupMid2 node, then obtain the first target data signal (also written as DataPu) through the first transmission module 206, obtain the second target data signal (also written as DataPd) through the second transmission module 207, and it can be understood that the first target data signal and the second target data signal are also a pair of differential signals, and are opposite-phase signals. Finally, the first transmission path (the first conversion module 204 and the second transmission module 206) and the second transmission path (the second conversion module 205 and the second transmission module 207) can transmit high-frequency signals, and the high-frequency performance of the circuit is effectively improved.

Further, for an application scenario in which a difference exists, taking the adjustment module 202 including the transmission gate module 2021 and the first not gate 2022 as an example, referring to fig. 13, a specific structural diagram of a data conversion circuit provided in the embodiment of the present disclosure is shown. As shown in fig. 13, the first conversion module 204 and the second conversion module 205 have the same structure and function as the conversion module 201 in fig. 8 or fig. 9, and the specific structure and function thereof can be understood by referring to the description of fig. 10 and fig. 11. Meanwhile, the first conversion module 204 and the second conversion module 205 may also share the same clock signal generator 2015; the first transmission module 206 and the second transmission module 207 have the same structure and function as the transmission module 203 in fig. 8 or 9. The detailed description of the functions is omitted here.

The difference of the differential scenario is in the connection manner of the adjustment module 202, and at this time, the adjustment module 202 is connected between the PupMid1 node and the PupMid2 node, so that the signal swing of the PupMid1 node can be reduced according to the second intermediate data signal, and the signal swing of the PupMid2 node can be reduced according to the first intermediate data signal.

The four initial data received by the first conversion module 204 are respectively: the four initial data received by the second conversion module 205 are DataERN, dataEFN, dataORN, and DataOFN, respectively, and it can be understood that the DataER and DataERN are a pair of inverted signals, and the clock signal for sampling the pair of inverted signals is setcker; the DataEF and DataEFN are a pair of inverted signals, and the clock signals for sampling the inverted signals are both SedCKEF; dataOR and DataORN are a pair of inverted signals, and the clock signals for sampling the inverted signals are both SedCKOR; dataOF and DataOFN are a pair of inverted signals, and the clock signal for sampling the pair of inverted signals is SedCKOF.

Similarly, for an application scenario in which there is a difference, the adjustment module 202 may be implemented by the resistor module 2023, and at this time, the resistor module 2023 is connected between the PupMid1 node and the PupMid2 node. Or, two adjusting modules 202 may be further arranged according to the connection manner of fig. 8 or fig. 9 to reduce signal swing of the PupMid1 node and the PupMid2 node, which is also beneficial to transmitting high-frequency data and improving the high-frequency performance of the circuit. For a more detailed description of fig. 13, reference may be made to the aforementioned fig. 8 to 10, which are not repeated herein.

In short, the data conversion circuit provided by the embodiment of the disclosure can improve the conversion rate of parallel data to serial data, in order to improve the high-frequency performance of the data conversion circuit, the high-frequency performance is improved by reducing the swing of the PupMid node, and for an application scenario without difference, the high-frequency performance is mainly realized by an adjustment module bridged between the PupMid node and the PupMid node. In a high-speed mode, the HSEn signal is high, and a transmission pipe is conducted, so that the swing amplitude of a PupMid node is reduced, the bandwidth of a signal is increased, and the purpose of transmitting high-frequency data is achieved; or, by a resistor module connected across the PupMid node and the PupMidN node. In a differential scenario, because the same data is output in a differential mode, when the PupMid1 node is at a High level (High), the PdnMid2 node is at a Low level (Low), and therefore, the voltage swing of the popmid 1 node and the PdnMid2 node can be reduced by adding a transmission pipe between the popmid 1 node and the PdnMid2 node, and the purpose of transmitting High-speed data is achieved.

The embodiment of the disclosure provides a data conversion circuit, which includes a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used for receiving a compensation signal, and the other end of the adjustment module is connected with the output end of the conversion module and the input end of the transmission module respectively, wherein: the conversion module is used for receiving the initial data signal and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal; the adjusting module is used for compensating the intermediate data signal according to the compensation signal so as to reduce the signal swing amplitude of the intermediate data signal; and the transmission module is used for carrying out drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal. Therefore, the adjustment module is arranged in the data conversion circuit and compensates the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, namely the signal swing of a connecting node of the conversion module and the transmission module is reduced, the signal bandwidth is increased, the purpose of transmitting high-frequency data is finally achieved, and the high-frequency performance of the circuit is improved.

In another embodiment of the present disclosure, referring to fig. 14, a flowchart of a data conversion method provided in an embodiment of the present disclosure is shown. As shown in fig. 14, the method may include:

s1001: the conversion module receives the initial data signal and carries out parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal.

S1002: the compensation signal is received through the adjusting module, and the intermediate data signal is compensated according to the compensation signal so as to reduce the signal swing of the intermediate data signal.

S1003: and receiving the intermediate data signal after compensation processing through the transmission module, and performing drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

In some embodiments, the compensation processing of the intermediate data signal according to the compensation signal includes: when the enable control signal is in an effective state, the transmission gate module is conducted so as to perform compensation processing on the intermediate data signal according to the compensation signal; or, when the enable control signal is in an invalid state, the transmission gate module is turned off.

In some embodiments, the enable control signal includes a first enable control signal and a second enable control signal, the method may further include: and receiving the first enabling control signal through the first NOT gate, and performing phase inversion processing on the first enabling control signal to obtain a second enabling control signal.

In some embodiments, the compensation processing of the intermediate data signal according to the compensation signal includes: and compensating the intermediate data signal through the resistance module according to the compensation signal so as to reduce the signal swing of the intermediate data signal.

In some embodiments, performing a drive enhancement process on the compensated intermediate data signal to obtain a target data signal includes:

performing inverse phase processing on the intermediate data signal after compensation processing through a first transmission submodule to obtain an initial target data signal;

and performing phase inversion processing on the initial target data signal through the second transmission submodule to obtain a target data signal.

In some embodiments, the method may further comprise: the initial target data signal is determined as a compensation signal.

In some embodiments, the parallel-to-serial conversion of the initial data signal to obtain the intermediate data signal includes:

receiving first initial data and a first clock signal through a first conversion sub-module, and sampling the first initial data according to the first clock signal to obtain first intermediate data;

receiving second initial data and a second clock signal through a second conversion submodule, and sampling the second initial data according to the second clock signal to obtain second intermediate data;

receiving third initial data and a third clock signal through a third conversion sub-module, and sampling the third initial data according to the third clock signal to obtain third intermediate data;

receiving fourth initial data and a fourth clock signal through a fourth conversion sub-module, and sampling the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

In some embodiments, the initial data signal includes a first initial data signal and a second initial data signal, the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, and the parallel-to-serial conversion of the initial data signals to obtain the intermediate data signal includes:

receiving a first initial data signal through a first conversion module, and performing parallel-to-serial conversion on the first initial data signal to obtain a first intermediate data signal;

and receiving the second initial data signal through the second conversion module, and performing parallel-to-serial conversion on the second initial data signal to obtain a second intermediate data signal.

In some embodiments, the compensation signal includes a first intermediate data signal and a second intermediate data signal, and performing compensation processing on the intermediate data signal according to the compensation signal includes:

compensating the second intermediate data signal according to the first intermediate data signal through an adjusting module to reduce the signal swing of the second intermediate data signal; and performing compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

In some embodiments, the target data signal includes a first target data signal and a second target data signal, and performing a drive enhancement process on the compensated intermediate data signal to obtain the target data signal includes:

performing drive enhancement processing on the compensated first intermediate data signal through a first transmission module to obtain a first target data signal;

and performing drive enhancement processing on the compensated second intermediate data signal through a second transmission module to obtain a second target data signal.

It should be noted that the data conversion method provided by the embodiment of the present disclosure can be applied to the data conversion circuit 20 described in the foregoing embodiment, and for details not disclosed in the embodiment of the present disclosure, please refer to the description of the foregoing embodiment for understanding.

The embodiment of the disclosure provides a data conversion method, which performs compensation processing on an intermediate data signal according to a compensation signal, and can reduce the signal swing of the intermediate data signal, so as to increase the signal bandwidth, finally achieve the purpose of transmitting high-frequency data, and improve the high-frequency performance of a circuit.

In another embodiment of the present disclosure, referring to fig. 15, a schematic structural diagram of a semiconductor memory provided in an embodiment of the present disclosure is shown. As shown in fig. 15, the semiconductor memory 150 may include at least the data conversion circuit 20 according to any one of the foregoing embodiments.

In some embodiments, semiconductor memory 150 is a dynamic random access memory DRAM chip.

In the embodiment of the present disclosure, for the DRAM, not only the memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, but also the memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5 may be met, which is not limited herein.

In the embodiment of the present disclosure, for the semiconductor memory 150, since it includes the data conversion circuit 20 described in the foregoing embodiment, the signal bandwidth is increased, and finally the purpose of transmitting high frequency data is achieved, thereby improving the performance of the memory.

The above description is only an example embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that, in the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments.

Features disclosed in several of the product embodiments provided in this disclosure may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data conversion circuit is characterized by comprising a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used for receiving a compensation signal, and the other end of the adjustment module is respectively connected with the output end of the conversion module and the input end of the transmission module, wherein:

2. The data conversion circuit of claim 1, wherein the adjustment module comprises a transmission gate module, one end of the transmission gate module is configured to receive the compensation signal, the other end of the transmission gate module is connected to the output end of the conversion module and the input end of the transmission module, respectively, and a control end of the transmission gate module is configured to receive an enable control signal, wherein:

3. The data conversion circuit of claim 2, wherein the enable control signal comprises a first enable control signal and a second enable control signal, wherein:

the transmission gate module comprises an NMOS tube and a PMOS tube, wherein the first end of the NMOS tube and the first end of the PMOS tube are connected to serve as one end of the transmission gate module, and the second end of the NMOS tube and the second end of the PMOS tube are connected to serve as the other end of the transmission gate module;

4. The data conversion circuit of claim 3, wherein the adjustment module further comprises a first not gate, an input terminal of the first not gate is connected to the gate terminal of the NMOS transistor, an output terminal of the first not gate is connected to the gate terminal of the PMOS transistor, wherein:

5. The data conversion circuit of claim 1, wherein the adjustment module comprises a resistor module, one end of the resistor module is configured to receive the compensation signal, and the other end of the resistor module is connected to the output end of the conversion module and the input end of the transmission module, respectively, wherein:

6. The data conversion circuit of claim 2, wherein the transmission module comprises a first transmission submodule and a second transmission submodule, an input of the first transmission submodule being connected to an output of the conversion module, an output of the first transmission submodule being connected to an input of the second transmission submodule, wherein:

7. The data conversion circuit of claim 6, wherein one end of the scaling module is connected to the output of the first transmission submodule and the other end of the scaling module is connected to the input of the first transmission submodule, wherein:

8. The data conversion circuit of claim 6, wherein the first transmission submodule comprises a second not gate and a first nand gate, the second transmission submodule comprises a third not gate, a first input of the first nand gate is used for receiving a transmission control signal, a second input of the first nand gate is connected with an output of the second not gate and an input of the third not gate, and an output of the first nand gate is connected with an input of the second not gate; the input end of the second not gate is used as the input end of the first transmission submodule, the output end of the second not gate is used as the output end of the first transmission submodule, the input end of the third not gate is used as the input end of the second transmission submodule, and the output end of the third not gate is used as the output end of the second transmission submodule.

9. The data conversion circuit of claim 1, wherein the conversion module comprises a first conversion sub-module, a second conversion sub-module, a third conversion sub-module, and a fourth conversion sub-module, and the initial data signal comprises first initial data, second initial data, third initial data, and fourth initial data, wherein:

10. The data conversion circuit of claim 1, wherein the conversion module comprises a first conversion module and a second conversion module, the initial data signal comprises a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal comprises a first intermediate data signal and a second intermediate data signal, wherein:

11. The data conversion circuit of claim 10, wherein the compensation signal comprises the first intermediate data signal and the second intermediate data signal, wherein:

12. The data conversion circuit of claim 11, wherein the target data signal comprises a first target data signal and a second target data signal, and the transmission module comprises a first transmission module and a second transmission module, wherein:

13. The data conversion circuit according to claim 12, wherein one end of the adjusting module is connected to the output end of the first converting module and the input end of the first transmitting module, respectively, and the other end of the adjusting module is connected to the output end of the second converting module and the input end of the second transmitting module, respectively.

14. The data conversion circuit according to any one of claims 1 to 13, wherein the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are serial data signals.

15. A method of data conversion, the method comprising:

16. A memory comprising a data conversion circuit as claimed in any one of claims 1 to 14.