CN115694484A - Binary weighted array capacitor grouping method and apparatus - Google Patents
Binary weighted array capacitor grouping method and apparatus Download PDFInfo
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Abstract
The embodiment of the application provides a capacitance grouping method and a capacitance grouping device for a binary weighted capacitor array, and particularly sequentially groups unit capacitances in the capacitor array into a high-order capacitor group and a low-order capacitor group according to a double rule; detecting a mismatch code between the capacitor banks; the packet is adjusted based on the mismatch code and a subsequent packet is completed. According to the method and the device, the capacitors are grouped and adjusted according to the mismatch codes, so that the precision of the twofold relation between adjacent capacitor groups is improved, and the analog-to-digital conversion precision of the charge redistribution type successive approximation analog-to-digital converter is improved.
Description
Technical Field
The present application relates to the field of electronic technologies, and in particular, to a method and an apparatus for grouping capacitors of a binary weighted capacitor array.
Background
The analog-to-digital converter is used for converting an analog quantity into a digital quantity, and is an important bridge for connecting an analog signal and a digital signal, wherein the charge redistribution type successive approximation analog-to-digital converter is widely applied due to the comprehensive advantages of medium conversion precision, medium conversion speed, low power consumption and low cost.
The charge redistribution type successive approximation analog-to-digital converter mainly comprises a digital-to-analog converter, a comparator, a digital control part and other analog circuits, and the core of the charge redistribution type successive approximation analog-to-digital converter is the digital-to-analog converter, the comparator and the digital control part. The successive approximation analog-to-digital converter uses a binary search algorithm to enable the output of the digital-to-analog converter to successively approximate the input analog signal, and for the N-bit successive approximation analog-to-digital converter, at least N conversion cycles are needed to complete the analog-to-digital conversion process.
As one of the key units of the charge redistribution type successive approximation analog-to-digital converter, the accuracy of the capacitor bank in the binary weighted capacitor array directly determines the accuracy of the whole analog-to-digital converter. However, due to the limitation of errors in the capacitor manufacturing process and the influence of parasitic capacitance caused by devices and traces, the quadratic relationship between adjacent capacitor sets in the binary weighted capacitor array is not accurate enough, thereby reducing the analog-to-digital conversion accuracy of the charge redistribution type successive approximation analog-to-digital conversion.
Disclosure of Invention
In order to solve the above problems, the present application provides a capacitance grouping method and apparatus for a binary weighted capacitor array to improve the analog-to-digital conversion accuracy of a charge redistribution type successive approximation analog-to-digital converter.
In view of the above, the present application discloses a capacitance grouping method for a binary weighted capacitor array, which is applied to a charge redistribution type successive approximation analog-to-digital converter, the charge redistribution type successive approximation analog-to-digital converter including a plurality of segments of capacitor arrays, each segment of the capacitor arrays including a plurality of unit capacitances, the capacitance grouping method including the steps of:
grouping the plurality of unit capacitors in the capacitor array into a high-order capacitor bank and a low-order capacitor bank according to a double rule;
for each grouping, detecting mismatch voltage between the high-order capacitor bank and the low-order capacitor bank to obtain mismatch codes corresponding to the mismatch voltage;
and adjusting the grouping based on the relation between the mismatch code and a preset target value, and completing all the grouping in sequence.
Optionally, the detecting a mismatch voltage between the high-side capacitor bank and the low-side capacitor bank includes:
and detecting the mismatch voltage between the high-order capacitor bank and the low-order capacitor bank by using the low order of the analog-to-digital converter.
Optionally, the adjusting the packet based on the relationship between the mismatch code and a preset target value, and completing all packets in sequence, includes the steps of:
comparing the mismatch code to the target value;
if the mismatch code is larger than the target value, adjusting the composition of the high-order capacitor bank and the composition of the low-order capacitor bank, and then returning to the step of detecting the mismatch voltage;
if the mismatch code is less than or equal to the target value, judging whether the low-order capacitor bank is the last group; if the lower capacitor bank is not the last one, returning to the step of grouping the plurality of unit capacitors in the capacitor array into a higher capacitor bank and a lower capacitor bank according to a doubling rule;
if the lower capacitor bank is the last packet, ending the packet and recording the packet condition.
Optionally, the adjusting the composition of the high-side capacitor bank and the composition of the low-side capacitor bank includes:
and adjusting the composition of the high-order capacitor bank and the composition of the low-order capacitor bank by using a cyclic shift method.
Optionally, the determining whether the low-side capacitor bank is the last group includes:
and judging whether the low-order capacitor bank is a single unit capacitor or not, if so, judging that the low-order capacitor bank is the last group, and if not, judging that the low-order capacitor bank is not the last group.
There is also provided a capacitance grouping apparatus of a binary weighted capacitance array applied to a charge redistribution type successive approximation analog-to-digital converter including a plurality of segments of capacitor arrays each including a plurality of unit capacitances, the capacitance grouping apparatus including, for each segment of the capacitor arrays:
a first grouping module configured to group the plurality of unit capacitances in the capacitor array into a higher order capacitor group and a lower order capacitor group on a double-rule basis;
a mismatch code detection module configured to detect, for each packet, a mismatch voltage between the high-order capacitor bank and the low-order capacitor bank using a low-order bit of the analog-to-digital converter, and obtain a mismatch code corresponding to the mismatch voltage;
and the second grouping module is configured to adjust the grouping based on the relation between the mismatch code and a preset target value and complete all the grouping in sequence.
Optionally, the mismatch code detection module is configured to detect a mismatch voltage between the high-order capacitor bank and the low-order capacitor bank by using a low order of the analog-to-digital converter.
8. The capacitive grouping apparatus of claim 6 wherein the second grouping module comprises:
a first judgment unit configured to compare the mismatch code with a preset target value;
a group adjusting unit configured to adjust the composition of the higher-order capacitor bank and the composition of the lower-order capacitor bank if the mismatch code is greater than the target value, and then control the mismatch code to perform detection of the mismatch voltage;
a second determination unit configured to determine whether the lower capacitor bank is a last bank if the mismatch code is less than or equal to the target value; if the lower capacitor bank is not the last group, controlling a first grouping module to perform grouping of the plurality of unit capacitors in the capacitor array into a higher capacitor bank and a lower capacitor bank according to a doubling rule;
a packet recording unit configured to end a packet and record a packet condition if the lower capacitor bank is the last packet.
Optionally, the grouping adjustment unit is configured to adjust the composition of the upper capacitor bank and the composition of the lower capacitor bank by using a cyclic shift method.
Optionally, the second determining unit is configured to determine whether the lower capacitor bank is a single unit capacitor, determine that the lower capacitor bank is the last group if the lower capacitor bank is a single unit capacitor, and determine that the lower capacitor bank is not the last group if the lower capacitor bank is not a single unit capacitor.
According to the technical scheme, the capacitor grouping method and device of the binary weighted capacitor array are provided, and specifically, unit capacitors in the capacitor array are sequentially grouped into a high-order capacitor bank and a low-order capacitor bank according to a double rule; detecting a mismatch code between the capacitor banks; the packet is adjusted based on the mismatch code and a subsequent packet is completed. According to the method and the device, the capacitors are grouped and adjusted according to the mismatch codes, so that the precision of the twofold relation between adjacent capacitor groups is improved, and the analog-to-digital conversion precision of the charge redistribution type successive approximation analog-to-digital converter is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for grouping capacitors of a binary weighted capacitor array according to an embodiment of the present application;
FIG. 2 is a circuit diagram of a binary-weighted capacitor array according to an embodiment of the present application;
FIG. 3 is a schematic diagram of the connection of a binary weighted capacitor array according to an embodiment of the present application;
FIG. 4 is a schematic diagram of the connection of a binary weighted capacitor array according to an embodiment of the present application;
fig. 5 is a block diagram of a capacitance grouping apparatus of a binary weighted capacitor array according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example one
Fig. 1 is a flowchart of a capacitance grouping method for a binary weighted capacitor array according to an embodiment of the present application.
The capacitance grouping method provided by the embodiment is applied to a charge redistribution type successive approximation analog-to-digital converter, which at least comprises a multi-segment capacitor array, a digital-to-analog converter, a comparator and a digital control part, wherein each segment of capacitor array comprises a plurality of unit capacitances. In this embodiment, the capacitor grouping method is described by taking a three-segment capacitor array as an example, where each segment in the three-segment capacitor array is four bits, where MSB is the highest segment, SMSB is the middle end, and LSB is the lowest segment. MSB and SMSB respectively comprise 15 unit capacitors, LSB comprises 16 unit capacitors, and as shown in FIG. 2, switch M 0 ～M 14 、L 0 ～L 14 、SL 0 ～SL 15 Respectively controlling unit capacitor grounding G nd Or to a reference voltage V ref Switch SL 0 And the capacitor is used for controlling the capacitance of 1C, and the capacitor only participates in sampling and does not participate in conversion.
As shown in fig. 1, for each of the MSBs, SMSBs and LSBs in the three-segment capacitor array, for example, the highest segment MSB, the capacitance grouping method provided by the present embodiment includes the following steps:
s1, sequentially dividing unit capacitors in the capacitor array into a high-order capacitor combined low-order capacitor group according to a two-fold rule.
For the MSB, the sequential grouping means that 15 unit capacitors and lower equivalent unit capacitors are first divided into a higher capacitor group including 8 unit capacitors and a lower capacitor group including 8 unit capacitors, that is, unit capacitors corresponding to M7 to M14 are grouped into a higher capacitor group, and unit capacitors corresponding to M00 and M0 to M6 are grouped into a lower capacitor group, where M00 is an equivalent capacitor of SMSB and LSB, and the equivalent capacitors do not participate in adjustment.
At the time of the second grouping, 8 unit capacitors in the lower capacitor group are grouped into a higher capacitor group including 4 unit capacitors and a lower capacitor group including 4 unit capacitors (including the equivalent capacitor M00). At the third grouping, 4 unit capacitances in the lower capacitor group are grouped into an upper capacitor group including 2 unit capacitances and a lower capacitor group including 2 unit capacitances (including an equivalent capacitance M00). After the third grouping is completed, the other unit capacitor in the lower capacitor group except the equivalent capacitor M00 is the last grouping. Thereby realizing twice regular grouping.
It is worth noting that, with subsequent adjustments, the resulting packets may not be the same as the original packets, but still remain twice as many, i.e., 32-16-8-4-2-1.
Specifically, the precharging is first performed at the beginning of a packet, where the upper plates of all capacitors are connected to a common mode level V as shown in FIG. 3 cm The lower polar plate of the unit capacitor corresponding to 8 capacitance switches M7-M14 in the MSB section is connected with G nd The lower polar plates of the unit capacitors corresponding to the other seven capacitors and the capacitor switches M0 to M6 are connected with V ref The lower electrode plates of all unit capacitors in SMSB and LSB sections are also connected with V ref 。
Then the charge redistribution phase follows, as shown in FIG. 4, the upper plates of all the unit capacitors and the common mode level V cm Disconnecting, before MSB segment lower pole plate connecting G nd Eight unit capacitors of the capacitor are changed into a connection V ref MSB connected to V ref Seven unit capacitors and SMSB and LSB all capacitors are connected with G nd . I.e. the first time the packet is implemented.
And S2, detecting mismatch voltage between the high-order capacitor bank and the low-order capacitor bank to obtain a mismatch code.
A mismatch voltage is generated at the output of the dac and then detected by the lower bits (e.g. the lower four bits) of the adc, which has a precondition that the mismatch voltage caused by the capacitance mismatch is less than 0.5LSB (the minimum resolution voltage of the adc) for the adc, and is easily satisfied for the lower bits, e.g. the capacitance mismatch of the highest bit is required to be less than 1/4096 for a 12-bit adc, and the capacitance mismatch of the lowest bit is required to be less than 1/4092, which can ensure the sufficient accuracy for the lower bits of the adc under the conditions of the prior art. The mismatch voltage is measured by using the lower bits of the analog-to-digital converter, a mismatch code can be obtained, the size of the mismatch code reflects the size of capacitor mismatch, the larger the mismatch code is, the larger the capacitor mismatch is, and the smaller mismatch code can be obtained through different capacitor combinations, so that the precision of the analog-to-digital converter is improved.
And S3, adjusting the packet based on the mismatch code and finishing the subsequent packet.
The mismatch code is compared with a preset target value, the upper high-order capacitor bank and the lower-order capacitor bank are adjusted according to a comparison result, and the subsequent grouping of the lower-order capacitor banks is sequentially completed, wherein the specific process is as follows:
and S31, judging whether the mismatch code is larger than a preset target value or not.
The mismatch code is compared with a preset target value, the relationship between the mismatch code and the preset target value is judged, and subsequent operation is executed according to the relationship between the mismatch code and the preset target value. If the mismatch code is larger than the target value, executing step S32; if the mismatch code is less than or equal to the target value, step S33 is performed.
And S32, adjusting the composition of the high-order capacitor bank and the composition of the low-order capacitor bank.
That is, when the mismatch code is larger than the target value, the unit capacitors forming the higher capacitor bank and the unit capacitors forming the lower capacitor bank are adjusted, where the adjustment may be regarded as interchange of the unit capacitors between the two capacitor banks, specifically, the capacitor banks of the unit capacitors are adjusted by cyclic shift, that is, the capacitor banks are regrouped by left shift or right shift. And then returns to step S2 above to reacquire the mismatch code between the two capacitor banks.
For example, the capacitors corresponding to the capacitor switches M7 to M14 are shifted to the left by one, the unit capacitors corresponding to M6 to M13 are regarded as the high-order capacitor group, and the units corresponding to M00, M0 to M5, and M14 are regarded as the low-order capacitor group. In addition, the composition of the high-order capacitor bank and the composition of the low-order capacitor bank can be adjusted by carrying out the second grouping and the third grouping on the capacitor banks according to the same method and principle.
And S33, judging whether the low-order capacitor bank is the last group.
Namely, after the mismatching code is judged each time, whether the low-order capacitor bank is the last group is judged, namely whether the third grouping is finished is judged, and the low-order capacitor bank comprising 1 unit capacitor is obtained. Specifically, the method of judging the number of unit capacitors included in the lower capacitor group determines whether it is the last group, and if it is 1, it is determined to be the last group, and if it is not 1, it is determined not to be the last group.
And S34, recording grouping conditions of the binary weighted capacitor array.
If the low-order capacitor group is the last group, the grouping is finished, and the grouping information is recorded by the storage device, so that the grouping of the unit capacitors is performed according to the grouping information when the analog-to-digital conversion is performed subsequently, and the high-precision analog-to-digital conversion is realized. In addition, if the lower capacitor bank is not the last one, the procedure returns to step S1, and the subsequent second grouping or third grouping is performed in order.
As can be seen from the above technical solutions, the present embodiment provides a capacitance grouping method for a binary weighted capacitor array, specifically, sequentially grouping unit capacitances in a capacitor array into a high-order capacitor bank and a low-order capacitor bank according to a double rule; detecting a mismatch code between the capacitor banks; the packet is adjusted based on the mismatch code and a subsequent packet is completed. According to the capacitor grouping adjustment method and device, the capacitors are grouped and adjusted according to the mismatch codes, so that the precision of the twofold relation between adjacent capacitor groups is improved, and the analog-to-digital conversion precision of the charge redistribution type successive approximation analog-to-digital converter is improved.
The most significant influence on the accuracy of the analog-to-digital converter is the matching of the capacitance of the MSB section, particularly the matching of the capacitance of the most significant bit of the MSB section, so that the capacitance grouping can be mainly carried out on the MSB section, and certainly, the capacitance grouping can be carried out on other sections, so that the accuracy can be further improved. After the capacitors are grouped, for example, the unit capacitors corresponding to M7 to M14 are respectively a group, the unit capacitors corresponding to M6 to M3 are respectively a group, the unit capacitors corresponding to M2 to M1 are respectively a group, and the unit capacitors corresponding to M0 are a group, the grouping information can be fixed and written into nonvolatile memories such as FLASH and OTP, and the capacitors with small capacitor mismatch are fixedly grouped in the subsequent application without being grouped again each time, so that the application is convenient, and the accuracy of the analog-to-digital converter is improved.
Example two
Fig. 5 is a block diagram of a capacitance grouping apparatus of a binary weighted capacitor array according to an embodiment of the present application.
The capacitance grouping method provided by the embodiment is applied to a charge redistribution type successive approximation analog-to-digital converter, which at least comprises a multi-segment capacitor array, a digital-to-analog converter, a comparator and a digital control part, wherein each segment of capacitor array comprises a plurality of unit capacitances. In this embodiment, the capacitor grouping method is described by taking a three-segment capacitor array as an example, each segment in the three-segment capacitor array is four bits, where MSB is the highest segment, SMSB is the middle end, and LSB is the lowest segment. MSB and SMSB respectively comprise 15 unit capacitors, LSB comprises 16 unit capacitors, and as shown in FIG. 2, switch M 0 ～M 14 、L 0 ～L 14 、SL 0 ～SL 15 Respectively controlling unit capacitanceGround G nd Or to a reference voltage V ref Switch SL 0 And the compensation capacitor is used for controlling the size of 1C, and the compensation capacitor only participates in sampling and does not participate in conversion.
As shown in fig. 5, the capacitance grouping apparatus provided in the present embodiment includes a first grouping module 10, a mismatch code detection module 20, and a second grouping module 30 for each of the MSBs, SMSBs, and LSBs, for example, the uppermost MSB, in the three-segment capacitor array.
The first grouping module is used for sequentially dividing unit capacitors in the capacitor array into a high-order capacitor group and a low-order capacitor group according to a double rule.
For the MSB, the sequential grouping means that 15 unit capacitors and lower equivalent unit capacitors are first divided into a higher capacitor group including 8 unit capacitors and a lower capacitor group including 8 unit capacitors, that is, unit capacitors corresponding to M7 to M14 are grouped into a higher capacitor group, and unit capacitors corresponding to M00 and M0 to M6 are grouped into a lower capacitor group, where M00 is an equivalent capacitor of the SMSB and LSB, and the equivalent capacitors do not participate in adjustment.
At the time of the second grouping, 8 unit capacitors in the lower capacitor group are grouped into a higher capacitor group including 4 unit capacitors and a lower capacitor group including 4 unit capacitors (including the equivalent capacitor M00). At the third grouping, 4 unit capacitances in the lower capacitor group are grouped into an upper capacitor group including 2 unit capacitances and a lower capacitor group including 2 unit capacitances (including an equivalent capacitance M00). After the third grouping is completed, the other unit capacitor in the lower capacitor group except the equivalent capacitor M00 is the last grouping. Thereby implementing an 8-4-2-1 packet.
It is worth noting that, through subsequent adjustment, the resulting packets may not be the same as the original packets, but the number remains 8-4-2-1.
Specifically, the precharging is first performed at the beginning of a packet, where the upper plates of all capacitors are connected to a common mode level V as shown in FIG. 3 cm The lower pole plate of the unit capacitor corresponding to 8 capacitance switches M7-M14 in the MSB section is connected with G nd Seven othersThe lower polar plate of the unit capacitor corresponding to the capacitors and the capacitor switches M0-M6 is connected with V ref The lower polar plates of all unit capacitors in the SMSB and LSB sections are also connected with V ref 。
Then the charge redistribution phase follows, as shown in FIG. 4, the upper plates of all the unit capacitors and the common mode level V cm Disconnecting, the lower pole plate of the MSB segment before G nd Eight unit capacitors of the capacitor are changed into a connection V ref MSB connected to V ref The lower plates of seven unit capacitors and all capacitors in SMSB and LSB segments are connected with G nd . I.e. the first time the packet is implemented.
The mismatch code detection module is used for detecting mismatch voltage between the high-order capacitor bank and the low-order capacitor bank by using the low-order bits of the analog-to-digital converter to obtain a mismatch code.
A mismatch voltage is generated at the output of the dac and then detected by the lower bits (e.g. the lower four bits) of the adc, which has a precondition that the mismatch voltage caused by the capacitance mismatch is less than 0.5LSB (the minimum resolution voltage of the adc) for the adc, and is easily satisfied for the lower bits, e.g. the capacitance mismatch of the highest bit is required to be less than 1/4096 for a 12-bit adc, and the capacitance mismatch of the lowest bit is required to be less than 1/4092, which can ensure the sufficient accuracy for the lower bits of the adc under the conditions of the prior art. The mismatch voltage is measured by using the lower bits of the analog-to-digital converter, a mismatch code can be obtained, the size of the mismatch code reflects the size of capacitor mismatch, the larger the mismatch code is, the larger the capacitor mismatch is, and the smaller mismatch code can be obtained through different capacitor combinations, so that the precision of the analog-to-digital converter is improved.
The second grouping module is used for adjusting the grouping based on the mismatch code and completing the subsequent grouping. Specifically, the mismatch code is compared with a preset target value, the upper high-order capacitor bank and the lower-order capacitor bank are adjusted according to a comparison result, and the subsequent grouping of the lower-order capacitor bank is sequentially completed. The module specifically includes a first judging unit 31, a grouping adjusting unit 32, a second judging unit 33, and a grouping recording unit 34.
The first judging unit is used for judging whether the mismatch code is larger than a preset target value.
The mismatch code is compared with a preset target value, the relationship between the mismatch code and the preset target value is judged, and subsequent operation is executed according to the relationship between the mismatch code and the preset target value.
The grouping adjusting unit is used for adjusting the composition of the high-order capacitor bank and the composition of the low-order capacitor bank.
That is, when the mismatch code is larger than the target value, the unit capacitors forming the higher capacitor bank and the unit capacitors forming the lower capacitor bank are adjusted, where the adjustment is regarded as the interchange of the unit capacitors between the two capacitor banks, specifically, the capacitor bank of the unit capacitor is adjusted by a cyclic shift method. And then returns to step S2 above to reacquire the mismatch code between the two capacitor banks.
For example, the capacitors corresponding to the capacitor switches M7 to M14 are shifted to the left by one, the unit capacitors corresponding to M6 to M13 are regarded as the high-order capacitor group, and the units corresponding to M00, M0 to M5, and M14 are regarded as the low-order capacitor group. In addition, the composition of the high-order capacitor bank and the composition of the low-order capacitor bank can be adjusted by carrying out the second grouping and the third grouping on the capacitor banks according to the same method and principle.
The second judging unit is used for judging whether the low-order capacitor bank is the last group.
That is, after the mismatch code is determined each time, it is determined whether the low-order capacitor bank is the last one, that is, it is determined whether the third grouping is completed, and a low-order capacitor bank including 1 unit capacitor is obtained. Specifically, the method of judging the number of unit capacitors included in the lower capacitor group determines whether it is the last group, and if it is 1, it is determined to be the last group, and if it is not 1, it is determined not to be the last group.
The grouping recording unit is used for recording grouping requests, namely if the low-order capacitor bank is determined to be the last grouping through judgment, the grouping is indicated to be completed, the grouping is ended, and the grouping recording module records the grouping information by using the storage device so as to perform grouping on the unit capacitors according to the grouping information when analog-to-digital conversion is performed subsequently, thereby realizing high-precision analog-to-digital conversion. In addition, if the lower capacitor bank is not the last one, the procedure returns to step S1, and the subsequent second grouping or third grouping is performed in order.
It can be seen from the foregoing technical solutions that, the present embodiment provides a capacitance grouping apparatus for a binary weighted capacitor array, specifically, a unit capacitance in a capacitor array is sequentially grouped into a high-order capacitor bank and a low-order capacitor bank according to a twofold rule; detecting a mismatch code between the capacitor banks; if the mismatch code is larger than a preset target value, adjusting the composition of the high-order capacitor bank and the composition of the low-order capacitor bank, and then detecting the mismatch code again; the packet is adjusted based on the mismatch code and a subsequent packet is completed. The capacitors are adjusted in groups according to the mismatch codes, so that the precision of a twofold relation between adjacent capacitor groups is improved, and the analog-to-digital conversion precision of the charge redistribution type successive approximation analog-to-digital converter is improved.
The embodiments in the present specification are all described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same and similar between the embodiments may be referred to each other.
As will be appreciated by one of skill in the art, embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the true scope of the embodiments of the application.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "include", "including" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or terminal device including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article, or terminal device. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or terminal device that comprises the element.
The technical solutions provided by the present application are introduced in detail, and specific examples are applied in the description to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A capacitance grouping method of a binary weighted capacitor array applied to a charge redistribution type successive approximation analog-to-digital converter including a plurality of segments of capacitor arrays each including a plurality of unit capacitances, the capacitance grouping method comprising, for each segment of the capacitor arrays, the steps of:
grouping the plurality of unit capacitors in the capacitor array into a high-order capacitor bank and a low-order capacitor bank according to a double rule;
for each grouping, detecting mismatch voltage between the high-order capacitor bank and the low-order capacitor bank to obtain mismatch codes corresponding to the mismatch voltage;
and adjusting the grouping based on the relation between the mismatch code and a preset target value, and completing all the grouping in sequence.
2. The capacitance grouping method of claim 1, wherein the detecting a mismatch voltage between the upper capacitor bank and the lower capacitor bank comprises the steps of:
and detecting the mismatch voltage between the high-order capacitor bank and the low-order capacitor bank by using the low order of the analog-to-digital converter.
3. The capacitive grouping method of claim 1, wherein the adjusting the grouping based on the relationship between the mismatch code and a preset target value and completing all the grouping in sequence comprises the steps of:
comparing the mismatch code to the target value;
if the mismatch code is larger than the target value, adjusting the composition of the high-order capacitor bank and the composition of the low-order capacitor bank, and then returning to the step of detecting the mismatch voltage;
if the mismatch code is less than or equal to the target value, judging whether the low-order capacitor bank is the last group; if the lower capacitor bank is not the last one, returning to the step of grouping the plurality of unit capacitors in the capacitor array into a higher capacitor bank and a lower capacitor bank according to a doubling rule;
if the lower capacitor bank is the last packet, ending the packet and recording the packet condition.
4. The capacitance grouping method of claim 3 wherein the adjusting the composition of the upper capacitor bank and the composition of the lower capacitor bank comprises the steps of:
and adjusting the composition of the high-order capacitor bank and the composition of the low-order capacitor bank by using a cyclic shift method.
5. The capacitive grouping method of claim 3 wherein said determining if said lower capacitor bank is the last group comprises the steps of:
and judging whether the low-order capacitor bank is a single unit capacitor or not, if so, judging that the low-order capacitor bank is the last group, and if not, judging that the low-order capacitor bank is not the last group.
6. A capacitance grouping apparatus of a binary weighted capacitor array applied to a charge redistribution type successive approximation analog-to-digital converter including a plurality of segments of a capacitor array, each segment of the capacitor array including a plurality of unit capacitances, the capacitance grouping apparatus comprising, for each segment of the capacitor array:
a first grouping module configured to group the plurality of unit capacitances in the capacitor array into a higher order capacitor group and a lower order capacitor group on a double-rule basis;
a mismatch code detection module configured to detect, for each of the packets, a mismatch voltage between the high-order capacitor bank and the low-order capacitor bank using the low-order bits of the analog-to-digital converter, and obtain a mismatch code corresponding to the mismatch voltage;
and the second grouping module is configured to adjust the grouping based on the relation between the mismatch code and a preset target value, and complete all the grouping in sequence.
7. The capacitance grouping apparatus of claim 6, wherein the mismatch code detection module is configured to detect a mismatch voltage between the upper capacitor bank and the lower capacitor bank with a lower bit of the analog-to-digital converter.
8. The capacitive grouping apparatus of claim 6, wherein the second grouping module comprises:
a first judgment unit configured to compare the mismatch code with a preset target value;
a group adjustment unit configured to adjust a composition of the upper capacitor bank and a composition of the lower capacitor bank if the mismatch code is greater than the target value, and then control the mismatch code to perform detection of the mismatch voltage;
a second determination unit configured to determine whether the lower capacitor bank is a last bank if the mismatch code is less than or equal to the target value; if the lower capacitor bank is not the last group, controlling a first grouping module to perform grouping of the plurality of unit capacitors in the capacitor array into a higher capacitor bank and a lower capacitor bank according to a doubling rule;
a packet recording unit configured to end a packet and record a packet condition if the lower capacitor bank is the last packet.
9. The capacitance grouping apparatus of claim 8, wherein the grouping adjustment unit is configured to adjust the composition of the upper capacitor bank and the composition of the lower capacitor bank using a cyclic shift method.
10. The capacitance grouping apparatus of claim 8, wherein the second determining unit is configured to determine whether the lower capacitor bank is a single unit capacitor, determine that the lower capacitor bank is the last group if yes, and determine that the lower capacitor bank is not the last group if not.
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| CN202110865972.7A CN115694484A (en) | 2021-07-29 | 2021-07-29 | Binary weighted array capacitor grouping method and apparatus |
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