CN115694181A - Power converter based on ACOT control mode and control circuit thereof - Google Patents
Power converter based on ACOT control mode and control circuit thereof Download PDFInfo
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Abstract
The utility model provides a power converter and control circuit based on ACOT control mode, through the feedback voltage stack that acquires at the partial pressure node at the alternating current component of switch node sampling signal generate ripple compensation signal, make its ripple very little, just also make this power converter system can adopt the ceramic capacitor of little ESR as output capacitance, the cost is reduced and the volume, and generate first pulse signal based on this ripple compensation signal, and utilize the timer to acquire the sampling signal and the input voltage generation second pulse signal at the switch node, then generate the on-off control signal through this first pulse signal and second pulse signal, and adjust the duty cycle of this on-off control signal in view of the above, with this transient characteristic who improves this power converter system, the stability and the output precision of this buck converter system have been guaranteed simultaneously.
Description
Technical Field
The disclosure relates to the technical field of integrated circuits, in particular to a power converter based on an ACOT control mode and a control circuit thereof.
Background
With the progress of circuit electronic technology, switching power supplies are continuously developed towards high power density, high efficiency and high reliability. Switching converters are widely used in switching power supplies of various electronic products. The switching converter may employ a variety of topologies, such as BOOST (BOOST), BUCK (BUCK), BOOST-BUCK (BOOST-BUCK), flyback. During operation, the switching converter controls the conduction state of the switching tube, for example, in a Pulse Width Modulation (PWM) manner, so as to control the transmission of electric energy from the input end to the output end, thereby providing a stable output voltage and/or current.
When the PWM control method is adopted, the switching converter can realize the duty ratio adjustment of the switching control signal based on the control method of Constant switching period or Constant On Time (COT), so as to obtain the desired output voltage and/or current. Switching converters employing a constant on-time control scheme are widely used in various electronic products because they do not require an additional loop compensation network and have a faster transient response characteristic. Under the condition of adopting a constant on-time control mode, adaptive on-time (ACOT) control of output voltage feedforward can be introduced to eliminate the influence of input and output voltages on the working frequency of a system, so that the switching converter adopting the constant on-time control mode can have better EMI characteristics.
An output capacitor is connected to the output end of the switching converter and is used for filtering the output voltage to obtain a smooth waveform. Because output capacitance's capacitive characteristic, when using low Equivalent Series Resistance (ESR) electric capacity as output filter capacitor, its ESR ripple is covered by the ripple on the electric capacity, because the electric capacity ripple has phase delay in comparison with inductance ripple, consequently can make the system take place subharmonic oscillation, so need sufficient ESR electric capacity just can guarantee system stable work, but the great electric capacity of ESR, not only the volume is very big if electrolytic capacitor, can lead to the increase of output voltage ripple moreover. On the other hand, during transient response of the switching converter, due to the fixed Ton time, sufficient energy cannot be provided to meet the load change requirement, undershoot (under shoot) during the step on the load is easily caused to be large, and due to the limitation of the constant Ton, when the input voltage and the output voltage are close to each other, the power tube cannot be opened 100%.
When the switching converter is used to supply a power supply voltage required by a high-end functional chip such as a CPU or a server, a ripple of the power supply voltage is required to be sufficiently small. In order to reduce the ripple of the supply voltage, additional ripple compensation modules are required on and off the chip of the switching converter to meet the system stability requirements.
However, the ripple compensation module located outside the chip requires additional components, and the ripple compensation module located inside the chip may introduce dc offset to cause deviation of the output voltage. In addition, in order to satisfy the requirement of system stability under different input and output voltages, the compensation amount of the ripple compensation module of the switching converter is designed to be large, which results in poor dynamic characteristics.
Therefore, it is desirable to further improve the ripple compensation module of the switching converter to meet the requirements of system stability and dynamic characteristics.
Disclosure of Invention
In order to solve the technical problem, the present disclosure provides a power converter based on an ACOT control mode and a control circuit thereof, which not only ensure the stability and the output accuracy of the power converter system, but also improve the transient characteristics of the system and eliminate the offset effect.
In one aspect, the present disclosure provides a control circuit of a power converter based on an ACOT control mode, where the power converter includes a first switch tube, a second switch tube and an inductor connected between an input end and an output end of the power converter, and the control circuit controls conduction states of the first switch tube and the second switch tube respectively through a switch control signal to provide an output voltage through the inductor, where the control circuit includes:
the ripple compensation unit is provided with a first input end for sampling a switch node formed by connecting the first switch tube and the second switch tube and a second input end for sampling the output voltage through a voltage division node, and the output end of the ripple compensation unit is used for providing a ripple compensation signal;
the negative input end of the error amplifier is connected with the voltage division node, the positive input end of the error amplifier is connected with a preset reference voltage, and the output end of the error amplifier provides an error amplification signal;
the first comparator is used for generating a first pulse signal according to the ripple compensation signal and the error amplification signal;
the input end of the timer is respectively connected with the switch node and the input end of the power converter, and the output end of the timer provides a second pulse signal;
and the logic unit is used for generating the switch control signal according to the first pulse signal and the second pulse signal and adjusting the duty ratio of the switch control signal according to the switch control signal.
Preferably, the aforementioned control circuit further comprises:
and the driving unit receives the switch control signal and respectively generates a first control signal and a second control signal according to the logic processing of the switch control signal, wherein the first control signal is provided to the control end of the first switch tube and used for driving and controlling the conduction state of the first switch tube, and the second control signal is provided to the control end of the second switch tube and used for driving and controlling the conduction state of the second switch tube.
Preferably, the ripple compensation unit includes:
the input end of the integrator is connected with the switch node and is used for processing the signal sampled at the switch node to generate a first compensation signal;
the high-pass filter is connected with the output end of the integrator and is used for acquiring the alternating current component of the first compensation signal;
the input end of the buffer is connected with the voltage division node and is used for acquiring feedback voltage generated by sampling the output voltage;
and a synthesizer for synthesizing the ac component of the first compensation signal and the feedback voltage to generate the ripple compensation signal.
Preferably, the aforementioned control circuit further comprises:
and the first resistor and the first capacitor are connected between the output end of the error amplifier and the ground in series and used for filtering the error amplified signal.
Preferably, the aforementioned logic unit comprises:
the set end of the RS trigger is respectively connected with the first pulse signal and the second pulse signal, and the output end of the RS trigger is used for providing the switch control signal;
and the input end of the minimum turn-off time generator is connected with the output end of the RS trigger, and is used for carrying out timing detection on the low-level pulse of the switch control signal according to a preset minimum turn-off time threshold value and providing a detection signal to the reset end of the RS trigger.
Preferably, the RS flip-flop includes: an OR gate, a first NAND gate, a second NAND gate and a third NAND gate,
the input end of the or gate is used as the position end of the RS trigger, is respectively connected with the output end of the first comparator and the output end of the timer, and is connected with the first pulse signal and the second pulse signal;
the input end of the first NAND gate is respectively connected with the output end of the OR gate and the output end of the second NAND gate;
the input end of the second NAND gate is respectively connected with the output end of the first NAND gate and the output end of the third NAND gate, and the output end of the second NAND gate is used as the output end of the RS trigger and used for providing the switch control signal;
the input end of the third nand gate is used as the reset end of the RS flip-flop and is respectively connected with the output end of the first comparator and the output end of the minimum turn-off time generator.
Preferably, any one of the first switching tube and the second switching tube is a metal oxide semiconductor field effect transistor.
Preferably, the channel types of the first switch tube and the second switch tube are the same, and then the first control signal and the second control signal are a pair of complementary and inverted signals;
or the channel types of the first switch tube and the second switch tube are opposite, the first control signal and the second control signal are a pair of same signals.
In another aspect, the present disclosure further provides a power converter based on an ACOT control mode, including:
the main circuit comprises a first switching tube, a second switching tube and an inductor, wherein the first switching tube and the second switching tube are connected between the input end of the power converter and the ground in series, and the inductor is connected between a switching node formed by connecting the first switching tube and the second switching tube and the output end of the power converter;
the control circuit samples the signal of the switch node, inputs the voltage and samples the output voltage through the voltage dividing node to generate a first pulse signal and a second pulse signal, further adjusts the duty ratio of the switch control signal generated by the control circuit by using the first pulse signal and the second pulse signal, and controls the conduction states of the first switch tube and the second switch tube by using the switch control signal respectively so as to provide the output voltage through the inductor.
Preferably, the aforementioned power converter further comprises:
and the feedback network comprises a first voltage division resistor and a second voltage division resistor which are connected between the output end of the power converter and the ground in series, and a feedforward capacitor which is connected across the first voltage division resistor in parallel, wherein the connection node of the first voltage division resistor and the second voltage division resistor is used as the voltage division node and is used for providing a feedback voltage for sampling the output voltage.
The beneficial effects of this disclosure are: the utility model provides a power converter and control circuit based on ACOT control mode, through the alternating current component of the feedback voltage stack sampling switch node signal that acquires at the partial pressure node generate ripple compensation signal, make its ripple very little, and generate first pulse signal based on this ripple compensation signal, and utilize the signal and the input voltage of aforementioned switch node of timer sampling to generate the second pulse signal, then generate the switch control signal through this first pulse signal and second pulse signal, and adjust the duty cycle of this switch control signal in view of the above, therefore have the transient response better than traditional COT control framework. And the buffer device is adopted to isolate the alternating current signal of the switch node SW from the feedback node FB, so that the ripple compensation signal generated after the superposition of the alternating current signal and the feedback node FB cannot interfere with the feedback node FB, and the stability and the output precision of the buck converter system are ensured.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a constant on-time controlled buck converter in the prior art;
FIG. 2 illustrates an operational timing diagram of a portion of the node signals and control signals shown in FIG. 1;
fig. 3 shows a schematic diagram of a buck converter based on an ACOT control mode according to an embodiment of the disclosure;
fig. 4 is a circuit configuration diagram illustrating a ripple compensating unit in the buck converter shown in fig. 3;
fig. 5 shows a circuit configuration diagram of a logic unit in the buck converter shown in fig. 3.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
As shown in fig. 1, in the circuit structure of the conventional constant on-time buck converter 100, the main circuit includes a main circuit and a control circuit 110, the main circuit includes a first switching tube Q1 and a second switching tube Q2 connected in series between an input terminal of the buck converter 100 and the ground, an inductor L connected between a connection node SW of the first switching tube Q and the output terminal of the buck converter 100, and an output capacitor Co (equivalent series resistance (ESR) of the output capacitor Co is not shown) and a feedback network connected in parallel between the output terminal of the buck converter 100 and the ground, the feedback network includes resistors Ra and Rb connected in series for generating a feedback voltage Vfb.
The control circuit 110 includes an error amplifier 101, a comparator 102, a timer 103, a combinational logic circuit 104, a minimum off-time generator 105, and a driving unit 106, wherein the timer 103 has inputs Vin and Vo and outputs an on-control signal Ton. Vo is divided by resistors Ra and Rb to obtain a feedback voltage Vfb, which is sent to the negative input terminal of the error amplifier 101, the positive input terminal of the error amplifier 101 is connected to a reference voltage Vref, the output terminal of the error amplifier 101 is connected to the non-inverting input terminal of the comparator 102, the inverting input terminal of the comparator 102 is connected to the feedback voltage Vfb, the output terminal of the comparator 102 is connected to one input terminal of the combinational logic circuit 104, the combinational logic circuit 104 includes a flip-flop circuit in which a logical and gate U1 and two logical nor gates U2 and U3 are combined, one input terminal of the and gate U1 is connected to the output terminal of the comparator 102, the other input terminal is the output terminal of the off-time control unit 105, the input terminal of the nor gate U3 is connected to the on-control signal Ton, and the output terminal provides the aforementioned switching control signal PWM. . The output Q of the combinational logic circuit 104 sends the switching control signal PWM to the driving unit 106, and feeds back the switching control signal PWM to the minimum off-time generator 105, and the driving unit 106 is configured to generate a control signal Drv1 for driving the first switching tube Q1 and a control signal Drv2 for driving the second switching tube Q2 according to the switching control signal PWM provided by the control circuit 110.
The operation of the buck converter 100 is as follows: when the circuit is operated, the output Vc of the error amplifier 101 is used as the reference voltage of the comparator 102, when the feedback voltage Vfb obtained by sampling the output voltage Vo is lower than the voltage Vc, the output of the comparator 102 is positive, if the output of the minimum off-time generator 105 is also positive, the output of the and gate U1 is positive, according to the characteristics of the flip-flop circuit, the output Q of the combinational logic circuit 104 is also positive, at this time, the positive signal Q opens the first switching tube Q1 through the driving unit 106, and the second switching tube Q2 is closed, so that the output voltage Vo is increased, and the feedback voltage Vfb is also increased. At the same time, the timer 103 starts counting time.
As the output voltage Vo increases, when the feedback voltage Vfb is greater than the voltage Vc, the output of the comparator 102 is negative, and the output Q of the and gate U1 in the combinational logic circuit 104 is zero. When the timer 103 reaches a predetermined time, the output terminal Ton becomes high, and the output of the nor gate U3 in the combinational logic circuit 104 becomes high, so that the output of the combinational logic circuit 104 becomes 0. The driver turns off the first switch Q1, turns on the second switch Q2, and the output voltage Vo starts to decrease, and simultaneously triggers the minimum off-time generator 105 to start timing. After the minimum off-time generator 105 is triggered, the output is always 0 for a preset minimum off-time. The purpose of the minimum off-time generator 105 is to prevent the output from being positive due to noise interference or other reasons, and to start a new cycle by mistake, so as to ensure that the first switching tube Q1 has a minimum off-time, and after the minimum off-time generator 105 is triggered, the output becomes positive after the minimum off-time. When the output voltage Vo drops such that the feedback voltage Vfb is lower than the voltage Vc, a new period is restarted.
Through the basic relational expression of the Buck converter, the basic formula of the COT controlled Buck can be obtained:
where D is the duty ratio of the switching control signal PWM, and Ton is the high level on-time of the on-control signal. The on-time Ton is a fixed time and is controlled by the timer 103, and the off-time Toff of the on-control signal is determined by detecting the valley value, as shown in fig. 2. When the ripple value of the feedback voltage Vfb drops to the compensation signal Vc, a new period is started.
In general, the constant on-time Ton in each cycle of the Buck converter is:
where K is a constant determined by circuit parameters and Ron is an external resistor. The operating frequency of the Buck converter can be derived from the two equations:
it can be seen that the operating frequency of the Buck converter in the COT control mode is determined by Vout, K and Ron, and these three parameters are all determined in an application circuit, so that the operating frequency of the Buck converter is theoretically kept unchanged, and in real applications, due to the non-ideal switching of the switching tube, the transmission delay of signals and other factors, the fluctuation of the effective range of the operating frequency may fluctuate, and it is generally considered that the fluctuation is about 5% of the set value, which meets the application requirements.
In a traditional COT control scheme, a ripple on an Equivalent Series Resistance (ESR) of an output filter capacitor is used as an information carrier of load change and is directly fed back to a control system, so that rapid load transient response is achieved. However, during transient response, the buck converter 100 cannot provide enough energy to meet the requirement of load change due to fixed on-time Ton, which causes a large undershoot during the step-up of the load, and meanwhile, due to the limitation of constant Ton, when Vin and Vo are close to each other, the first switching tube Q1 cannot be turned on 100% in a conducting manner, and when the buck converter is used for providing the power supply voltage required by high-end functional chips such as CPUs and servers, the ripple of the power supply voltage is required to be small enough.
Based on this, the present disclosure provides a buck converter based on the ACOT control mode and having a fast transient response. The buck converter system is based on self-adaptive on-time control, so that the system does not need a large number of loop compensation elements, the design difficulty is reduced, the stability and the output precision of the system are ensured, and the transient response is more excellent than that of the traditional COT control scheme.
The present disclosure is described in detail below with reference to the accompanying drawings.
Fig. 3 illustrates a schematic structure diagram of a buck converter based on an ACOT control mode according to an embodiment of the present disclosure, fig. 4 illustrates a circuit structure diagram of a ripple compensation unit in the buck converter illustrated in fig. 3, and fig. 5 illustrates a circuit structure diagram of a logic unit in the buck converter illustrated in fig. 3.
Referring to fig. 3, taking a Buck (Buck) type topology power converter as an example, an embodiment of the present disclosure provides a Buck converter 200 based On an Adaptive Constant On Time (ACOT) control mode, which includes: the main circuit comprises a first switch tube Q1 and a second switch tube Q2 which are connected in series between the input end of the buck converter 200 and the ground, an inductor L connected between a switch node SW between the first switch tube Q1 and the second switch tube Q2 and the output end of the buck converter 200, an output capacitor Cout (Resr is an equivalent series resistor of the output capacitor Cout) and a feedback network which are connected in parallel between the output end of the buck converter 200 and the ground, wherein the feedback network comprises resistors Ra and Rb which are connected in series, and a feedforward capacitor Cc connected in parallel between two ends of the resistor Ra, the connection node of the resistors Ra and Rb is used as a voltage dividing node FB and used for providing a feedback voltage Vfb for sampling an output voltage Vo, and Ro represents a load. The control circuit 210 generates a first pulse signal Ton1 and a second pulse signal Ton2 by sampling the signal of the switch node SW, inputting the voltage Vin, and sampling the output voltage Vout through the voltage dividing node FB, and then adjusts the duty ratio of the switch control signal PWM generated by the control circuit 210 by using the first pulse signal Ton1 and the second pulse signal Ton2, and controls the on-state of the first switch tube Q1 and the second switch tube Q2 by using the switch control signal PWM, so as to provide the output voltage Vo through the inductor L.
In this embodiment, the control circuit 210 includes an error amplifier 21, a first comparator 22, a ripple compensation unit 23, a timer 24, a logic unit 25 and a driving unit 26, wherein an input terminal of the timer 24 is respectively connected to an input terminal of the buck converter 200 and a switch node SW, and is configured to generate a second pulse signal Ton2 for turning on a first switch Q1 in a main circuit, and the second pulse signal Ton2 determines a switching frequency of the first switch Q1; the output voltage Vo is subjected to voltage division by resistors Ra and Rb to obtain a feedback voltage Vfb, which is respectively sent to the negative input end of the error amplifier 21 and the ripple compensation unit 23, the positive input end of the error amplifier 21 is connected to a preset reference voltage Vref, and the output end of the error amplifier is connected to the non-inverting input end of the first comparator 22 to provide an error amplification signal Vc; the ripple compensating unit 23 has a first input end sampling the switch node SW and a second input end sampling the output voltage Vo through the voltage dividing node FB, and an output end of the ripple compensating unit 23 is used for providing a ripple compensating signal Vcomp; the inverting input terminal of the first comparator 22 is connected to the ripple compensation signal Vcomp, and the first comparator 22 is configured to generate a first pulse signal Ton1 according to the ripple compensation signal Vcomp and the error amplification signal Vc; the logic unit 25 is configured to generate the aforementioned switching control signal PWM according to the aforementioned first pulse signal Ton1 and second pulse signal Ton2, and adjust the duty ratio of the switching control signal PWM according to the aforementioned (first pulse signal Ton1 and second pulse signal Ton 2).
Further, in the present embodiment, the first comparator 22 is a hysteresis comparator circuit structure, so that the response speed of the comparator can be increased by using the positive feedback added in the hysteresis comparator circuit structure. In addition, the hysteresis comparator can avoid self-oscillation caused by circuit parasitic coupling because the positive feedback added by the hysteresis comparator is strong and much stronger than the parasitic coupling in the circuit.
Further, in this embodiment, the control circuit 210 further includes a driving unit 26, the driving unit 26 receives the switching control signal PWM, and generates a first control signal Drv1 and a second control signal Drv2 according to the logic processing of the switching control signal PWM, the first control signal Drv1 is provided to the control terminal of the first switching tube Q1 for driving and controlling the conducting state of the first switching tube Q1, and the second control signal Drv2 is provided to the control terminal of the second switching tube Q2 for driving and controlling the conducting state of the second switching tube Q2.
Further, referring to fig. 4, in the present embodiment, the ripple compensation unit 23 includes: the integrator 231, the high-pass filter 232, the buffer 233 and the synthesizer 234, wherein the input end of the integrator 231 is connected to the switch node SW for processing the signal sampled at the switch node SW to generate a first compensation signal V1; the high-pass filter 232 is connected to the output end of the integrator 231, and is configured to obtain an alternating current component of the first compensation signal V1; the input end of the buffer 233 is connected to the voltage dividing node FB, and is configured to obtain the feedback voltage Vfb generated by sampling the output voltage Vo; the synthesizer 234 is configured to synthesize the ac component of the first compensation signal V1 and the feedback voltage Vfb to generate the ripple compensation signal Vcomp.
Further, in this embodiment, the control circuit 210 further includes a first resistor Rea and a first capacitor Cea, and the first resistor Rea and the first capacitor Cea are connected in series between the output end of the error amplifier 21 and ground for filtering the error amplified signal Vc.
Further, referring to fig. 5, in the present embodiment, the aforementioned logic unit 25 includes: a minimum off-time generator 251 and an RS flip-flop 252, wherein a set terminal of the RS flip-flop 252 is respectively connected to the first pulse signal Ton1 and the second pulse signal Ton2, and an output terminal is used for providing the switching control signal PWM; the input terminal of the minimum off-time generator 251 is connected to the output terminal of the RS flip-flop 252, and is configured to time and detect a low-level pulse of the switching control signal PWM according to a preset minimum off-time threshold, and provide a detection signal Toff to the reset terminal of the RS flip-flop 252.
Further, referring to fig. 5, in the present embodiment, the RS flip-flop 252 includes: an or gate U4, a first nand gate U7, a second nand gate U6 and a third nand gate U5, wherein an input terminal of the or gate U4 is used as a set terminal of the RS flip-flop 252, is respectively connected to an output terminal of the first comparator 22 and an output terminal of the timer 24, and is connected to the first pulse signal Ton1 and the second pulse signal Ton2; the input end of the first NAND gate U7 is respectively connected with the output end of the OR gate U4 and the output end of the second NAND gate U6; the input end of the second nand gate U6 is connected to the output end of the first nand gate U7 and the output end of the third nand gate U5, respectively, and the output end of the second nand gate U6 is used as the output end of the RS flip-flop 252 for providing the aforementioned switch control signal PWM; the input terminal of the third nand gate U5 is used as the reset terminal of the RS flip-flop 252, and is respectively connected to the output terminal of the first comparator 22 and the output terminal of the minimum off-time generator 251.
Further, in this embodiment, any one of the first switch tube Q1 and the second switch tube Q2 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET, hereinafter referred to as MOS tube).
Further, in this embodiment, the channel types of the first switch Q1 and the second switch Q2 are the same, and the first control signal Drv1 and the second control signal Drv2 are a pair of complementary inverted signals; or in an alternative embodiment, the channel types of the first switch tube Q1 and the second switch tube Q2 are opposite, and the first control signal Drv1 and the second control signal Drv2 are a pair of same signals.
In this embodiment, the timer 24 may be regarded as a timing module, an input end of the timing module is connected to the input voltage Vin of the buck converter 200 and a signal obtained by sampling the switch node SW, and a timing value output by the timing module, that is, the second pulse signal Ton2= D × Tsw (D is a duty ratio of the switch control signal PWM, the signal obtained by sampling the switch node SW and the input voltage Vin are obtained, tsw is a target frequency value and is a fixed value), when the first switch tube Q1 is turned on, the timer 24 starts to time, and when the timing time reaches Ton2 (the Ton2 is a preset target on-time, specifically, for example, a preset time when the detection voltage reaches the reference voltage during normal timing in the circuit to turn over the comparator), a high level signal is output and sent to the RS flip-flop 252 to send an off signal for turning off the first switch tube Q1. The minimum off-time generator 251 is also a timing module for limiting the minimum time for turning off the first switch tube Q1 by a preset minimum off-time threshold.
In this embodiment, the control circuit 210 may generate the ripple compensation signal Vcomp by superimposing the ac component of the signal of the sampling switch node SW on the feedback voltage Vfb acquired at the voltage dividing node FB, so that the ripple is small, and the system of the power converter 200 may use the ceramic capacitor with small ESR as the output capacitor, thereby reducing the cost and the volume.
Furthermore, in the present embodiment, the control circuit 210 generates a first pulse signal Ton1 based on the ripple compensation signal Vcomp, and generates a second pulse signal Ton2 by sampling the signal of the aforementioned switching node SW and the input voltage Vin with the timer 24, and then generates a switching control signal PWM by the first pulse signal Ton1 and the second pulse signal Ton2, and adjusts the duty ratio of the switching control signal PWM accordingly, so that the transient response characteristic is better than that of the conventional COT control architecture.
In addition, in the control circuit 210 of this embodiment, the switch node SW and the feedback node FB (high impedance node) that are sampled to obtain the ac signal are isolated by using the buffer device (buffer 233), so that the superimposed ripple compensation signal Vcomp does not interfere with the feedback node FB, thereby ensuring the stability and the output accuracy of the buck converter 200 system, and meanwhile, the error amplifier 21 with high dc gain used in the control circuit 210 further guarantees the high output accuracy.
In the present embodiment, the timer 24 limits the minimum time for the first switch Q1 to turn on, and when the on (high level) time of the switch control signal PWM is less than the pulse width of the second pulse signal Ton2, the on time of the first switch Q1 is limited to Ton2, because the timer 24 is adaptive frequency, this arrangement can ensure that the system operates in the pseudo-constant frequency state, and the control signals of the control circuit 210 include the driving control signals (Drv 1 and Drv 2) of the first switch Q1 and the second switch Q2 and the related feedback signals (Vfb and SW). Since the first control signal Drv1 driving the first switching transistor Q1 and the second control signal Drv2 driving the second switching transistor Q2 are related to the current mode and the zero-crossing time of the buck converter 200, the buck converter 200 in this embodiment can operate in both the continuous mode and the discontinuous mode of the inductor current to achieve the beneficial effects of improving the transient characteristics and eliminating the imbalance.
In the embodiment, based on the setting of the RS flip-flop 252, as long as the switching control signal PWM is in a constant on or constant off state, the buck converter 200 system can be in a constant on or constant off state, especially the system can be in a constant on state, which can satisfy some applications with close input/output, and in addition, the setting makes the upper limit of the on-time of the system not limited by the timer 24, so the transient response is better than that of the conventional COT architecture system.
In the buck converter 200 of the present embodiment, during a transient change of the load, since the change of the output voltage Vo can be directly transmitted to the feedback node FB through the feedforward capacitor Cc and then sent to the first comparator 22 to control the on/off of the first switch Q1 without waiting for the response of the error amplifier 21, the transient response is more excellent.
It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate an orientation or positional relationship for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (10)
1. A control circuit of a power converter based on an ACOT control mode, the power converter including a first switch tube, a second switch tube and an inductor connected between an input end and an output end of the power converter, the control circuit respectively controlling conduction states of the first switch tube and the second switch tube through switch control signals to provide an output voltage through the inductor, wherein the control circuit includes:
the ripple compensation unit is provided with a first input end for sampling a switching node formed by connecting the first switching tube and the second switching tube and a second input end for sampling the output voltage through a voltage division node, and the output end of the ripple compensation unit is used for providing a ripple compensation signal;
the negative input end of the error amplifier is connected with the voltage dividing node, the positive input end of the error amplifier is connected with a preset reference voltage, and the output end of the error amplifier provides an error amplification signal;
a first comparator for generating a first pulse signal according to the ripple compensation signal and the error amplification signal;
the input end of the timer is respectively connected with the switch node and the input end of the power converter, and the output end of the timer provides a second pulse signal;
and the logic unit is used for generating the switch control signal according to the first pulse signal and the second pulse signal and adjusting the duty ratio of the switch control signal according to the switch control signal.
2. The control circuit of claim 1, further comprising:
and the driving unit receives the switch control signal and respectively generates a first control signal and a second control signal according to the logic processing of the switch control signal, the first control signal is provided to the control end of the first switch tube and used for driving and controlling the conduction state of the first switch tube, and the second control signal is provided to the control end of the second switch tube and used for driving and controlling the conduction state of the second switch tube.
3. The control circuit of claim 2, wherein the ripple compensation unit comprises:
the input end of the integrator is connected with the switching node and used for processing the signal obtained by sampling at the switching node to generate a first compensation signal;
the high-pass filter is connected with the output end of the integrator and is used for acquiring the alternating current component of the first compensation signal;
the input end of the buffer is connected with the voltage division node and is used for acquiring feedback voltage generated by sampling the output voltage;
and the synthesizer is used for synthesizing the alternating current component of the first compensation signal and the feedback voltage to generate the ripple compensation signal.
4. The control circuit of claim 3, wherein the control circuit further comprises:
and the first resistor and the first capacitor are connected between the output end of the error amplifier and the ground in series and are used for filtering the error amplified signal.
5. The control circuit of claim 3, wherein the logic unit comprises:
the set end of the RS trigger is respectively connected with the first pulse signal and the second pulse signal, and the output end of the RS trigger is used for providing the switch control signal;
and the input end of the minimum turn-off time generator is connected with the output end of the RS trigger, and is used for carrying out timing detection on the low-level pulse of the switch control signal according to a preset minimum turn-off time threshold value and providing a detection signal to the reset end of the RS trigger.
6. The control circuit of claim 5, wherein the RS flip-flop comprises: an OR gate, a first NAND gate, a second NAND gate and a third NAND gate,
the input end of the or gate is used as a position end of the RS trigger, is respectively connected with the output end of the first comparator and the output end of the timer, and is connected with the first pulse signal and the second pulse signal;
the input end of the first NAND gate is respectively connected with the output end of the OR gate and the output end of the second NAND gate;
the input end of the second nand gate is respectively connected with the output end of the first nand gate and the output end of the third nand gate, and the output end of the second nand gate is used as the output end of the RS flip-flop and is used for providing the switch control signal;
and the input end of the third NAND gate is used as the reset end of the RS trigger and is respectively connected with the output end of the first comparator and the output end of the minimum turn-off time generator.
7. The control circuit of claim 2, wherein either one of the first switching transistor and the second switching transistor is a metal oxide semiconductor field effect transistor.
8. The control circuit of claim 7, wherein the first switch tube and the second switch tube have the same channel type, and the first control signal and the second control signal are a pair of complementary inverted signals,
or the channel types of the first switch tube and the second switch tube are opposite, the first control signal and the second control signal are a pair of same signals.
9. A power converter based on an ACOT control mode, comprising:
the main circuit comprises a first switch tube, a second switch tube and an inductor, the first switch tube and the second switch tube Guan Guanchuan are connected between the input end of the power converter and the ground, and the inductor is connected between a switch node formed by connecting the first switch tube and the second switch tube and the output end of the power converter;
the control circuit according to any one of claims 1 to 8, wherein the control circuit samples the signal of the switch node, inputs the voltage, and samples the output voltage through a voltage dividing node to generate a first pulse signal and a second pulse signal, and further adjusts the duty ratio of the switch control signal generated by the control circuit according to the first pulse signal and the second pulse signal, and controls the conduction states of the first switch tube and the second switch tube with the switch control signal, respectively, to provide the output voltage through the inductor.
10. The power converter of claim 9, further comprising:
and the feedback network comprises a first voltage division resistor and a second voltage division resistor which are connected between the output end of the power converter and the ground in series, and a feedforward capacitor which is connected across the first voltage division resistor in parallel, wherein the connection node of the first voltage division resistor and the second voltage division resistor is used as the voltage division node and used for providing a feedback voltage for sampling the output voltage.
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| CN202110835307.3A CN115694181A (en) | 2021-07-23 | 2021-07-23 | Power converter based on ACOT control mode and control circuit thereof |
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| CN202110835307.3A CN115694181A (en) | 2021-07-23 | 2021-07-23 | Power converter based on ACOT control mode and control circuit thereof |
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| CN102868293A (en) * | 2012-09-10 | 2013-01-09 | 常州大学 | Slope compensating method and device of fixed turn-off time control switch converter |
| US20180301985A1 (en) * | 2017-04-14 | 2018-10-18 | Allegro Microsystems, Llc | Converter digital control circuit with adaptive compensation |
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| CN110545039A (en) * | 2019-08-29 | 2019-12-06 | 杭州士兰微电子股份有限公司 | switch converter and control circuit and control method thereof |
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| CN102868293A (en) * | 2012-09-10 | 2013-01-09 | 常州大学 | Slope compensating method and device of fixed turn-off time control switch converter |
| US20180301985A1 (en) * | 2017-04-14 | 2018-10-18 | Allegro Microsystems, Llc | Converter digital control circuit with adaptive compensation |
| CN109600029A (en) * | 2019-01-03 | 2019-04-09 | 深圳市基准半导体有限公司 | A kind of Buck DC-DC of the adaptive turn-on time of pseudo- fixed frequency of use is lightly loaded efficient and ripple control method |
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