CN115694151A - High-side driving circuit and equipment of half-bridge driver - Google Patents
High-side driving circuit and equipment of half-bridge driver Download PDFInfo
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- CN115694151A CN115694151A CN202211466554.1A CN202211466554A CN115694151A CN 115694151 A CN115694151 A CN 115694151A CN 202211466554 A CN202211466554 A CN 202211466554A CN 115694151 A CN115694151 A CN 115694151A
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Abstract
The application provides a high-side driving circuit and equipment of a half-bridge driver, wherein the high-side driving circuit of the half-bridge driver comprises a level shifter and a high-side control driving module; the high-side control driving module is provided with an input end and an output end, the input end of the high-side control driving module is electrically connected with the output end of the level shifter, and the high-side control driving module is used for avoiding the output end of the high-side control driving module from outputting wrong levels due to transient change of the second variable voltage source. The output of the high-side driving circuit of the half-bridge driver is determined by the level shifter and the high-side control driving module together, and in the time of fast transient change, the output of the high-side driving circuit of the half-bridge driver is determined by the high-side control driving module and is irrelevant to the output end of the level shifter at the moment, so that the problem of how to eliminate the influence of transient interference and noise generated by the floating high-speed transient change of the half-bridge driver on the normal operation of the high-side driving circuit is solved.
Description
Technical Field
The application relates to the technical field of half-bridge drivers, in particular to a high-side driving circuit and equipment of a half-bridge driver.
Background
Fig. 1 is a first schematic diagram of a half-bridge driver of the prior art, which includes a high-side portion and a low-side portion, wherein the low-side portion drives a low-side switch N1 by a low-side driver 110; the high side part is driven by a high side driver 120 to drive a high side switch tube N2, and the switch tubes N1 and N2 are driven by a control signal PWM 1 And PWM 2 And controlling the alternate conduction. It can be seen from fig. 1 that the low side supply is VDD and GND, VDD is held at a fixed voltage and GND voltage is zero. The voltage difference between VBST and VSW of the high-side power supply remains unchanged, but the voltage of VSW is related to the operating state of the switching tubes N1 and N2. When N1 is switched on and N2 is switched off, the voltage of VSW is equal to GND; when N2 is on and N1 is off, VSW is equal to VIN. VSW is called floating ground and will rise from GND to VIN or fall from VIN to GND during the switching of the switch tube. Transient changes in the VSW voltage can produce glitch voltages and glitch currents that can affect the proper operation of the high-side driver.
Fig. 2 is a second schematic diagram of a half-bridge driver of the prior art, and the high-side driver 120 includes a voltage level shifter 121 and a driving stage 122, wherein an input signal PWM of the voltage level shifter 121 2 And low side driver input signal PWM 1 Similarly, the reference voltages are VDD and GND. The reference voltages of the output signal at the output terminal A of the voltage level shifter 121 are VBST and VSW for PWM 2 High side driver in the same direction as OUT, for exampleFIG. 3 shows the operation timing diagram of PWM 2 After going from low to high, the voltage level shifter output a goes from low to high. Since the driving delay of the output stage is TD, that is, the delay from point a to OUT is TD1, after point a goes high, TD1 OUT goes high, the upper tube N2 is turned on, and VSW goes from GND to VIN. PWM 2 The delay from high to low to VSW from high to low is TD2. The rise time of VSW from low to high is TR, and the fall time from high to low is TF. As can be seen from fig. 3, TD1, TD2 do not overlap with TR and TF in time. When the voltage level shifter is working normally, PWM 2 During the time between output a, the voltage level shifter is not affected by VSW transients. During both TR and TF periods, the output of the voltage level shifter may be affected due to rapid transient changes in VSW.
Disclosure of Invention
The main objective of the present application is to provide a high-side driving circuit and a device of a half-bridge driver, so as to solve the problem of how to eliminate the influence of transient interference and noise generated by high-speed transient change of a floating ground of the half-bridge driver on the normal operation of the high-side driving circuit.
According to an aspect of an embodiment of the present invention, there is provided a high side driving circuit of a half bridge driver, the high side driving circuit of the half bridge driver including a level shifter and a high side control driving module; the level shifter is provided with a first power supply end, a second power supply end, a signal receiving end and an output end, wherein the first power supply end of the level shifter is used for being electrically connected with a first variable voltage source, the second power supply end of the level shifter is used for being electrically connected with a second variable voltage source, and the signal receiving end of the level shifter is used for being electrically connected with the signal output end of the controller; the high-side control driving module is provided with an input end and an output end, the input end of the high-side control driving module is electrically connected with the output end of the level shifter, and the high-side control driving module is used for avoiding that the output end of the high-side control driving module outputs wrong levels due to transient change of the second variable voltage source.
Optionally, the high-side control drive module comprises: the edge detection delay unit, the alternative multiplexer, the buffer unit, the first buffer and the multi-stage buffer are respectively and electrically connected with the first variable voltage source, and the edge detection delay unit, the alternative multiplexer, the buffer unit, the first buffer and the multi-stage buffer are respectively and electrically connected with the second variable voltage source.
Optionally, the edge detection delay unit includes: the first input end of the exclusive-OR gate is electrically connected with the output end of the time delay, the second input end of the exclusive-OR gate is respectively electrically connected with the input end of the time delay and the input end of the multi-stage buffer, the output end of the exclusive-OR gate is electrically connected with the selection end of the two-choice multiplexer, the exclusive-OR gate and the time delay are further electrically connected with the first variable voltage source, and the exclusive-OR gate and the time delay are further electrically connected with the second variable voltage source.
Optionally, the one-out-of-two multiplexer comprises: the input end of the first inverter is respectively and electrically connected with the first input end of the first NAND gate and the first end of the edge detection delay unit, the second input end of the first NAND gate is electrically connected with the input ends of the multistage buffers, the output end of the first inverter is electrically connected with the first input end of the second NAND gate, the second input end of the second NAND gate is electrically connected with the output end of the buffer unit, the output end of the first NAND gate is electrically connected with the first input end of the third NAND gate, the output end of the second NAND gate is electrically connected with the second input end of the third NAND gate, the output end of the third NAND gate is electrically connected with the input end of the first buffer, the first NAND gate, the second NAND gate, the third NAND gate and the first inverter are also electrically connected with the first variable voltage source, and the first NAND gate, the second NAND gate, the third NAND gate and the first inverter are also electrically connected with the second variable voltage source.
Optionally, the buffer unit is a buffer in a case where a phase of a signal output terminal of the controller is the same as a potential of an output terminal of the multi-stage buffer.
Alternatively, in a case where a phase of a signal output terminal of the controller is opposite to a potential of an output terminal of the multi-stage buffer, the buffer unit is an inverter.
Optionally, the multi-stage buffer includes a plurality of buffers connected in series in sequence and having gradually increasing driving capability.
Optionally, the level shifter includes a first transistor, a second transistor, a third transistor, a fourth transistor, a second inverter, a protection unit, a first diode and a second diode, a source of the first transistor is electrically connected to a source of the second transistor and the first variable voltage source, a gate of the first transistor is electrically connected to a cathode of the second diode, a drain of the second transistor, an input terminal of the high-side control driving module, and a second terminal of the protection unit, a gate of the second transistor is electrically connected to a cathode of the first diode, a drain of the first transistor, and a first terminal of the protection unit, an anode of the first diode is electrically connected to an anode of the second diode and the second variable voltage source, a drain of the third transistor is electrically connected to a third terminal of the protection unit, a drain of the fourth transistor is electrically connected to a fourth terminal of the protection unit, a gate of the third transistor is electrically connected to an input terminal of the second inverter, an input terminal of the second inverter is further configured to be electrically connected to a signal output terminal of the controller, and a source of the fourth transistor is electrically connected to an output terminal of the first diode, and a gate of the third transistor are electrically connected to ground.
Optionally, the protection unit includes a first high voltage transistor and a second high voltage transistor, a gate of the first high voltage transistor and a gate of the second high voltage transistor are respectively electrically connected to a dc voltage source, a drain of the first high voltage transistor is electrically connected to a cathode of the first diode, a drain of the second high voltage transistor is electrically connected to a cathode of the second diode, a source of the first high voltage transistor is electrically connected to a drain of the third transistor, and a source of the second high voltage transistor is electrically connected to a drain of the fourth transistor.
According to another aspect of the embodiments of the present invention, there is also provided an apparatus including a high-side driving circuit of any one of the half-bridge drivers.
In the embodiment of the invention, the output of the high-side driving circuit of the half-bridge driver is determined by the level shifter and the high-side control driving module together, the output of the high-side driving circuit is determined by the output end of the level shifter outside the rapid transient change time of the second variable voltage source, and the output of the high-side driving circuit of the half-bridge driver is determined by the high-side control driving module in the rapid transient change time, and is not related to the output end of the level shifter at the moment, so that the problem of how to eliminate the influence of transient interference and noise generated by the floating high-speed transient change of the half-bridge driver on the normal operation of the high-side driving circuit is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, are included to provide a further understanding of the application, and the description of the exemplary embodiments and illustrations of the application are intended to explain the application and are not intended to limit the application. In the drawings:
figure 1 shows a first schematic diagram of a half bridge driver of the prior art scheme;
fig. 2 shows a second schematic diagram of a half-bridge driver of the prior art scheme;
fig. 3 shows an operation timing diagram of a half bridge driver of the prior art scheme;
fig. 4 shows a schematic diagram of a high side drive circuit of a first kind of half bridge driver in an embodiment in accordance with the application;
fig. 5 shows a schematic diagram of a high side drive circuit of a second type of half bridge driver in an embodiment in accordance with the application;
FIG. 6 shows a schematic diagram of an edge-detect delay cell in an embodiment in accordance with the application;
FIG. 7 shows a schematic diagram of an alternative multiplexer in an embodiment in accordance with the application;
fig. 8 shows an operation timing diagram of a high-side driving circuit of a first half-bridge driver in an embodiment in accordance with the present application;
fig. 9 shows an operation timing diagram of a high-side driving circuit of a second half-bridge driver in an embodiment according to the present application.
Wherein the figures include the following reference numerals:
110. a low side driver; 120. a high-side driver; 121. a voltage level shifter; 122. a drive stage; 200. a level shifter; 210. a protection unit; 300. a high side control drive module; 310. an edge detection delay unit; 311. a time delay; 312. an exclusive-or gate; 320. an alternative multiplexer; 321. a first NAND gate; 322. a second NAND gate; 323. a third nand gate.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the accompanying drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the application herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background, in order to solve the problem of how to eliminate the effect of the transient interference and noise generated by the high-speed transient change of the floating half-bridge driver on the normal operation of the high-side driving circuit, in an exemplary embodiment of the present application, a high-side driving circuit and a device of the half-bridge driver are provided.
According to the present applicationEmbodiments of the present invention provide a high side driving circuit of a half bridge driver, as shown in fig. 4 and 5, the high side driving circuit of the half bridge driver includes a level shifter 200 and a high side control driving module 300; the level shifter 200 has a first power terminal for electrically connecting to a first variable voltage source VBST, a second power terminal for electrically connecting to a second variable voltage source VSW, a signal receiving terminal for electrically connecting to a signal output terminal PWM of the controller, and an output terminal 2 Wherein, the first variable voltage source VBST and the second variable voltage source VSW are both voltage variable voltage sources, and a difference between the first variable voltage source VBST and the second variable voltage source VSW is a constant voltage value (for example, the difference is always maintained at 5V); the high-side control driving module 300 has an input terminal and an output terminal, the input terminal of the high-side control driving module 300 is electrically connected to the output terminal of the level shifter 200, and the high-side control driving module 300 is configured to prevent the output terminal of the high-side control driving module 300 from outputting an error level due to a transient change of the second variable voltage source VSW.
In the circuit, the output of the high-side driving circuit of the half-bridge driver is determined by the level shifter and the high-side control driving module together, the output of the high-side driving circuit is determined by the output end A of the level shifter outside the rapid transient change time of the VSW of the second variable voltage source, and the output of the high-side driving circuit of the half-bridge driver is determined by the high-side control driving module in the rapid transient change time of the VSW and is independent of the output end A of the level shifter at the moment, so that the problem of how to eliminate the influence of transient interference and noise generated by the floating high-speed transient change of the half-bridge driver on the normal operation of the high-side driving circuit is solved.
In an embodiment of the present invention, the high-side control driving module 300 includes an edge detection delay unit 310, an alternative multiplexer 320, a buffer unit I1, a first buffer I2, and a multi-stage buffer I3, a selection terminal of the alternative multiplexer 320 is electrically connected to a first terminal of the edge detection delay unit 310, a first input terminal of the alternative multiplexer 320 is electrically connected to an output terminal of the buffer unit I1, an input terminal of the buffer unit I1 is electrically connected to an output terminal of the level shifter 200, a second input terminal of the alternative multiplexer 320 is electrically connected to a second terminal of the edge detection delay unit 310, an output terminal of the first buffer I2, and an input terminal of the multi-stage buffer I3, respectively, an input terminal of the first buffer I2 is electrically connected to an output terminal of the alternative multiplexer 320, the edge detection delay unit 310, the alternative multiplexer 320, the buffer unit I1, the first buffer I2, and the multi-stage buffer I3 are electrically connected to the first variable voltage source, the edge detection delay unit 310, the second variable voltage source I3, and the second variable voltage source I3.
Specifically, the buffer unit functions to rectify an output signal of the level shifter; the first buffer is used for enhancing the driving capability of the output end of the alternative multiplexer; the function of the alternative multiplexer is to select one of the output of the level shifter after passing through the buffer unit or the output of the alternative multiplexer after passing through the first buffer as the input of the multiplexer; the edge detection delay unit is used for detecting the edge of the input signal at the second end and outputting a high-level signal with a certain width at the first end; the multi-stage buffer functions to increase the driving capability of its input signal step by step and has a relatively large current driving capability at its output terminal.
In an embodiment of the present application, as shown in fig. 4 and 6, the edge detection delay unit 310 includes an xor gate 312 and a delay 311, a first input terminal of the xor gate 312 is electrically connected to an output terminal of the delay 311, a second input terminal of the xor gate 312 is electrically connected to an input terminal of the delay 311 and an input terminal of the multi-stage buffer I3, respectively, an output terminal of the xor gate 312 is electrically connected to a selection terminal of the two-way multiplexer 320, the xor gate 312 and the delay 311 are further electrically connected to the first variable voltage source VBST, and the xor gate 312 and the delay 311 are further electrically connected to the second variable voltage source VSW.
Specifically, the exclusive-or gate is used for outputting a low level when two input signals are the same, and outputting a high level when the two input signals are different; the time delay device is used for delaying an input signal for a period of time and then outputting the delayed input signal.
In one embodiment of the present application, as shown in fig. 4 and 7, the two-select multiplexer 320 includes a first nand gate 321, a second nand gate 322, a third nand gate 323, and a first inverter I5, inputs of the first inverter I5 are electrically connected to a first input of the first nand gate 321 and a first end of the edge-detect delay unit 310, respectively, a second input of the first nand gate 321 is electrically connected to an input of the multi-stage buffer I3, an output of the first inverter I5 is electrically connected to a first input of the second nand gate 322, a second input of the second nand gate 322 is electrically connected to an output of the buffer unit I1, an output end of the first nand gate 321 is electrically connected to a first input end of the third nand gate 323, an output end of the second nand gate 322 is electrically connected to a second input end of the third nand gate 323, an output end OUT _ S of the third nand gate 323 is electrically connected to an input end of the first buffer I2, the first nand gate 321, the second nand gate 322, the third nand gate 323, and the first inverter I5 are further electrically connected to the first variable voltage source VBST, and the first nand gate 321, the second nand gate 322, the third nand gate 323, and the first inverter I5 are further electrically connected to the second variable voltage source VSW.
Specifically, the expression of the output terminal OUT _ S of the one-of-two multiplexer 320 is OUT _ S = S × C + S × B, and the level of S is opposite to the level of S.
In an embodiment of the present invention, the buffer unit is a buffer when a phase of a signal output terminal of the controller is the same as a potential of an output terminal of the multi-stage buffer. As shown in FIG. 8, the initial state PWM2 of the circuit is low, and the A and B terminals outputAll are low level, S is low level, the alternative multiplexer selects the B terminal as input, and the C terminal is also low level. When PWM 2 When the level is changed from low level to high level, the output of the level shifter is changed from low level to high level, the output of the point B is changed from low level to high level, the output of the point S is still kept at low level, and the output of the point C is changed from low level to high level. After the point C becomes high level, triggering the edge detection delay control module to work and outputting S to become high level, and keeping the time length of the high level to be DT. After S becomes high level, the point C is used as the input end (namely, the selection input end) of the alternative multiplexer, so that the voltage of the point C can be kept at high level in the whole DT time range. The high side drive circuit output OUT of the half bridge driver is overlapped by the time length TR and DT that low goes high, and the S point output is high level in the TR period. Therefore, in the TR time when VSW rises rapidly, the voltage at the point C is kept at a high level no matter the values of the outputs A and B of the level shifter are high level or low level, so that the OUT output is ensured to be at a high level, and a high-side driving circuit of the half-bridge driver works normally.
Similarly, when PWM 2 When VSW changes from high to low, TF and DT overlap in time, and the output OUT is not influenced by the value of the output A of the level shifter during the time that VSW changes from high to low. Also, when PWM 2 The operation principle of the level shifter is the same when the phase is opposite to the OUT phase, and the operation timing chart at this time is shown in fig. 9.
In an embodiment of the present application, in a case where a phase of the signal output terminal of the controller is opposite to a potential of the output terminal of the multi-stage buffer, the buffer unit is an inverter, as shown in fig. 5.
In an embodiment of the present application, the multi-stage buffer I3 includes a plurality of buffers connected in series in sequence and having gradually increasing driving capability, the buffers are formed by transistors, and the buffers can be formed by CMOS devices.
In an embodiment of the present application, the level shifter 200 includes a first transistor PM1, a second transistor PM2, a third transistor NM1, a fourth transistor NM2, a second inverter I4, a protection unit 210, a first diode D1, and a second diode D2, a source of the first transistor PM1A source of the second transistor PM2 and the first variable voltage source VBST are electrically connected to the source of the second transistor PM2, a gate of the first transistor PM1 is electrically connected to a cathode of the second diode D2, a drain of the second transistor PM2, an input terminal of the high-side control driving module 300, and a second terminal of the protection unit 210, a gate of the second transistor PM2 is electrically connected to a cathode of the first diode D1, a drain of the first transistor PM1, and a first terminal of the protection unit 210, an anode of the first diode D1 is electrically connected to an anode of the second diode D2 and the second variable voltage source VSW, a drain of the third transistor NM1 is electrically connected to a third terminal of the protection unit 210, a drain of the fourth transistor NM2 is electrically connected to a fourth terminal of the protection unit 210, a gate of the third transistor NM1 is electrically connected to an input terminal of the second inverter I4, and an input terminal of the second inverter I4 is electrically connected to a signal output terminal of the PWM controller 2 The gate of the fourth transistor NM2 is electrically connected to the output terminal of the second inverter I4, and the source of the third transistor NM1 and the source of the fourth transistor NM2 are grounded, respectively.
In an embodiment of the present invention, the protection unit 210 includes a first high voltage transistor HNM1 and a second high voltage transistor HNM2, a gate of the first high voltage transistor HNM1 and a gate of the second high voltage transistor HNM2 are respectively electrically connected to a dc voltage source VDD, a drain of the first high voltage transistor HNM1 is electrically connected to a negative electrode of the first diode D1, a drain of the second high voltage transistor HNM2 is electrically connected to a negative electrode of the second diode D2, a source of the first high voltage transistor HNM1 is electrically connected to a drain of the third transistor NM1, and a source of the second high voltage transistor HNM2 is electrically connected to a drain of the fourth transistor NM2.
The first and second high voltage transistors HNM1 and HNM2 are used to protect the third and fourth transistors NM1 and NM2.
The present application further provides an apparatus comprising a high-side driver circuit of any of the half-bridge drivers described above.
It should be noted that the electrical connection may be a direct electrical connection or an indirect electrical connection, where a direct electrical connection means that two devices are directly connected, and an indirect electrical connection means that other devices such as a capacitor and a resistor are connected between a and B that are connected.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) The output of the high-side driving circuit of the half-bridge driver is determined by the level shifter and the high-side control driving module together, outside the time of the second variable voltage source for quick transient change, the output of the high-side driving circuit is determined by the output end of the level shifter, and in the time of the quick transient change, the output of the high-side driving circuit of the half-bridge driver is determined by the high-side control driving module per se and is irrelevant to the output end of the level shifter at the moment, so that the problem of how to eliminate the influence of transient interference and noise generated by the floating high-speed transient change of the half-bridge driver on the normal work of the high-side driving circuit is solved.
2) The output of the high-side driving circuit of the half-bridge driver is determined by the level shifter and the high-side control driving module together, outside the time of the second variable voltage source for quick transient change, the output of the high-side driving circuit is determined by the output end of the level shifter, and in the time of the quick transient change, the output of the high-side driving circuit of the half-bridge driver is determined by the high-side control driving module per se and is irrelevant to the output end of the level shifter at the moment, so that the problem of how to eliminate the influence of transient interference and noise generated by the floating high-speed transient change of the half-bridge driver on the normal work of the high-side driving circuit is solved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A high side driver circuit for a half bridge driver, comprising:
the level shifter comprises a first power supply end, a second power supply end, a signal receiving end and an output end, wherein the first power supply end of the level shifter is used for being electrically connected with a first variable voltage source, the second power supply end of the level shifter is used for being electrically connected with a second variable voltage source, and the signal receiving end of the level shifter is used for being electrically connected with the signal output end of a controller;
and the high-side control driving module is provided with an input end and an output end, the input end of the high-side control driving module is electrically connected with the output end of the level shifter, and the high-side control driving module is used for avoiding the output of the high-side control driving module from outputting wrong levels due to transient change of the second variable voltage source.
2. The circuit of claim 1, wherein the high-side control driver module comprises: the edge detection delay unit, the alternative multiplexer, the buffer unit, the first buffer and the multi-stage buffer are respectively and electrically connected with the first variable voltage source, and the edge detection delay unit, the alternative multiplexer, the buffer unit, the first buffer and the multi-stage buffer are respectively and electrically connected with the second variable voltage source.
3. The circuit of claim 2, wherein the edge detection delay cell comprises: the first input end of the exclusive-OR gate is electrically connected with the output end of the time delay device, the second input end of the exclusive-OR gate is respectively electrically connected with the input end of the time delay device and the input end of the multi-stage buffer, the output end of the exclusive-OR gate is electrically connected with the selection end of the two-choice multiplexer, the exclusive-OR gate and the time delay device are further electrically connected with the first variable voltage source, and the exclusive-OR gate and the time delay device are further electrically connected with the second variable voltage source.
4. The circuit of claim 2, wherein the one-of-two multiplexer comprises: the input end of the first inverter is respectively and electrically connected with the first input end of the first NAND gate and the first end of the edge detection delay unit, the second input end of the first NAND gate is electrically connected with the input ends of the multistage buffers, the output end of the first inverter is electrically connected with the first input end of the second NAND gate, the second input end of the second NAND gate is electrically connected with the output end of the buffer unit, the output end of the first NAND gate is electrically connected with the first input end of the third NAND gate, the output end of the second NAND gate is electrically connected with the second input end of the third NAND gate, the output end of the third NAND gate is electrically connected with the input end of the first buffer, the first NAND gate, the second NAND gate, the third NAND gate and the first inverter are also electrically connected with the first variable voltage source, and the first NAND gate, the second NAND gate, the third NAND gate and the first inverter are also electrically connected with the second variable voltage source.
5. The circuit according to claim 2, wherein the buffer unit is a buffer in a case where a phase of the output terminal of the level shifter is the same as a potential of the output terminal of the multi-stage buffer.
6. The circuit according to claim 2, wherein the buffer unit is an inverter in a case where a phase of the output terminal of the level shifter is opposite to a potential of the output terminal of the multi-stage buffer.
7. The circuit of any of claims 2-6, wherein the multi-stage buffer comprises a plurality of buffers connected in series and having gradually increasing drive capabilities.
8. The circuit of claim 1, wherein the level shifter comprises: the source of the first transistor is electrically connected with the source of the second transistor and the first variable voltage source, the gate of the first transistor is electrically connected with the cathode of the second diode, the drain of the second transistor, the input end of the high-side control driving module and the second end of the protection unit, the gate of the second transistor is electrically connected with the cathode of the first diode, the drain of the first transistor and the first end of the protection unit, the anode of the first diode is electrically connected with the anode of the second diode and the second variable voltage source, the drain of the third transistor is electrically connected with the third end of the protection unit, the drain of the fourth transistor is electrically connected with the third end of the protection unit, the gate of the third transistor is electrically connected with the input end of the second inverter, the input end of the second inverter is further used for being electrically connected with the signal output end of the controller, the gate of the fourth transistor is electrically connected with the output end of the second inverter, the source of the fourth transistor is electrically connected with the source of the fourth inverter, and the source of the fourth transistor is grounded.
9. The circuit of claim 8, wherein the protection unit comprises: the grid electrode of the first high-voltage transistor and the grid electrode of the second high-voltage transistor are respectively and electrically connected with a direct-current voltage source, the drain electrode of the first high-voltage transistor is electrically connected with the negative electrode of the first diode, the drain electrode of the second high-voltage transistor is electrically connected with the negative electrode of the second diode, the source electrode of the first high-voltage transistor is electrically connected with the drain electrode of the third transistor, and the source electrode of the second high-voltage transistor is electrically connected with the drain electrode of the fourth transistor.
10. An apparatus, characterized by a high side drive circuit comprising a half bridge driver of any of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211466554.1A CN115694151A (en) | 2022-11-22 | 2022-11-22 | High-side driving circuit and equipment of half-bridge driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211466554.1A CN115694151A (en) | 2022-11-22 | 2022-11-22 | High-side driving circuit and equipment of half-bridge driver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115694151A true CN115694151A (en) | 2023-02-03 |
Family
ID=85053534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211466554.1A Pending CN115694151A (en) | 2022-11-22 | 2022-11-22 | High-side driving circuit and equipment of half-bridge driver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115694151A (en) |
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2022
- 2022-11-22 CN CN202211466554.1A patent/CN115694151A/en active Pending
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