CN115693101A - W-band transmit-receive integrated phased array packaged antenna and manufacturing process - Google Patents
W-band transmit-receive integrated phased array packaged antenna and manufacturing process Download PDFInfo
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Abstract
The invention provides a W-band transmit-receive integrated phased array packaged antenna and a manufacturing process thereof, wherein the W-band transmit-receive integrated phased array packaged antenna comprises an upper layer packaging body and a lower layer packaging body; the first substrate is provided with a first through hole, the upper surface of the first substrate is provided with a first rewiring layer, and the lower surface of the first substrate is provided with a second rewiring layer; a second through hole is formed in the second substrate; the transceiver chip is embedded in the second substrate; a third rewiring layer electrically connected with the conductive material in the second through hole is arranged on the upper surface of the second substrate; and a fourth rewiring layer electrically connected with the conductive material in the second through hole is arranged on the lower surface of the second substrate. The invention has the technical effects of reasonable structure, lower transmission loss and higher integration level, and can realize the performances of expandability, miniaturization, large scanning angle and the like by structural layout design in order to meet the strict size and power limitation.
Description
Technical Field
The invention belongs to the technical field of millimeter wave packaged antennas, and particularly relates to a W-band transmit-receive integrated phased array packaged antenna and a manufacturing process thereof.
Background
The W-band radio frequency micro-system can be applied to working scenes such as anti-collision radars, detection imaging and return communication, and has the advantages of strong anti-interference capability, high resolution, high imaging speed, good penetrability and all-weather work in radar application due to the high W-band frequency and the low absorption characteristic of the atmospheric window.
The packaging antenna is the most important component of a W-band radar radio frequency micro-system, the wavelength is longer when the frequency is lower (< 10 GHz), and the packaging requirement is relatively flexible due to the larger antenna spacing. However, at millimeter wave frequencies (> 30 GHz), especially in the W-band, the physically shorter antenna spacing (1/2 λ <3 mm) makes multilayer package interconnect loss, impedance matching challenging, while demanding on packaging process, integration and package architecture.
The conventional technology of packaging an Antenna (AIP) mainly includes Low Temperature Co-fired Ceramic (LTCC), high Density Interconnect (HDI) printed circuit board (HDI), and Wafer Level Package (WLP). The LTCC has low integration level, and the moisture absorption, the maximum processing size and the large radio frequency loss of the material limit the further development of the LTCC on the millimeter wave packaging antenna; the HDI has low integration level and is mainly used for the frequency band of 20 GHz-40 GHz after being combined with a high integrated chip; WLP has high integration level, and can realize high-density, small-size and light-weight packaging.
In wafer level packaging, W-band signal interconnection transmission needs to be performed through a Polyimide (PI) Redistribution Layer (RDL) on the surface of a chip, but due to the limitations of a wafer level packaging process (the thickness of a PI dielectric Layer is thin, and the line width and the line distance of a metal line are limited), the design of a W-band 50-ohm transmission line is difficult, and the electromagnetic performance of the chip is affected when W-band signals are transmitted above the chip.
Disclosure of Invention
The invention aims to solve at least one technical problem in the prior art and provides a novel technical scheme of a W-band transceiving integrated phased array packaged antenna and a manufacturing process thereof.
According to a first aspect of the present application, there is provided a W-band transceiving integrated phased array package antenna, comprising:
an upper package including a first substrate, a first rewiring layer, and a second rewiring layer; the first substrate is provided with a first through hole, the first through hole penetrates through the upper surface and the lower surface of the first substrate, and a conductive material is filled in the first through hole; a first rewiring layer electrically connected with the conductive materials in the first through holes is arranged on the upper surface of the first substrate, a second rewiring layer electrically connected with the conductive materials in the first through holes is arranged on the lower surface of the first substrate, and first bumps are formed on the second rewiring layer;
the lower-layer packaging body comprises a second substrate, a transceiver chip, a third rewiring layer and a fourth rewiring layer; the second substrate is provided with a second through hole, the second through hole penetrates through the upper surface and the lower surface of the second substrate, and a conductive material is filled in the second through hole; the transceiver chip is embedded in the second substrate, and the second through holes are respectively positioned at two opposite sides of the transceiver chip; a third rewiring layer electrically connected with the conductive material in the second through hole is arranged on the upper surface of the second substrate; a fourth rewiring layer electrically connected with the conductive material in the second through hole is arranged on the lower surface of the second substrate, and the transceiver chip is electrically connected with the fourth rewiring layer;
the first bump is bonded with the third rewiring layer; and the W-band signal is transmitted to the first rewiring layer through the fourth rewiring layer, the conductive material in the second through hole, the third rewiring layer, the first bump, the second rewiring layer and the conductive material in the first through hole in sequence. Wherein, the first rewiring layer is an antenna layer.
Optionally, a second bump is formed on the fourth redistribution layer, and a BGA solder ball is implanted at the second bump of the fourth redistribution layer.
Optionally, the transceiver chip is a silicon-based CMOS chip.
Optionally, the conductive material in the first via and the main conductive material in the second via are both copper.
Optionally, the first bump is a Cu pillar Sn cap bump; the second salient point is a Cu column salient point.
According to a second aspect of the present application, there is provided a manufacturing process of a W-band transmit-receive integrated phased array packaged antenna, for manufacturing the W-band transmit-receive integrated phased array packaged antenna according to the first aspect, including the following steps:
firstly, punching a hole on a resin wafer core substrate to form a first through hole, filling a conductive material in the first through hole, and growing Cu bumps communicated with the conductive material in the first through hole on the upper surface and the lower surface of the resin wafer core substrate; secondly, pressing films on the upper surface and the lower surface of the resin wafer core substrate, and curing to form a Cu salient point so as to form an adapter plate; thirdly, reconstructing the adapter plate by using a wafer-level injection molding machine to form a first resin wafer with a preset size, arranging a first rewiring layer on the upper surface of the first resin wafer by using an RDL rewiring process, and arranging a second rewiring layer on the lower surface of the first resin wafer; finally, arranging a first bump on the second rewiring layer to form an upper-layer packaging body;
step two, firstly, mounting the transceiver chip and the adapter plate formed in the step one to a temporary carrier plate; secondly, reconstructing the transceiver chip and the adapter plate by using a wafer-level injection molding machine to form a second resin wafer with a preset size; finally, a fourth rewiring layer is arranged on the lower surface of the second resin wafer by an RDL rewiring process, second bumps are arranged on the fourth rewiring layer, and a third rewiring layer is arranged on the upper surface of the fourth rewiring layer to form a lower-layer packaging body;
bonding the upper-layer packaging body and the lower-layer packaging body through the first salient point and the third rewiring layer; then, the BGA solder balls are implanted at the second bumps of the fourth re-wiring layer.
Optionally, the interposer is a TGV interposer, a TSV interposer, or a TMV interposer.
Optionally, reconfiguring the interposer into a first resin wafer of a predetermined size using a wafer-level injection molding machine, comprising:
and mounting the adapter plate on the temporary carrier plate, and performing wafer-level injection molding on the adapter plate by using a wafer-level injection molding machine to reconstruct the adapter plate into a first resin wafer with a preset size.
Optionally, the step of providing a first redistribution layer on the upper surface of the first resin wafer and providing a second redistribution layer on the lower surface of the first resin wafer by using an RDL redistribution process includes:
removing the temporary carrier plate, turning over the first resin wafer, and forming a first rewiring layer on the upper surface of the first resin wafer by using an RDL rewiring process; and then, turning over the first resin wafer, thinning the lower surface of the first resin wafer to expose the conductive material, and forming a second rewiring layer on the lower surface of the first resin wafer by adopting an RDL rewiring process.
Optionally, the step of providing a fourth redistribution layer on the lower surface of the second resin wafer by using an RDL rewiring process, providing a second bump on the fourth redistribution layer, and providing a third redistribution layer on the upper surface includes:
arranging a fourth rewiring layer on the lower surface of the second resin wafer by adopting an RDL rewiring process, arranging a second bump on the fourth rewiring layer, and then forming an epoxy resin molding compound (EMC) layer coating the second bump by adopting a wafer-level injection molding process; then, turning over the second resin wafer, thinning the lower surface of the second resin wafer to expose the conductive material, and forming a third rewiring layer on the upper surface of the second resin wafer by adopting an RDL rewiring process; and finally, overturning the second resin wafer, thinning the EMC layer and exposing the second salient point.
One technical effect of the invention is that:
in the embodiment of the application, the W-band transceiving integrated phased-array packaged antenna is formed by stacking an upper layer package body and a lower layer package body, wherein the upper layer package body is embedded with a first through hole to realize the feeding of the antenna, and the lower layer package body is used for completing the integrated packaging of a transceiving chip and realizing the vertical transmission of 94GHz radio-frequency signals by embedding a second through hole.
Further, the surface of the transceiver chip faces downward, and the W-band signal is transmitted to the first redistribution layer, i.e., the antenna layer, sequentially through the fourth redistribution layer, the conductive material in the second via, the third redistribution layer, the first bump, the second redistribution layer, and the conductive material in the first via. Meanwhile, signals such as power signals, control signals, ground signals and intermediate frequency signals are transmitted to the PCB motherboard below the packaging antenna through the fourth rewiring layer, electromagnetic interference of radio frequency signals to internal circuits of the transceiver chip can be avoided through the layout mode, interconnection of W-band 50-ohm transmission lines is achieved, impedance matching is completed, and low transmission loss can be guaranteed. Meanwhile, by adopting the packaging framework, a smaller packaging body can be realized, a larger scanning angle is ensured, and an expandable function is realized.
Drawings
Fig. 1 is an exploded view of a W-band transmit-receive integrated phased array packaged antenna according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a W-band transmit-receive integrated phased array packaged antenna according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an interposer preform of a W-band transmit-receive integrated phased-array package antenna according to an embodiment of the present invention mounted on a temporary carrier;
fig. 4 is a schematic diagram illustrating a first resin wafer with a predetermined size formed by reconfiguring an interposer of a W-band transmit-receive integrated phased-array package antenna according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a first redistribution layer formed on an upper surface of a first resin wafer of a W-band transmit-receive integrated phased-array package antenna according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a W-band transmit-receive integrated phased-array package antenna according to an embodiment of the present invention, in which a second redistribution layer and a first bump are formed on a lower surface of a first resin wafer;
fig. 7 is a schematic diagram of a diced upper package of a W-band transmit-receive integrated phased-array packaged antenna according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating a transmitting chip of a W-band transceiving integrated phased-array packaged antenna, an interposer, and a temporary carrier according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a second resin wafer with predetermined sizes formed by reconfiguring a transceiver chip and an interposer of a W-band transceiver integrated phased-array packaged antenna according to an embodiment of the present invention;
fig. 10 is a schematic diagram illustrating a W-band transmit-receive integrated phased-array package antenna according to an embodiment of the present invention, wherein a fourth redistribution layer and a second bump are disposed on a lower surface of a second resin wafer;
fig. 11 is a schematic diagram of an EMC layer covering a second bump of a W-band transmit-receive integrated phased array package antenna according to an embodiment of the present invention;
fig. 12 is a schematic diagram illustrating a W-band transmit-receive integrated phased-array packaged antenna according to an embodiment of the present invention, wherein a third redistribution layer is disposed on a surface of a second resin wafer;
fig. 13 is a schematic diagram of a W-band transmit-receive integrated phased-array packaged antenna according to an embodiment of the invention, where EMC material of a second resin wafer is thinned and second bumps are exposed;
fig. 14 is a schematic diagram of a lower package dicing of a W-band transmit-receive integrated phased-array packaged antenna according to an embodiment of the present invention;
fig. 15 is a schematic diagram illustrating a stack of an upper package and a lower package of a W-band transceiver-integrated phased array package antenna according to an embodiment of the present invention;
fig. 16 is a schematic diagram illustrating a micro system package completed by implanting BGA solder balls of a W-band transmit-receive integrated phased array package antenna according to an embodiment of the present invention;
fig. 17 is a schematic diagram of a transition structure of a W-band signal from a terminal of a transceiver chip to an antenna feed port of a W-band transceiver integrated phased array package antenna according to an embodiment of the present invention;
FIG. 18 shows simulation results of transition structures of W-band signals from the output terminals of the transceiver chips to the antenna feed ports;
FIG. 19 is a simulation result of E-plane scanning of the W-band transmit-receive integrated phased array packaged antenna at a frequency point of 94 GHz;
fig. 20 shows a simulation result of H-plane scanning of the W-band transmit-receive integrated phased array packaged antenna at a frequency point of 94 GHz.
In the figure: 1. an upper package body; 11. a first substrate; 111. a first through hole; 12. a first rewiring layer; 13. a second rewiring layer; 14. a first bump; 2. a lower package; 21. a second substrate; 211. a second through hole; 22. a transceiver chip; 23. a third rewiring layer; 24. a fourth rewiring layer; 25. a second bump; 3. BGA solder balls; 4. a temporary carrier plate; 5. a patch panel; 6. and an EMC layer.
Detailed Description
Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise.
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The features of the terms first and second in the description and in the claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "a plurality" is two or more unless otherwise specified. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
Referring to fig. 1 and 2, according to a first aspect of the present application, a W-band transmit-receive integrated phased array package antenna is provided, which may be applied to working scenarios such as radar collision avoidance, detection imaging, backhaul communication, and the like. The W-band transceiving integrated phased-array packaged antenna comprises an upper-layer packaging body 1 and a lower-layer packaging body 2 which are stacked. The upper package 1 embeds the first through hole 111 to realize feeding of the antenna, and the lower package 2 completes integrated packaging of the transceiver chip 22 and realizes vertical transmission of 94GHz radio frequency signals through embedding the second through hole 211.
Specifically, the upper package includes a first substrate 11, a first redistribution layer 12, and a second redistribution layer 13; a first through hole 111 is formed in the first substrate 11, the first through hole 111 penetrates through the upper and lower surfaces of the first substrate 11, and a conductive material is filled in the first through hole 111; a first redistribution layer 12 electrically connected to the conductive material in the first through hole 111 is disposed on the upper surface of the first substrate 11, a second redistribution layer 13 electrically connected to the conductive material in the first through hole 111 is disposed on the lower surface of the first substrate 11, and a first bump 14 is formed on the second redistribution layer 13.
Further specifically, the lower package 2 includes a second substrate 21, a transceiver chip 22, a third redistribution layer 23, and a fourth redistribution layer 24; a second through hole 211 is formed in the second substrate 21, the second through hole 211 penetrates through the upper and lower surfaces of the second substrate 21, and a conductive material is filled in the second through hole 211; the transceiver chip 22 is embedded in the second substrate 21, and the plurality of second through holes 211 are respectively located at two opposite sides of the transceiver chip 22; a third rewiring layer 23 electrically connected with the conductive material in the second through hole 211 is arranged on the upper surface of the second substrate 21; a fourth redistribution layer 24 electrically connected to the conductive material in the second via hole 211 is disposed on the lower surface of the second substrate 21, and the transceiver chip 22 is electrically connected to the fourth redistribution layer 24.
In the embodiment of the present application, the first bump 14 and the third redistribution layer 23 are bonded, for example, a plurality of the second through holes 211 may be respectively located at two opposite sides of the transceiver chip 22; the W band signal is transmitted to the first rewiring layer 12, that is, the antenna layer, through the fourth rewiring layer 24, the conductive material in the second via 211, the third rewiring layer 23, the first bump 14, the second rewiring layer 13, and the conductive material in the first via 111 in this order.
The W-band transceiving integrated phased array packaged antenna avoids electromagnetic interference between W-band signals and internal circuits of the transceiving chip 22 through the layout design of a three-dimensional heterogeneous integrated architecture, and meanwhile, can realize W-band low-loss 50-ohm interconnection transmission. The antenna can realize high-density integration, simultaneously ensure a larger scanning angle and realize expandable antenna configuration.
It should be noted that the three-dimensional heterogeneous integrated architecture adopted by the invention can solve the problem that the electromagnetic performance of the chip is affected by the transmission of the W-band signal above the transceiver chip, and improve the electromagnetic compatibility. Furthermore, silicon-based CMOS chips have lower transmission losses and higher levels of integration than group iii v chips, which can meet demanding size and power requirements.
Optionally, a second bump 25 is formed on the fourth redistribution layer 24, and the BGA solder balls 3 are implanted at the second bump 25 of the fourth redistribution layer 24. The power supply signal, the control signal, the ground signal and the intermediate frequency signal are fanned into the BGA solder balls 3 through the fourth rewiring layer 24 and are connected to the lower PCB motherboard, the layout mode can avoid electromagnetic interference of radio frequency signals on internal circuits of the chip, interconnection of W-band 50-ohm transmission lines is achieved, impedance matching is completed, and lower transmission loss can be guaranteed. Meanwhile, by adopting the packaging framework, a smaller packaging body can be realized, a larger scanning angle is ensured, and an expandable function is realized.
Referring to fig. 17, fig. 17 is a schematic diagram of a transition structure of a W-band signal of the W-band transmit-receive integrated phased-array packaged antenna from a transmit-receive chip lead-out terminal to an antenna feed port, which can ensure low-loss transmission of the signal.
Optionally, the transceiver chip 22 is a silicon-based CMOS chip. The silicon-based COMS chip is adopted for carrying out radio frequency front end integrated packaging, and the performances of expandability, miniaturization, large scanning angle and the like are realized through the structural layout design.
Optionally, the conductive material in the first via 111 and the main conductive material in the second via 211 are both copper. This enables stable W-band signal transmission.
Optionally, the first bump 14 is a Cu stud Sn cap bump; the second bump 25 is a Cu stud bump. The first bump 14 can achieve better bonding with the third re-wiring layer 23, and the second bump 25 can achieve stable transmission of various signals.
According to a second aspect of the present application, a manufacturing process of a W-band transmit-receive integrated phased array packaged antenna is provided, which is shown in fig. 3 to 16. The method is used for manufacturing the W-band transceiving integrated phased array packaged antenna, and comprises the following steps:
first, a first through hole 111 is formed in the resin wafer core substrate, for example, the first through hole 111 is formed by mechanical drilling. Filling a conductive material in the first through hole 111, and growing Cu bumps communicated with the conductive material in the first through hole 111 on the upper surface and the lower surface of the resin wafer core substrate, wherein the metal filling in the first through hole 111 is realized by adopting an electroplating Cu process; secondly, pressing films on the upper surface and the lower surface of the resin wafer core substrate, curing and molding to expose the Cu salient points to form an adapter plate 5; thirdly, reconstructing the adapter plate 5 by using a wafer-level injection molding machine to form a first resin wafer with a preset size, arranging a first rewiring layer 12 on the upper surface of the first resin wafer by using an RDL rewiring process, and arranging a second rewiring layer 13 on the lower surface of the first resin wafer; finally, the first bump 14 is disposed on the second re-wiring layer 13 to form the upper package 1, and the upper package 1 is diced to complete the packaging of the antenna, see fig. 3 to 7.
Step two, firstly, mounting the transceiver chip 22 and the adapter plate 5 formed in the step one to the temporary carrier plate 4, for example, the adapter plate 5 is a TMV adapter chip, and the transceiver chip 22 is a 16-channel transceiver chip with frequency conversion; secondly, reconstructing the transceiver chip 22 and the adapter plate 5 by using a wafer-level injection molding machine to form a second resin wafer with a preset size, for example, forming an EMC layer 6 on the surfaces of the transceiver chip 22 and the adapter plate 5; finally, a fourth re-wiring layer 24 is arranged on the lower surface of the second resin wafer by using an RDL re-wiring process, second bumps 25 are arranged on the fourth re-wiring layer 24, and a third re-wiring layer 23 is arranged on the upper surface of the fourth re-wiring layer to form a lower package body 2, and the chip package is completed by dicing, as shown in fig. 8 to 14.
The first rewiring layer 12, the second rewiring layer 13, the third rewiring layer 23, and the fourth rewiring layer 24 each have a plurality of layers.
Step three, firstly, the upper layer packaging body 1 and the lower layer packaging body 2 are bonded through the first bump 14 and the third rewiring layer 23, and the step 15 is shown; then, the BGA balls 3 are implanted at the second bumps 25 of the fourth re-wiring layer 24, see fig. 16. Namely, the module of the upper-layer packaging body 1 and the module of the lower-layer packaging body 2 are stacked and bonded by using a high-precision stacking process; and (3) planting BGA solder balls 3 at the outer leading-out end of the integrated surface of the lower-layer packaging body 2 by using a single-chip ball planting process to finish the integrated packaging of the W-band AiP module.
In one specific embodiment, the second resin wafer with the preset size and the second resin wafer with the preset size are 12-inch resin wafers.
In the embodiment of the application, the manufacturing process of the W-band transmit-receive integrated phased-array packaging antenna adopts a wafer-level packaging tape-flow mode, is simple in process and is suitable for batch production. Meanwhile, the wafer level three-dimensional integration density is high, the size is small, and the interconnection wiring is short; the processing cost is low, and manufacturing cycle is fast, compares traditional tube shell pottery and seals, and the base plate plastic envelope, the cost reduces by a wide margin, does not receive tube shell, base plate material purchase influence, and the progress controllability is higher. This kind of little modularization is integrated, can carry out the secondary with other encapsulation modules and integrate, and the expansibility is higher, and the BGA encapsulation of final adoption maintains the dismantlement time short in the operating condition.
Optionally, the interposer 5 is a TGV (through glass via) interposer 5, a TSV (through silicon via) interposer 5, or a TMV (plastic through hole) interposer 5. This has expanded the scope of keysets 5 well, has guaranteed the stability of keysets 5 signal transmission.
Optionally, reconfiguring the interposer 5 into a first resin wafer of a preset size using a wafer-level injection molding machine, comprising:
the adapter plate 5 is mounted on the temporary carrier plate 4, and wafer-level injection molding is performed on the adapter plate 5 by using a wafer-level injection molding machine, for example, an EMC layer 6 is formed on the surface of the adapter plate, so that the adapter plate 5 is reconfigured to form a first resin wafer with a preset size. This makes the way of forming the first resin wafer simpler and more convenient to operate.
Optionally, the step of providing the first redistribution layer 12 on the upper surface of the first resin wafer and providing the second redistribution layer 13 on the lower surface of the first resin wafer by using an RDL redistribution process includes:
removing the temporary carrier plate 4, turning over the first resin wafer, and forming a first rewiring layer 12 on the upper surface of the first resin wafer by using an RDL rewiring process; then, the first resin wafer is turned over, the lower surface of the first resin wafer is thinned, the conductive material is exposed, and a second rewiring layer 13 is formed on the lower surface of the first resin wafer by using an RDL rewiring process.
In the above embodiment, the first redistribution layer 12 is provided on the upper surface of the first resin wafer, and the second redistribution layer 13 is provided on the lower surface thereof, which is relatively simple.
Optionally, the step of providing a fourth redistribution layer 24 on the lower surface of the second resin wafer by using an RDL redistribution process, providing a second bump 25 on the fourth redistribution layer 24, and providing a third redistribution layer 23 on the upper surface includes:
arranging a fourth re-wiring layer 24 on the lower surface of the second resin wafer by using an RDL re-wiring process, arranging a second bump 25 on the fourth re-wiring layer 24, and then forming an EMC layer 6 wrapping the second bump 25 by using a wafer-level injection molding process; then, turning over the second resin wafer, thinning the lower surface of the second resin wafer to expose the conductive material, and forming a third rewiring layer 23 on the upper surface of the second resin wafer by using an RDL rewiring process; finally, the second resin wafer is turned over again, the EMC layer is thinned, and the second bumps 25 are exposed.
In the above embodiment, the third redistribution layer 23 is provided on the upper surface of the second resin wafer, and the fourth redistribution layer 24 is provided on the lower surface, which is relatively simple, and the second bumps 25 can be protected well.
The simulation results of the W-band signal interconnection structure and the transmission structure related to the integrated architecture of the invention are shown in fig. 17 and fig. 18, and the chip Fanout is interconnected with the antenna through the electroplating bump after being packaged, so that the | S11| is less than or equal to-15 dB within the range of 80GHz-110GHz, and has lower transmission loss, thereby meeting the interconnection transmission requirements.
In addition, the size of the antenna unit is 1.25mm multiplied by 1.25mm, and the antenna unit are coupled by adding a metal through hole to inhibit coupling, so that better scanning performance is realized. Two-dimensional scanning simulation results of the antenna at a 94GHz frequency point are shown in fig. 19 and 20, and as the spacing between the E-plane units is 2mm, the scanning range can meet +/-30 degrees, the spacing between the H-plane units is 1.8mm, and the scanning range can meet +/-40 degrees. Finally, the size of the whole W-band (94 GHz) 64-channel transceiving integrated packaging antenna is 7.8mm multiplied by 7mm multiplied by 1.3mm, the antenna can be expanded in XY two dimensions, and application scenes such as imaging radars and communication can be supported.
Therefore, the W-band transceiving integrated phased-array packaged antenna manufactured by the manufacturing process of the W-band transceiving integrated phased-array packaged antenna uses a heterogeneous integrated resin-based wafer-level fan-out process, and realizes the W-band packaged antenna with low loss, 50-ohm transmission, expandability and a wide scanning angle through the design of a packaging framework. The interconnection loss of W-band signal transmission can be realized by simulation to be less than or equal to 1.5dB, the full-wave simulation azimuth plane scanning angle is +/-45 degrees, and the pitch plane scanning angle is +/-30 degrees. Meanwhile, a sparse array arrangement mode is adopted, so that the manufacturing cost of the antenna can be reduced.
It should be noted that, in the prior art, the W-band package antenna mostly adopts a flip-chip bonding method to interconnect the iii-v-group radio frequency chip and the antenna package, and in this layout method, the W-band signal passes through the upper side of the surface of the radio frequency chip, thereby affecting the electromagnetic performance of the radio frequency chip. The W-band transceiving integrated phased-array packaging antenna adopts a silicon-based CMOS chip (bare chip) to be packaged in a wafer-level plastic package fan-out mode, the surface of the silicon-based CMOS chip faces downwards, W-band signals are connected with an antenna feed end through the second through holes 211 on the two sides of the silicon-based CMOS chip and the first through holes 111 of the upper-layer packaging body, electromagnetic interference between the W-band signals and an internal circuit of the silicon-based CMOS chip is avoided, and meanwhile, low-loss 50-ohm interconnection transmission of the W-band can be achieved. The invention realizes high-density integration, ensures a larger scanning angle and realizes expandable antenna configuration. Therefore, the W-band transmit-receive integrated phased-array packaged antenna integrates the multifunctional transmit-receive chip 22 and the antenna array at high density, ensures the electromagnetic performance of the transmit-receive chip 22, can realize W-band low-loss 50-ohm interconnection transmission, and has the characteristics of expandability, low cost, high integration level and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the invention, and such modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A W-band transmit-receive integrated phased array packaged antenna, comprising:
an upper package including a first substrate, a first rewiring layer and a second rewiring layer; the first substrate is provided with a first through hole, the first through hole penetrates through the upper surface and the lower surface of the first substrate, and a conductive material is filled in the first through hole; a first rewiring layer electrically connected with the conductive material in the first through hole is arranged on the upper surface of the first substrate, a second rewiring layer electrically connected with the conductive material in the first through hole is arranged on the lower surface of the first substrate, and a first bump is formed on the second rewiring layer;
the lower-layer packaging body comprises a second substrate, a transceiver chip, a third rewiring layer and a fourth rewiring layer; the second substrate is provided with a second through hole, the second through hole penetrates through the upper surface and the lower surface of the second substrate, and a conductive material is filled in the second through hole; the transceiver chip is embedded in the second substrate, and the second through holes are respectively positioned at two opposite sides of the transceiver chip; a third rewiring layer electrically connected with the conductive material in the second through hole is arranged on the upper surface of the second substrate; a fourth rewiring layer electrically connected with the conductive material in the second through hole is arranged on the lower surface of the second substrate, and the transceiver chip is electrically connected with the fourth rewiring layer;
the first bump is bonded with the third rewiring layer; and the W-band signal is transmitted to the first rewiring layer through the fourth rewiring layer, the conductive material in the second through hole, the third rewiring layer, the first bump, the second rewiring layer and the conductive material in the first through hole in sequence.
2. The W-band transmit-receive integrated phased array package antenna according to claim 1, wherein a second bump is formed on the fourth redistribution layer, and a BGA solder ball is mounted on the second bump of the fourth redistribution layer.
3. The W-band transmit-receive integrated phased array package antenna according to claim 2, wherein the transmit-receive chip is a silicon-based CMOS chip.
4. The W-band transceiver-integrated phased array package antenna of claim 3, wherein the conductive material in the first via and the majority of the conductive material in the second via are copper.
5. The W-band transceiving integrated phased-array package antenna of claim 4, wherein the first bump is a Cu stud Sn cap bump; the second salient point is a Cu column salient point.
6. A manufacturing process of a W-band transmit-receive integrated phased array packaged antenna, which is used for manufacturing the W-band transmit-receive integrated phased array packaged antenna according to any one of claims 1 to 5, and comprises the following steps:
firstly, punching a hole on a resin wafer core substrate to form a first through hole, filling a conductive material in the first through hole, and growing Cu salient points communicated with the conductive material in the first through hole on the upper surface and the lower surface of the resin wafer core substrate; secondly, pressing films on the upper surface and the lower surface of the resin wafer core substrate, and curing to form a Cu salient point so as to form an adapter plate; thirdly, reconstructing the adapter plate by using a wafer-level injection molding machine to form a first resin wafer with a preset size, arranging a first rewiring layer on the upper surface of the first resin wafer by using an RDL rewiring process, and arranging a second rewiring layer on the lower surface of the first resin wafer; finally, arranging a first bump on the second rewiring layer to form an upper-layer packaging body;
step two, firstly, mounting the transceiver chip and the adapter plate formed in the step one to a temporary carrier plate; secondly, reconstructing the transceiver chip and the adapter plate by using a wafer-level injection molding machine to form a second resin wafer with a preset size; finally, a fourth rewiring layer is arranged on the lower surface of the second resin wafer by an RDL rewiring process, second bumps are arranged on the fourth rewiring layer, and a third rewiring layer is arranged on the upper surface of the fourth rewiring layer to form a lower-layer packaging body;
bonding the upper-layer packaging body and the lower-layer packaging body through the first salient point and the third rewiring layer; then, the BGA solder balls are implanted at the second bumps of the fourth re-wiring layer.
7. The manufacturing process of the W-band transmit-receive integrated phased-array packaged antenna according to claim 6, wherein the interposer is a TGV interposer, a TSV interposer or a TMV interposer.
8. The process of claim 6, wherein a wafer level injection molding machine is used to reconfigure the interposer to a first resin wafer of a predetermined size, comprising:
and mounting the adapter plate on the temporary carrier plate, and performing wafer-level injection molding on the adapter plate by using a wafer-level injection molding machine to reconstruct the adapter plate into a first resin wafer with a preset size.
9. The manufacturing process of a W-band transmit-receive integrated phased-array packaged antenna according to claim 8, wherein an RDL rewiring process is used to provide a first rewiring layer on the upper surface of the first resin wafer and a second rewiring layer on the lower surface, comprising:
removing the temporary carrier plate, turning over the first resin wafer, and forming a first rewiring layer on the upper surface of the first resin wafer by using an RDL rewiring process; and then, turning over the first resin wafer, thinning the lower surface of the first resin wafer to expose the conductive material, and forming a second rewiring layer on the lower surface of the first resin wafer by adopting an RDL rewiring process.
10. The manufacturing process of a W-band transmit-receive integrated phased-array package antenna according to claim 9, wherein an RDL rewiring process is used to provide a fourth rewiring layer on a lower surface of the second resin wafer, provide the second bump on the fourth rewiring layer, and provide the third rewiring layer on an upper surface, comprising:
arranging a fourth rewiring layer on the lower surface of the second resin wafer by adopting an RDL rewiring process, arranging a second bump on the fourth rewiring layer, and then forming an EMC layer wrapping the second bump by adopting a wafer-level injection molding process; then, turning over the second resin wafer, thinning the lower surface of the second resin wafer to expose the conductive material, and forming a third rewiring layer on the upper surface of the second resin wafer by adopting an RDL rewiring process; and finally, overturning the second resin wafer, thinning the EMC layer and exposing the second salient point.
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