CN115692209A - Composite layer circuit element and manufacturing method thereof - Google Patents

Abstract

The embodiment of the disclosure provides a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element comprises the following steps. A carrier plate is provided. Forming a first dielectric layer on the carrier plate, and patterning the first dielectric layer. And arranging the carrier plate with the first dielectric layer on the first curved surface mould and curing the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. And patterning the second dielectric layer. And arranging the carrier plate with the first dielectric layer and the second dielectric layer on the second curved surface mold and curing the second dielectric layer. The thickness of the protruding portion of the first curved surface mold is smaller than the thickness of the protruding portion of the second curved surface mold.

Description

Composite layer circuit element and manufacturing method thereof

The present disclosure is a divisional application of an invention patent application with an application number of 202110835017.9, entitled "composite layer circuit element and manufacturing method thereof", which was filed on 2021, month 07, and month 23.

Technical Field

Embodiments of the present disclosure relate to circuit devices, and more particularly, to a composite layer circuit device and a method for fabricating the same.

Background

With the increasing application of electronic devices, the process yield of electronic devices is concerned, and the conventional manufacturing method of the composite layer circuit component has the problem that the composite layer circuit component is easy to warp during the manufacturing process due to the difference between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of each layer in the composite layer circuit component, thereby affecting the structure or quality of the electronic device. Therefore, a method for manufacturing an electronic device is needed to reduce the above problems.

Disclosure of Invention

According to an embodiment of the present disclosure, a method for manufacturing a multi-layer circuit device includes the following steps. A carrier plate is provided. A first dielectric layer is formed on the carrier. The first dielectric layer is patterned. And arranging the carrier plate with the first dielectric layer on the first curved surface mould and curing the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. And patterning the second dielectric layer. And arranging the carrier plate with the first dielectric layer and the second dielectric layer on the second curved surface mold and curing the second dielectric layer. The thickness of the protruding portion of the first curved surface mold is smaller than the thickness of the protruding portion of the second curved surface mold.

According to an embodiment of the present disclosure, a composite layer circuit device includes a first dielectric layer, a first circuit layer disposed on the first dielectric layer, and a second dielectric layer disposed on the first circuit layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

Drawings

FIG. 1 is a flow chart of a method for fabricating a multi-layer circuit device according to an embodiment of the present disclosure;

fig. 2A to fig. 2G are schematic cross-sectional views illustrating a manufacturing process of a multi-layer circuit device according to an embodiment of the disclosure;

fig. 2H is a schematic cross-sectional view of an electronic device including a multi-layer circuit element according to an embodiment of the disclosure.

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity and brevity of the drawings, the various drawings in the present disclosure depict only some of the electronic devices and are not necessarily drawn to scale. In addition, the number and size of the elements in the figures are merely illustrative and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the following description and appended claims to refer to particular elements. Those skilled in the art will appreciate that electronic device manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in function but not name. In the following specification and claims, the words "comprise", "comprising", "have", and the like are open-ended words, and thus should be interpreted to mean "including, but not limited to, \8230;". Thus, when the terms "comprises," "comprising," and/or "having" are used in the description of the present disclosure, they specify the presence of stated features, regions, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, and/or components.

Directional phrases used herein include, for example: "upper", "lower", "front", "rear", "left", "right", etc., refer only to the orientation of the figures. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. In the drawings, which illustrate general features of methods, structures, and/or materials used in certain embodiments. These drawings, however, should not be construed as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various film layers, regions, and/or structures may be reduced or exaggerated for clarity.

It will be understood that when an element or layer is referred to as being "connected to" another element or layer, it can be directly connected to the other element or layer or intervening elements or layers may be present. When an element is referred to as being "directly connected to" another element or layer, there are no intervening elements or layers present between the two. In addition, when a member is referred to as being "coupled to" another member (or a variation thereof), it may be directly connected or electrically connected to the other member or indirectly connected or electrically connected to the other member through one or more members.

In the present disclosure, the length and the width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison.

The terms "about," "equal," or "the same," "substantially," or "approximately" are generally construed as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

The term "between a and B" is to be interpreted to include the case where at least one of a and B or both are included, as well as other values between a and B.

The structure (or layer, component, substrate) located on another structure (or layer, component, substrate) described in the present disclosure may refer to two structures adjacent to each other and directly connected, or may refer to two structures adjacent to each other and not directly connected, where the indirect connection refers to two structures having at least one secondary structure (or secondary layer, secondary component, secondary substrate, secondary space) between them, the lower surface of one structure is adjacent to or directly connected to the upper surface of the secondary structure, the upper surface of the other structure is adjacent to or directly connected to the lower surface of the secondary structure, and the secondary structure may be a single-layer or multi-layer solid structure or a non-solid structure, without limitation. In the present disclosure, when a structure is "disposed on" another structure, it may mean that the structure is "directly" on the other structure or "indirectly" on the other structure, that is, at least one structure is interposed between the structure and the other structure.

The terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, the discussion of a "first element," "component," "region," "layer," or "portion" below is intended to be inclusive in a manner separate from a "second element," "component," "region," "layer," or "portion," and not intended to limit the order or particular elements, components, regions, layers, and/or portions.

The electronic device may have a good electronic effect through the composite layer electronic component of the embodiment of the disclosure, wherein the electronic device may include a display device, an encapsulation device, a backlight device, an antenna device, a sensing device, or a splicing device, but not limited thereto. The electronic device can be a bendable or flexible electronic device. The display device may be a non-self-luminous type display device or a self-luminous type display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasonic waves, but not limited thereto. The electronic devices may include passive devices and active devices, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include, for example, an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. The present disclosure will be described below with respect to a composite layer electronic device as an electronic device or a splicing device, but the present disclosure is not limited thereto.

In the present disclosure, various embodiments described below can be mixed and matched without departing from the spirit and scope of the present disclosure, for example, some features of one embodiment can be combined with some features of another embodiment to form another embodiment.

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 is a flowchart illustrating a method for fabricating a multi-layer circuit device according to an embodiment of the disclosure. Fig. 2A to fig. 2G are schematic cross-sectional views illustrating a manufacturing process of a multi-layer circuit device according to an embodiment of the disclosure. For clarity of the drawings and ease of illustration, several components are omitted from fig. 2A-2G. Referring to fig. 1, in an embodiment of the present disclosure, a method S10 for manufacturing a multi-layer circuit device 100 includes the following steps. First, in step S110, a carrier 300 is provided. Next, in step S120, a first dielectric layer 110 is formed on the carrier 300. In step S130, the first dielectric layer 110 is patterned. In step S140, the carrier formed with the first dielectric layer 110 is disposed on the first curved mold 200 and the first dielectric layer 110 is cured, wherein the first curved mold 200 has a protrusion 210, and the protrusion 210 has a thickness H1. In step S150, a second dielectric layer 120 is formed on the first dielectric layer 110. In step S160, the second dielectric layer 120 is patterned. In step S170, the carrier 300 formed with the first dielectric layer 110 and the second dielectric layer 120 is disposed on the second curved mold 200A and the second dielectric layer 120 is cured, wherein the second curved mold 200A has a protrusion 210A, and the protrusion 210A has a thickness H2. In the step of curing the first dielectric layer 110 or the second dielectric layer 120, the first dielectric layer 110 or the second dielectric layer 120 is cured by, for example, a heating process to be more rigid, which will be described in detail later. Since the thermal expansion coefficient of the carrier 300 is different from that of the dielectric layer, in the step of curing the first dielectric layer 110 or the second dielectric layer 120, the carrier 300 may have a warpage force to warp the carrier 300 toward the first dielectric layer 110 or the second dielectric layer 120. For example, the carrier may have an inner surface S1 and an outer surface S2, the inner surface S1 is closer to the first dielectric layer 110 or the second dielectric layer 120 than the outer surface S2, and the above-mentioned "the carrier 300 is warped toward the first dielectric layer 110 or the second dielectric layer 120" means that the inner surface S1 is compressed due to the warping, such that an area of a plane (as shown in fig. 2A) formed by projecting the inner surface S1 to the X axis and the Y axis is smaller than an area of a plane (as shown in fig. 2A) formed by projecting the outer surface S2 to the X axis and the Y axis, wherein a top view direction (as shown in fig. 2A, the Z axis) is perpendicular to the X axis and the Y axis, respectively.

In an embodiment of the present disclosure, by providing the first curved mold 200 or the second curved mold 200A in the step of curing the first dielectric layer 110 and/or the second dielectric layer 120, the protrusion 210 of the first curved mold 200 or the protrusion 210A of the second curved mold 200A may generate a bending force to the carrier 300, which may, for example, cause the carrier 300 to bend along the shape of the first curved mold 200 or the second curved mold 200A (details of the bending force are described later), and the bending force is, for example, substantially opposite to the direction of the warpage force of the carrier 300, thereby reducing the warpage problem.

The method for manufacturing the multi-layer circuit device 100 will be briefly described with reference to the manufacturing flow shown in fig. 2A to 2G. The method for manufacturing the composite layer circuit element 100 of the present disclosure can make the composite layer circuit element 100 have good structural strength or quality.

Referring to fig. 2A, first, in step S110, a carrier 300 is provided. In some embodiments, the material of the carrier 300 may include organic or inorganic materials, such as glass, quartz, sapphire (sapphire), ceramic, stainless steel, silicon wafer, molding compound (e.g., resin, epoxy, silicone), other suitable substrate materials, or combinations thereof, but is not limited thereto. In some embodiments, the thickness T of the carrier 300 can be between 0.5 millimeters (mm) and 1.5mm (0.5 mm < T < 1.5 mm) or between 0.7mm (mm) and 1.3mm (0.7 mm < T < 1.3 mm), but not limited thereto. The thickness T may be defined as an average of thicknesses of any three regions of the carrier plate 300 measured in a normal direction of the carrier plate 300. In some embodiments, when the carrier 300 is substantially rectangular, the length L of the side of the carrier 300 may be, for example, but not limited to, between 600mm and 800mm (600 mm ≦ length L ≦ 800 mm) or between 650mm and 750mm (650 mm ≦ length L ≦ 750 mm). For example, when the carrier 300 is substantially square, the length L may be defined as the length of the side of the carrier 300, and when the carrier 300 is in other shapes, the carrier 300 may be framed by a minimum rectangle, for example, and the length L may be the length of the long side of the minimum rectangle, for example. In some embodiments, the carrier 300 has a Coefficient of Thermal Expansion (CTE) between 2 ppm/deg.c and 10 ppm/deg.c (2 ppm/deg.c. And 10 ppm/deg.c) or between 4 ppm/deg.c and 8 ppm/deg.c (4 ppm/deg.c and 8 ppm/deg.c), but not limited thereto.

In some embodiments, a release layer 310 is optionally disposed on the carrier 300.

Next, a first seed layer 330 may be sequentially disposed on the release layer 310. The release layer 310 may be removed in a subsequent step. In some embodiments, the release layer 310 may be an epoxy-based heat release material that loses its adhesive properties when heated, such as, but not limited to, a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 310 may include an Ultraviolet (UV) adhesive, and the release layer 310 may be an ultraviolet adhesive that loses its adhesive property when exposed to ultraviolet light (UV), but is not limited thereto.

In some embodiments, the first seed layer 330 is formed by physical vapor deposition (pvd), chemical vapor deposition (cvd), or electroplating. The material of the first seed layer 330 includes, but is not limited to, titanium, copper, or other suitable materials. In some embodiments, the first seed layer 330 comprises a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the first seed layer 330 may include, but is not limited to, a titanium layer and a copper layer on the titanium layer.

A layer of conductive material (not shown) is then formed on the first seed layer 330, which may be formed, for example, by electroplating or other suitable means. Next, the conductive material layer is patterned. In detail, a patterned photoresist is formed on the conductive material layer to form a mask. Then, the conductive material exposed by the mask is etched to form a plurality of conductive structures 111 on the first seed layer 330. It should be noted that fig. 2A only schematically illustrates two conductive structures 111, however, the embodiments of the disclosure are not limited to the number and/or the shape of the conductive structures 111. The number of the conductive structures 111 may be less than or more than two, depending on design requirements.

In some embodiments, the material of the conductive material layer (or conductive structure 111) includes, for example, a metal or a metal alloy. For example, the material of the conductive material layer (or the conductive structure 111) may include copper, titanium, tungsten, aluminum, other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the conductive structure 111 may be stacked by a single layer of conductive material or multiple layers of conductive material. In some embodiments, the thickness of conductive structure 111 is between about 3 microns and 20 microns (3 μm and 20 μm) or between 4 microns and 18 microns (4 μm and 18 μm), but not limited thereto.

Referring to fig. 1 and fig. 2B, in step S120, a first dielectric layer 110 is formed on the carrier 300, and in step S130, the first dielectric layer 110 is patterned, and a cross-sectional structure after step S130 is shown in fig. 2B. Specifically, the first dielectric layer 110 may be disposed on the first seed layer 330 and cover the conductive structure 111, followed by patterning the first dielectric layer 110. The step of patterning the first dielectric layer 110 includes "removing a portion of the first dielectric layer 110 corresponding to the conductive structure 111 to expose the surface of the conductive structure 111", as shown in fig. 2B. In detail, the method for patterning the first dielectric layer 110 may include disposing a patterned mask on the first dielectric layer 110, and etching (e.g., wet etching or dry etching) the first dielectric layer 110. The patterned first dielectric layer 110 may have a plurality of first openings O1, and the plurality of first openings O1 may expose the conductive structures 111, for example. In other words, the first opening O1 may overlap the conductive structure 111 in the normal direction of the carrier 300.

In some embodiments, the first dielectric layer 110 may have a thickness T1, and the thickness T1 may be defined as the maximum thickness of the first dielectric layer 110 in the normal direction of the carrier 300 in a cross-section. In some embodiments, the thickness T1 of the first dielectric layer 110 is, for example, between 5 μm and 25 μm (5 μm and 25 μm), or between 10 μm and 20 μm (10 μm and 20 μm), but not limited thereto.

In some embodiments, the material of the first dielectric layer 110 may include an organic insulating layer or an inorganic insulating layer, and the material may include a photosensitive polyimide material, an organic polymer material, a photoresist material, or other suitable materials. In some embodiments, the first dielectric layer 110 may include a Polyimide (PI), a polyamide (polyamide), a Polybenzoxazole (PBO), an acrylic (acrylic), a siloxane (siloxane), an ajinomoto-buied-up layer (ABF), a cyclic olefin copolymer (cyclo olefin polymer), other suitable materials, or a combination thereof, but is not limited thereto.

In some embodiments, the coefficient of thermal expansion of the first dielectric layer 110 is between 3 ppm/deg.C and 80 ppm/deg.C (3 ppm/deg.C. And 80 ppm/deg.C), between 10 ppm/deg.C and 70 ppm/deg.C (10 ppm/deg.C. And 70 ppm/deg.C), or between 15 ppm/deg.C and 65 ppm/deg.C (15 ppm/deg.C and 65 ppm/deg.C), but not limited thereto.

Referring to fig. 1 and fig. 2C, next, in step S140, the carrier 300 formed with the first dielectric layer 110 is disposed on the first curved mold 200, and the first dielectric layer 110 is cured, wherein the first curved mold 200 has a protrusion 210, and the protrusion 210 has a thickness H1. In some embodiments, the thermal expansion coefficient of the first curved mold 200 may be similar to that of the carrier plate 300, for example, but is not limited thereto. In some embodiments, the coefficient of thermal expansion of the first curve mold 200 may be less than or equal to 10 ppm/deg.C or less than or equal to 8 ppm/deg.C, but is not limited thereto. In some embodiments, the hardness of the first curved mold 200 may be, for example, less than that of the carrier 300, so as to reduce the risk of scratching the carrier 300, but is not limited thereto.

In some embodiments, the first curved mold 200 may have a base plate 211 and a protrusion 210, the protrusion 210 being connected to the base plate 211. In some embodiments, the material of the master 211 may be the same as or different from the material of the projections 210. In some embodiments, the master 211 and the projections 210 may be, for example, integrally formed.

In some embodiments, the surface 201 of the master 211 may, for example, be coupled to the curved surface 205 of the projection 210

The curved surface 205 may contact the carrier 300. In some embodiments, the curved surface 205 has a vertex 203 that is located at the highest height of the curved surface 205. In some embodiments, the protrusion 210 of the first curved mold 200 has a thickness H1, and the thickness H1 can be defined as the distance between the vertex 203 and the upper surface 201 in the normal direction of the master 211 (e.g., the direction of the Z-axis in the figure). The thickness H1 of the protrusion 210 of the first curved mold 200 ranges from 0.1mm to 0.4mm (0.1 mm ≦ thickness H1 ≦ 0.4 mm) or from 0.15mm to 0.35mm (0.15 mm ≦ thickness H1 ≦ 0.35 mm), but not limited thereto.

In some embodiments, the carrier plate 300 formed with the first dielectric layer 110 may be disposed on the first curved mold 200, and the carrier plate 300 may be adjacent to or contact the protrusion 210 of the first curved mold 200. In some embodiments, the protrusion 210 of the first curved mold 200 has, for example, a plurality of holes (not shown). In some embodiments, during the step of curing the first dielectric layer 110, a vacuum tool (not shown) may vacuum-adsorb the carrier 300 through the holes, for example, so that the carrier 300 is adsorbed on the curved surface 205 of the protrusion 210, thereby forming a bending force on the carrier 300. As described above, the first curved mold 200 can generate a bending force opposite to the warpage direction to the carrier 300, so that the carrier 300 can be bent substantially along the protrusion 120 of the first curved mold 200, thereby reducing the warpage problem of the composite layer circuit device 100. The method for manufacturing the composite layer circuit element 100 of the present disclosure can make the composite layer circuit element 100 have good structural strength or quality.

In some embodiments, in the step of curing the first dielectric layer 110, a portion of the carrier 300 may be, for example, in contact with the first curved mold 200 (e.g., the protrusion 210), and another portion of the carrier 300 may not be, for example, in contact with the first curved mold 200, such that a gap SP may be formed between the carrier 300 and the protrusion 210 of the portion of the first curved mold 200. In some embodiments, the plurality of holes (not shown) may be distributed only in a portion of the protrusion 210, for example, the holes may be distributed only in a central portion of the protrusion 210, so that the other portion of the carrier 300 cannot be adsorbed on the protrusion 210, and a gap SP may be formed between the carrier 300 and the portion of the protrusion 210 of the first curved mold 200, but is not limited thereto. Through the above design, in the step of curing the first dielectric layer 110, the risk of the carrier 300 being cracked due to the excessive bending force caused by the first curved surface mold 200 being completely adsorbed on the protrusion 210 of the first curved surface mold 200 can be reduced, but not limited thereto.

In some embodiments, the step of curing the first dielectric layer 110 includes baking the first dielectric layer 110, wherein the baking includes placing the first dielectric layer 110 in an environment with an oxygen concentration less than 100ppm for a baking time of more than about 3 hours, for example, but not limited to, between 180 ℃ and 350 ℃ (180 ℃ ≦ 350 ℃). In some embodiments, the first dielectric layer 110 may be baked, for example, in a bake chamber under a vacuum environment. In other embodiments, the first dielectric layer 110 may be in nitrogen (N) ₂ ) The baking is performed in a baking oven under the environment of (2), but not limited thereto.

Referring to fig. 1 and fig. 2D, similarly, a second seed layer 113 is then formed on the upper surface 110T of the first dielectric layer 110, and the second seed layer 113 may, for example, partially fill the opening O1 of the first dielectric layer 110. The second seed layer 113 may be formed of a material or in a manner similar to the first seed layer 330. Next, a conductive material layer is disposed on the second seed layer 113, a patterned photoresist is formed on the conductive material layer to form a mask, the conductive material exposed by the mask and the second seed layer 113 are etched to pattern the conductive material layer and the second seed layer 113, and the patterned conductive material layer forms a plurality of conductive structures 116.

Referring to fig. 1 and fig. 2E, next, in step S150, a second dielectric layer 120 is formed on the first dielectric layer 110. In detail, a first circuit layer (including the conductive structure 116) is disposed on the first dielectric layer 110, and a second dielectric layer 120 is disposed on the first circuit layer (including the conductive structure 116). In other words, the second dielectric layer 120 may be disposed on the upper surface 110T of the first dielectric layer 110 and the conductive structure 116, for example. In some embodiments, the second dielectric layer 120 has a thickness T2. The thickness T2 may be defined as the maximum thickness of the second dielectric layer 120 in the normal direction of the carrier 300 in a cross section. In some embodiments, the thickness T2 of the second dielectric layer 120 is, for example, between 5 μm and 25 μm (5 μm and 25 μm) or between 8 μm and 20 μm (8 μm and 20 μm), but not limited thereto.

In some embodiments, the thickness T1 of the first dielectric layer 110 may be greater than the thickness T2 of the second dielectric layer 120. In some embodiments, the ratio of the thickness T1 of the first dielectric layer 110 to the thickness T2 of the second dielectric layer 120 may be between 1.5 and 10 (1.5 ≦ T1/T2 ≦ 10) or between 2 and 5 (2 ≦ T1/T2 ≦ 5), but not limited thereto. Since the more dielectric layers the composite layer circuit element 100 is stacked, the greater the degree of warpage may be, the severity of warpage may be reduced by designing the thickness of the dielectric layer of the nth layer to be thinner than the thickness of the dielectric layer of the mth layer, where M is less than N. For example, the thickness T2 of the second dielectric layer 120 to be disposed on the first dielectric layer 110 may be smaller than the thickness T1 of the first dielectric layer 110, which may reduce the warpage of the stacked composite layer circuit device 100.

In some embodiments, the material of the second dielectric layer 120 is the same as or different from the material of the first dielectric layer 110, and the material of the second dielectric layer 120 can refer to the material of the first dielectric layer 110, and thus is not described herein again. In some embodiments, the second dielectric layer 120 has a thermal expansion coefficient between 3 ppm/deg.C and 80 ppm/deg.C (3 ppm/deg.C. And 80 ppm/deg.C), between 10ppm and 70ppm (10 ppm/deg.C. And 70 ppm/deg.C), or between 15ppm and 65ppm (15 ppm/deg.C. And 65 ppm/deg.C), but not limited thereto.

Next, referring to fig. 1 and fig. 2E, in step S160, the second dielectric layer 120 is patterned. The method for patterning the second dielectric layer 120 may be similar to the method for patterning the first dielectric layer 100, and thus is not described herein again. The patterned second dielectric layer 120 may have a plurality of second openings O2, and the plurality of second openings O2 may, for example, expose a portion of the conductive structure 116.

Referring to fig. 1 and fig. 2F, in step S170, the carrier 300 formed with the first dielectric layer 110 and the second dielectric layer 120 is disposed on the second curved mold 200A, and the second dielectric layer 120 is cured, wherein the second curved mold 200A has a protrusion 210A, and the protrusion 210A has a thickness H2. In some embodiments, the material of the second curve mold 200A is similar to the material of the first curve mold 200, and the thermal expansion coefficient or hardness characteristics thereof can be referenced to the first curve mold 200.

It is noted that the second curved surface mold 200A differs from the first curved surface mold 200 in that the thickness H1 of the projecting portion of the first curved surface mold 200 may be, for example, less than the thickness H2 of the projecting portion of the second curved surface mold 200A. In detail, the second curved surface mold 200A has a bottom plate 211A and a protrusion 210A, and the protrusion 210A is connected to the bottom plate 211A. In some embodiments, the material of the master 211A and the material of the projections 210A may be the same or different. In some embodiments, the master 211A and the projections 210A may be integrally formed, for example. In some embodiments, the surface 201A of the master 211A may be connected to the curved surface 205A of the protrusion 210A, for example, and the curved surface 205A may contact the carrier 300. In some embodiments, the curved surface 205A has an apex 203A located at the highest height of the curved surface 205A. The convex portion 210A of the second curved surface mold 200A has a thickness H2, and the thickness H2 can be defined as the distance between the vertex 203A and the upper surface 201A in the normal direction (the Z-axis direction in the figure) of the master 211A. The thickness H2 of the protrusion 210A of the second curved mold 200A is between 0.3mm and 0.8mm (0.3 mm ≦ thickness H2 ≦ 0.8 mm), but not limited thereto.

In some embodiments, the ratio of the thickness H1 of the protrusion 210 of the first curved mold 200 to the thickness H2 of the protrusion 210A of the second curved mold 200A may be between 1 and 5 (1 < thickness H1/thickness H2 ≦ 5) _ or between 1 and 3 (1 < thickness H1/thickness H2 ≦ 3) _ or between 1 and 2 (1 < thickness H1/thickness H2 ≦ 2), but is not limited thereto.

In some embodiments, the coefficient of thermal expansion of the second curved mold 200A may be less than or equal to 10 ppm/c or less than or equal to 8 ppm/c, but is not limited thereto. In some embodiments, the hardness of the second curved mold 200A may be, for example, less than that of the carrier 300, so as to reduce the risk of scratching the carrier 300, but is not limited thereto.

In some embodiments, the carrier 300 formed with the first dielectric layer 110 and the second dielectric layer 120 may be disposed on the second curved mold 200A, for example, and the carrier 300 may be adjacent to or contact the protrusion 210A of the second curved mold 200A. In some embodiments, the projections 210A of the second curve mold 200A have, for example, a plurality of holes (not shown). In some embodiments, during the step of curing the second dielectric layer 120, a vacuum tool (not shown) may vacuum-adsorb the carrier 300 through the holes, for example, so that the carrier 300 is adsorbed on the curved surface 205A of the protrusion 210A, thereby forming the bending force as described above. As described above, the second curved surface mold 200A can generate a bending force opposite to the warping direction to the carrier plate 300, for example, so that the carrier plate 300 can be bent substantially along the protruding portion 120A of the second curved surface mold 200A, thereby reducing the warping problem of the composite layer circuit device 100. The method for manufacturing the multi-layer circuit device 100 according to the present disclosure can make the multi-layer circuit device 100 have good structural strength or quality.

In some embodiments, in the step of curing the second dielectric layer 120, a portion of the carrier 300 may be, for example, in contact with the second curved mold 200A (e.g., the protrusion 210A), and another portion of the carrier 300 may not be, for example, in contact with the second curved mold 200A, such that a gap SP may be formed between the carrier 300 and the protrusion 210A of the portion of the second curved mold 200A. In some embodiments, the plurality of holes (not shown) may be distributed only in a portion of the protrusion 210A, for example, the holes (not shown) may be distributed only in a central portion of the protrusion 210A, so that a portion of the carrier 300 cannot be adsorbed on the protrusion 210A, and a gap SP may be formed between the carrier 300 and the portion of the protrusion 210A of the second curved mold 200, but not limited thereto. Through the above design, in the step of curing the second dielectric layer 120, the risk of cracking of the carrier 300 caused by an excessive bending force due to the second curved surface mold 200A completely adhering to the protrusion 210A of the second curved surface mold 200A can be reduced, but not limited thereto.

In some embodiments, the step of curing the second dielectric layer 120 includes performing a baking process on the second dielectric layer 120, wherein the conditions of the baking process may be similar to those of the baking process for curing the first dielectric layer 110.

Referring to fig. 2G, a third seed layer 123 is formed on the upper surface 120T of the second dielectric layer 120, and the third seed layer 123 may be filled in the opening O2 of the second dielectric layer 120, for example. Next, a conductive material layer is disposed on the third seed layer 123, and then the conductive material layer and the third seed layer 123 are patterned, so that the patterned conductive material layer forms a plurality of conductive structures 126. The conductive structure 126 can be formed by patterning the conductive material layer as described above with reference to the formation of the plurality of conductive structures 111. Thus, the manufacturing of the composite layer circuit element 100 is substantially completed. It is noted that the multi-layer circuit device 100 of the present disclosure is illustrated as a stacked configuration as shown in fig. 2G, but is not limited thereto. In other embodiments, the number of layers, such as seed layers, conductive structures and/or dielectric layers, or the manner of connection of the composite layer circuit element 100 may be varied as desired. It should be noted that the method for manufacturing the composite layer circuit device 100 of the present disclosure is only illustrated as using the first curved mold 200 and the second curved mold 200A, but is not limited thereto. In other embodiments, the number of curved molds used in the method for manufacturing the composite layer circuit device 100 may be varied according to the number of dielectric layers to be cured.

Fig. 2H is a schematic cross-sectional view of an electronic device including a multi-layer circuit element according to an embodiment of the disclosure. Several elements are omitted from fig. 2H for clarity and ease of illustration. Referring to fig. 2H, the carrier 300, the release layer 310, and the first seed layer 330 are removed. For example, the carrier plate 300, the release layer 310 and/or the first seed layer 330 may be removed by a laser or other suitable methods, but is not limited thereto. In addition, by designing the thickness T1 of the first dielectric layer 110 to be greater than the thickness T2 of the second dielectric layer 120 according to the present disclosure, the effect on the composite layer circuit device when the carrier 300, the release layer 310 and/or the first seed layer 330 are removed can be reduced. In detail, a portion of the first dielectric layer 110 may be slightly removed or damaged during the process of removing the carrier 300, the release layer 310 and/or the first seed layer 330, and the design of the thickness T1 of the first dielectric layer 110 is thicker, so that the first dielectric layer 110 is thinned, which may affect the yield of the composite layer circuit device.

Then, external electronic components may be selectively bonded to the composite layer circuit component 100 to form the electronic device 10. For example, the external electronic component may include the first electronic component 400 or the second electronic component 400A. The first electronic element 400 and the second electronic element 400A may include, for example, an integrated circuit chip (IC chip), a Light Emitting Diode (LED), or other suitable electronic elements or circuit elements, but not limited thereto. In some embodiments, a step of disposing an external electronic component may be performed before the step of removing the carrier 300, and the embodiments of the present disclosure are not limited thereto.

In some embodiments, the first electronic component 400 can be, for example, a light emitting diode, but is not limited thereto. The first electronic component 400 can be electrically connected to the multi-layer circuit component 100 through the conductive bump 420. The second electronic component 400A can be, for example, but not limited to, an integrated circuit chip. In some embodiments, the second electronic component 400A may be electrically connected to the multi-layer circuit component 100 through the conductive bump 420A. Thus, the composite layer circuit device 100 can be applied to a light emitting display device or other suitable electronic devices. The electronic device 10 including the composite layer circuit element 100 may have good structural strength or quality.

In some embodiments, the method of fabricating the multi-layer circuit device of the present disclosure may be applied to fabricate a semiconductor package type electronic device, such as a system on chip (SoC), a System In Package (SiP), or other suitable electronic devices. Specifically, the method for manufacturing the composite layer circuit element disclosed by the invention can be applied to a method for manufacturing a redistribution layer first (RDL first), a method for manufacturing a chip first/face up (chip first/face down) or a method for manufacturing a chip first/face down (chip first/face down). In the method for fabricating the redistribution layer in advance of the multi-layer circuit device according to an embodiment of the present disclosure, the carrier 300 may include, but is not limited to, glass, quartz, sapphire, ceramic, stainless steel, silicon wafer, encapsulant (e.g., resin, epoxy, silicone compound), other suitable substrate materials, or a combination thereof. In the die-first/face-up method and the die-first/face-down method, the carrier 300 may include, but is not limited to, an integrated circuit chip (integrated circuit chip) encapsulated by an encapsulant (e.g., epoxy resin, organosilicon compound), a silicon wafer, other suitable substrate materials, or a combination thereof. In some embodiments, in the pre-processing method of the redistribution layer, the carrier 300 may be removed after the redistribution layer is formed, so that the redistribution layer may be bonded to a component, such as an integrated circuit chip and/or a printed circuit board, in a subsequent process, but not limited thereto. In some embodiments, in the die-first/face-up manufacturing method and the die-first/face-down manufacturing method, a release layer may be optionally disposed on the carrier 300 or not, so as to bond a component, such as a printed circuit board, in a subsequent process, but not limited thereto.

In summary, in the multi-layer circuit device according to an embodiment of the disclosure, since the curved mold is provided in the step of curing the dielectric layer, the carrier can be bent toward the curved mold during the curing of the dielectric layer to offset the warpage force during the curing, so that the warpage degree of the dielectric layer and the carrier after the curing can be reduced to provide good structural strength or quality of the multi-layer circuit unit. In addition, the thickness of the dielectric layer can be adjusted to reduce the overall warping degree of the composite layer circuit unit.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for manufacturing a composite layer circuit component, comprising:

providing a carrier plate;

forming a first dielectric layer on the carrier plate;

patterning the first dielectric layer;

arranging the carrier plate with the first dielectric layer on a first curved surface mold and curing the first dielectric layer;

forming a second dielectric layer on the first dielectric layer;

patterning the second dielectric layer; and

arranging the carrier plate with the first dielectric layer and the second dielectric layer on a second curved surface mold and curing the second dielectric layer,

wherein the thickness of the protruding portion of the first curved surface mold is smaller than the thickness of the protruding portion of the second curved surface mold.

2. The method of claim 1, wherein in the step of curing the first dielectric layer, a gap is formed between the carrier and a portion of the protrusion of the first curved mold.

3. The method of claim 1, wherein in the step of curing the second dielectric layer, a gap is formed between the carrier and a portion of the protrusion of the second curved mold.

4. The method of claim 1, wherein the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

5. The method of claim 1, wherein the coefficient of thermal expansion of the first curved mold or the second curved mold is less than or equal to 10ppm/° c.

6. The method of claim 1, wherein the material of the carrier plate comprises glass, quartz, sapphire, or ceramic.

7. The method of claim 1, wherein the thickness of the protrusion of the first curved mold is between 0.1 millimeters and 0.4 millimeters and the thickness of the protrusion of the second curved mold is between 0.3 millimeters and 0.8 millimeters.

8. A composite layer circuit component, comprising:

a first dielectric layer;

a first circuit layer disposed on the first dielectric layer; and

a second dielectric layer is disposed on the first circuit layer,

wherein the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

9. A composite layer circuit element as claimed in claim 8, wherein the coefficients of thermal expansion of the first and second dielectric layers are between 3ppm/° c and 80ppm/° c.

10. The composite layer circuit element of claim 8, wherein the ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer is between 1.5 and 10.

Images