CN115691621A - Method for reducing programming interference of memory bit line and memory thereof - Google Patents
Method for reducing programming interference of memory bit line and memory thereof Download PDFInfo
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- CN115691621A CN115691621A CN202211378551.2A CN202211378551A CN115691621A CN 115691621 A CN115691621 A CN 115691621A CN 202211378551 A CN202211378551 A CN 202211378551A CN 115691621 A CN115691621 A CN 115691621A
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Abstract
The invention discloses a method for reducing programming interference of a memory bit line and a memory thereof, wherein the method comprises the following steps: the memory comprises a plurality of memory arrays, a plurality of memory arrays and a plurality of bit lines, wherein the memory arrays comprise a plurality of identical memory cells and a plurality of bit lines, one bit line is connected with the memory cells in the same column, different bit lines correspond to the memory cells in different columns, and adjacent bit lines are wired by adopting metal wires in different layers; and a grounding metal wire parallel to the two bit lines is arranged between the two bit lines of at least one layer of metal wire routing in the same layer. The advantages are that: according to the method, the grounding metal wire parallel to the two bit lines is arranged between the two bit lines of at least one layer of metal wire routing at the same layer, so that mutual interference between the bit lines during programming is reduced, and the programming interference effect caused by bit line coupling is effectively inhibited under the condition that the chip area overhead is not increased.
Description
Technical Field
The invention relates to the field of electronic technology, in particular to a memory array capable of reducing bit line programming interference.
Background
Adjacent bit) will interfere with each other during programming operation as the characteristic size of the memory cell of the EEPROM/flash memory is reduced. Taking EEPROM programming operation as an example, when a byte (byte) is programmed, the bit line (bitline) corresponding to the byte to be programmed is set to a high voltage of more than 12V; while the bit lines corresponding to the bytes that do not need to be programmed are floating. The bit lines, which are in a floating state, are coupled to a higher voltage due to the presence of coupling capacitance between the bit lines. When this voltage reaches around 8V, the memory cell (bitcell) that should not be written to will be "wrongly" written due to tunneling effect, which is known as program disturb (programming disturb) phenomenon.
In order to solve the above problems, a bit line clamp circuit is usually added to improve the problem, and the specific principle is that when a memory cell is in a non-programmed state, the corresponding bit line is not suspended, but connected to a specially designed clamp level (near VCC), so that the coupling effect of adjacent bit lines can be effectively avoided. However, this solution has the disadvantage of requiring a special clamp circuit in the bit line driving circuit, which increases the area of the bit line driving module, resulting in a significant increase in chip cost. Therefore, there is a need for an improved method for programming a bit line to reduce the interference between adjacent bit lines.
It should be understood that the foregoing merely provides background information related to the present invention and does not necessarily constitute prior art.
Disclosure of Invention
The invention aims to provide a method for reducing programming interference of a memory bit line and a memory thereof, wherein adjacent bit lines in a memory array are wired by adopting metal lines of different layers; a grounding metal wire parallel to the two bit lines is arranged between the two bit lines of at least one layer of metal wire routing in the same layer so as to reduce the mutual interference between the bit lines during programming. The method effectively inhibits the program interference effect caused by bit line coupling under the condition of not increasing the chip area overhead; the method can be applied to array design of NVM (non volatile memory) memories of EEPROM (electrically erasable programmable read-Only memory), flash and other similar operations, and can reduce interference between adjacent bit lines during programming.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a method of reducing memory bit line program disturb, comprising:
the memory comprises a plurality of memory arrays which comprise a plurality of same memory cells and a plurality of bit lines, wherein one bit line is connected with the memory cells in the same column, different bit lines correspond to the memory cells in different columns, and adjacent bit lines are wired by adopting metal wires in different layers;
and a grounding metal wire parallel to the two bit lines is arranged between the two bit lines of at least one layer of metal wire routing in the same layer.
Optionally, the grounding metal line is disposed between two bit lines of the upper layer metal line routing.
Optionally, the memory comprises an EEPROM memory array or a FLASH memory array.
Optionally, a memory, comprising:
a plurality of storage arrays, the storage arrays comprising:
a plurality of identical memory cells;
the memory comprises a plurality of bit lines, wherein one bit line is connected with the memory cells in the same column, different bit lines correspond to the memory cells in different columns, adjacent bit lines are wired by metal lines in different layers, and a grounding metal line parallel to the two bit lines is arranged between at least two bit lines of at least one layer of metal line wiring.
Optionally, each adjacent bit line in the memory array adopts a first layer of metal line routing and a second layer of metal line routing, the second layer of metal line is an upper layer of routing, and a grounding metal line parallel to at least two bit lines is arranged between at least two bit lines of the second layer of metal line routing.
Optionally, in each bit line routed by the second layer of metal lines, one grounding metal line parallel to the two bit lines is arranged between the bit lines.
Optionally, the memory array includes a bit line zero, a bit line two and a bit line four routed by the second layer of metal lines, and a bit line one and a bit line three routed by the first layer of metal lines, the bit lines one and three and the bit lines zero, the bit lines two and the bit lines four are arranged in a staggered manner, and adjacent bit lines of the bit line one are the bit line zero and the bit line two.
Optionally, a first grounding metal line parallel to the two bit lines is arranged between the zero bit line and the second bit line, and a second grounding metal line parallel to the two bit lines is arranged between the second bit line and the fourth bit line.
Optionally, the coupling voltage V of the first bit line during programming BL1 Comprises the following steps:
wherein, C c1 Is the capacitance between the zero bit line and the one bit line, C c2 Is the capacitance between bit line two and bit line one, C gnd Is the ground coupling capacitor, C 'of the bit line number one' gnd Is the capacitance between the first grounding metal line and the first bit line, V pp Is the bit line voltage at the time of programming.
Optionally, the memory comprises an EEPROM memory array or a FLASH memory array.
Compared with the prior art, the invention has the following advantages:
in the method for reducing the programming interference of the memory bit line and the memory thereof, the adjacent bit lines in the memory array are wired by adopting metal lines at different layers; a grounding metal wire parallel to at least two bit lines of at least one layer of metal wire routing is arranged between the at least two bit lines of at least one layer of metal wire routing to reduce mutual interference between the bit lines during programming. The method effectively inhibits the program interference effect caused by bit line coupling under the condition of not increasing the chip area overhead.
Furthermore, the method for reducing the programming interference of the memory bit line can be applied to the array design of NVM memories of EEPROM, flash and other similar operations, and can reduce the interference between adjacent bit lines in the memories.
Drawings
FIG. 1 is a schematic cross-sectional view of bit lines in an EEPROM memory array;
FIG. 2 is a cross-sectional view of a bit line in an EEPROM memory array according to the present invention.
Detailed Description
The present invention will now be further described by way of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.
The following description is provided with reference to the accompanying drawings and detailed description for further details of the method for reducing program disturb of bit line in memory according to the present invention. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise scale for the purpose of facilitating and distinctly aiding in the description of the embodiments of the present invention. To make the objects, features and advantages of the present invention comprehensible, reference is made to the accompanying drawings. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the implementation conditions of the present invention, so that the present invention has no technical significance, and any structural modification, ratio relationship change or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention.
In order to further reduce the interference between adjacent bit lines during programming, as shown in fig. 1, different layers of metal lines are used for routing the adjacent bit lines in the layout design, that is, a jumper mode is used for bit line arrangement of the memory array. Specifically, the memory array includes a bit line No. zero BL0, a bit line No. one BL1, a bit line No. two BL2, a bit line No. three BL3, a bit line No. four BL4, a bit line No. five BL5, a bit line No. six BL6, and a bit line No. seven BL7 (each bit line direction is perpendicular to the paper surface), adjacent bit lines are routed by Metal lines of different layers, as shown in fig. 1, bit line zero BL0, bit line two BL2, bit line four BL4, and bit line six BL6 all use a second layer of Metal line Metal2 routing (each Metal line of each bit line is in layer (2), each Metal line of each bit line routing in the layer is called second layer of Metal line Metal2, each Metal line and bit line are perpendicular to the paper surface) (second layer of Metal line Metal2 is not shown in the figure), the first bit line BL1, the third bit line BL3, the fifth bit line BL5, and the seventh bit line BL7 are all routed by using a first layer of Metal line Metal1 (each Metal line of each bit line is located in a layer (1), each Metal line of each bit line of the layer is called a first layer of Metal line Metal1, and each Metal line and each bit line are perpendicular to the paper surface) (the first layer of Metal line Metal1 is not shown in the figure), and each bit line routed by the first layer of Metal line Metal1 and each bit line routed by the second layer of Metal line Metal2 are arranged in a staggered manner, so that the coupling capacitance between adjacent bit lines is reduced, and no additional circuit module or area overhead is brought. For the first bit line BL1, the adjacent bit lines are the zero bit line BL0 and the second bit line BL2, and during programming, when the peripheral zero bit line BL0, the second bit line BL2 and the third bit line BL3 are all in the programming high-voltage state, the voltage coupled to the first bit line BL1 is:
wherein, C c1 Is the capacitance between the bit line No. zero BL0 and the bit line No. one BL1, C c2 Is the capacitance between the bit line No. two BL2 and the bit line No. one BL1, C gnd Is the ground coupling capacitance, V, of bit line one BL1 pp Is the bit line voltage at the time of programming.
However, in practical applications, the above scheme has a certain drawback, and when the size of the memory cell (bitcell) is further reduced and the coupling capacitances of the adjacent bit lines and the next adjacent bit lines are equivalent, the anti-coupling effect of the scheme is greatly reduced, and particularly, the scheme is almost ineffective in a special mode (pattern) in which the adjacent and next adjacent bytes of the non-programmed bit (bit) are simultaneously in a programmed state.
Further, the present invention further provides a method for reducing program disturb of a memory bit line, the method comprising: the memory comprises a plurality of memory arrays, a plurality of memory arrays and a plurality of bit lines, wherein the memory arrays comprise a plurality of identical memory cells and a plurality of bit lines, one bit line is connected with the memory cells in the same column, different bit lines correspond to the memory cells in different columns, and adjacent bit lines are wired by adopting metal wires in different layers; and a grounding metal wire parallel to the two bit lines is arranged between the at least two bit lines of the routing of the metal wires in the same layer, and the grounding metal wire is not contacted with other metal wires and is not contacted with the bit lines. The method optimizes the wiring design of the bit line, is simple to operate, has lower cost and higher reliability of the corresponding memory, and can effectively inhibit the interference effect caused by bit line coupling during programming without increasing the chip area overhead.
Further, in this embodiment, the grounding metal line is disposed between two bit lines of the upper layer metal line trace, so as to reduce mutual interference between the bit lines. It is understood that, in other embodiments, the grounding metal line is disposed between two bit lines of the lower metal line routing, and the present invention is not limited thereto.
It should be noted that the above method of the present invention is not limited to be applied to a memory including an EEPROM memory array, but may also be applied to an array including a FLASH memory array and other NVM memories of similar operations.
Further, the above improvement method is described by taking an EEPROM memory array as an example, in this embodiment, the EEPROM memory includes a plurality of memory arrays, where each memory array includes a plurality of identical memory cells and a plurality of bit lines, one bit line connects memory cells in a same column, and different bit lines correspond to memory cells in different columns, where adjacent bit lines are routed by metal lines in different layers, and a grounding metal line parallel to the two bit lines is disposed between at least two bit lines of at least one layer of metal line routing. The structure complexity of the memory is far lower than that of a memory additionally provided with a bit line clamping circuit, the cost is lower without increasing the chip area overhead, and the mode effectively inhibits the program interference effect caused by bit line coupling. It should be noted that the memory array is not limited to include the above memory cells and bit lines, but also includes a row selection circuit, a column decoding circuit, and a column selection circuit, etc. the present invention is not limited to and described in detail herein, and the principles of storing and reading bytes in the memory are similar to or the same as those of the conventional memory (for example, the memory in CN 112466370A), and the present invention is not limited to and described in detail herein.
Further, a description will be given by taking a part of the memory array as an example, where adjacent bit lines in the memory array adopt a first layer Metal line Metal1 routing and a second layer Metal line Metal2 routing (in fig. 2, the layer (1) is a bit line and a Metal line thereof routed by the first layer Metal line Metal1, and the layer (2) is a bit line and a Metal line thereof routed by the second layer Metal line Metal 2), the bit lines routed by the first layer Metal line Metal1 and the bit lines routed by the second layer Metal line Metal2 are arranged in a staggered manner, the second layer Metal line Metal2 is an upper layer routing, and a grounding Metal line parallel to the two bit lines is arranged between at least two bit lines routed by the second layer Metal line Metal 2. It can be understood that the larger the number of grounding metal lines arranged between each bit line of the layer of metal line routing, the smaller the interference between adjacent bit lines of each bit line contacted by the layer of metal line is, and of course, the invention does not limit the number of grounding metal lines arranged. As shown in fig. 2, in the present embodiment, in each bit line routed by the second-layer Metal line Metal2, a grounding Metal line parallel to the two bit lines is disposed between every two bit lines.
Specifically, as shown in fig. 2, the bit line No. zero BL0, the bit line No. two BL2, the bit line No. four BL4, and the bit line No. six BL6 of the memory array are routed by using the Metal line Metal2 of the second layer (all belong to the layer (2)), the bit line No. one BL1, the bit line No. three BL3, the bit line No. five BL5, and the bit line No. seven BL7 are routed by using the Metal line Metal1 of the first layer (all belong to the layer (1)), directions of each bit line and the Metal line thereof are perpendicular to the paper surface, and each bit line routed by the Metal line Metal1 of the first layer and each bit line routed by the Metal line Metal2 of the second layer are arranged in a staggered manner.
As shown in fig. 2, in the present embodiment, a grounding Metal line parallel to the two bit lines is disposed between the bit lines routed by the second-layer Metal line Metal 2. Specifically, a first grounding metal wire M2D1 parallel to the two bit lines is arranged between the zero bit line BL0 and the second bit line BL2, a second grounding metal wire M2D2 parallel to the two bit lines is arranged between the second bit line BL2 and the fourth bit line BL4, and a third grounding metal wire M2D3 parallel to the two bit lines is arranged between the fourth bit line BL4 and the sixth bit line BL 6. Of course, the metal line levels in the memory array are not limited to the above, and the number of bit lines routed by each metal line level is not limited to the above, and the embodiment only exemplifies some bit lines for convenience of description.
For bit line one, BL1, its adjacent bit lines are bit line zero, BL0, and bit line two, BL2. During programming, when the peripheral bit line zero BL0, bit line two BL2 and bit line three BL3 are all in the programming high-voltage state, the voltage V coupled to the bit line one BL1 BL1 Comprises the following steps:
wherein, C c1 Is the capacitance between the bit line No. zero BL0 and the bit line No. one BL1, C c2 Is the capacitance between the bit line No. two BL2 and the bit line No. one BL1, C gnd Ground coupling capacitance, C 'of bit line No. one BL 1' gnd Is the capacitance, V, between the first grounding metal line M2D1 and the first bit line BL1 pp Is the bit line voltage at the time of programming.
As can be seen from the above, compared to the memory array only arranged in the jumper mode, the voltage to which the bit lines are coupled during programming is smaller, and the interference between the adjacent bit lines is smaller. In practical application, taking the smic0.13um EEPROM process as an example, TCAD simulation shows that the coupling voltage is reduced by 45% by adding a grounding metal wire (shielding wire).
It is understood that the grounding Metal lines are not limited to be disposed between the bit lines routed by the second-level Metal line Metal2, but in other embodiments, the grounding Metal lines can also be disposed between the bit lines routed by the first-level Metal line Metal1, and the present invention does not limit the Metal line hierarchy. When the grounding Metal wire is arranged between the bit lines wired by the first layer Metal wire Metal1, the grounding Metal wire is not arranged between the bit lines wired by the upper layer Metal wire adjacent to the grounding Metal wire, namely the second layer Metal wire Metal 2.
It should be noted that the memory array of the present invention is not limited to include the two layers of metal line traces and the bit lines, and a part of the structures is exemplified and described here for illustration only, and in practical applications, the number and arrangement of the metal line layers and the bit lines may be set according to actual needs, which is not limited by the present invention. Further, the memory is not limited to include the EEPROM memory array, and in other embodiments, the memory may also be a FLASH memory array or an array of NVM memories operating similarly.
In summary, in the method for reducing the programming interference of the memory bit line and the memory thereof of the present invention, the adjacent bit lines in the memory array use metal line traces of different layers, and a grounding metal line parallel to at least two bit lines is disposed between at least two bit lines of at least one layer of metal line traces of the same layer to reduce the mutual interference between the bit lines during programming. The method effectively inhibits the program interference effect caused by bit line coupling under the condition of not increasing the chip area overhead.
Furthermore, the method for reducing the programming interference of the memory bit line can be applied to the array design of NVM memories of EEPROM, flash and other similar operations, and can reduce the interference between adjacent bit lines in the memories.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (10)
1. A method for reducing memory bit line program disturb, comprising:
the memory comprises a plurality of memory arrays, a plurality of memory arrays and a plurality of bit lines, wherein the memory arrays comprise a plurality of identical memory cells and a plurality of bit lines, one bit line is connected with the memory cells in the same column, different bit lines correspond to the memory cells in different columns, and adjacent bit lines are wired by adopting metal wires in different layers;
and a grounding metal wire parallel to the two bit lines is arranged between the two bit lines of at least one layer of metal wire routing in the same layer.
2. The method of reducing memory bit line program disturb of claim 1,
the grounding metal wire is arranged between the two bit lines of the upper layer metal wire routing.
3. The method of reducing memory bit line program disturb of claim 1,
the memory comprises an EEPROM memory array or a FLASH memory array.
4. A memory, comprising:
a plurality of storage arrays, the storage arrays comprising:
a plurality of identical memory cells;
the memory cell structure comprises a plurality of bit lines, wherein one bit line is connected with the memory cells in the same column, different bit lines correspond to the memory cells in different columns, adjacent bit lines are wired by metal lines in different layers, and a grounding metal line parallel to the two bit lines is arranged between at least two bit lines of at least one layer of metal line wiring.
5. The memory of claim 4,
each adjacent bit line in the memory array adopts a first layer of metal wire routing and a second layer of metal wire routing, the second layer of metal wire is an upper layer of routing, and a grounding metal wire parallel to at least two bit lines is arranged between at least two bit lines of the second layer of metal wire routing.
6. The memory of claim 5,
and in each bit line wired by the second layer of metal lines, a grounding metal line parallel to the two bit lines is arranged between the bit lines.
7. The memory of claim 5,
the memory array comprises a zero bit line, a second bit line and a fourth bit line which are wired by the second layer of metal wires, and a first bit line and a third bit line which are wired by the first layer of metal wires, wherein the first bit line and the third bit line are arranged with the zero bit line, the second bit line and the fourth bit line in a staggered mode, and adjacent bit lines of the first bit line are the zero bit line and the second bit line.
8. The memory of claim 7,
a first grounding metal wire parallel to the two bit lines is arranged between the zero bit line and the second bit line, and a second grounding metal wire parallel to the two bit lines is arranged between the second bit line and the fourth bit line.
9. The memory of claim 8,
coupling voltage V of the first bit line during programming BL1 Comprises the following steps:
wherein, C c1 Is the capacitance between the zero bit line and the one bit line, C c2 Is the capacitance between bit line two and bit line one, C gnd Ground coupling capacitance, C 'of bit line number one' gnd Is the capacitance between the first grounding metal line and the first bit line, V pp Is the bit line voltage at the time of programming.
10. The memory of claim 4,
the memory comprises an EEPROM memory array or a FLASH memory array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211378551.2A CN115691621A (en) | 2022-11-04 | 2022-11-04 | Method for reducing programming interference of memory bit line and memory thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211378551.2A CN115691621A (en) | 2022-11-04 | 2022-11-04 | Method for reducing programming interference of memory bit line and memory thereof |
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| CN115691621A true CN115691621A (en) | 2023-02-03 |
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| CN202211378551.2A Pending CN115691621A (en) | 2022-11-04 | 2022-11-04 | Method for reducing programming interference of memory bit line and memory thereof |
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