CN115691614A - TCAM (ternary content addressable memory), bit cell thereof and write operation method - Google Patents

Abstract

The technical scheme of the application provides a TCAM and a bit cell and a write operation method thereof, wherein the TCAM bit cell comprises: the information storage unit is used for storing information and comprises a first storage unit and a second storage unit; a multi-bit write unit connected to the first and second memory cells, the multi-bit write unit configured to write to the first and second memory cells simultaneously. According to the technical scheme, the TCAM, the bit cell and the write operation method thereof can greatly shorten the write-in time.

Description

TCAM (ternary content addressable memory), bit cell thereof and write operation method

Technical Field

The application relates to the field of semiconductor devices and integrated circuits, in particular to a TCAM, a bit cell of the TCAM and a write operation method of the TCAM.

Background

Ternary Content Addressable Memory (TCAM) is an associative Memory implemented on the basis of conventional Memory technology, and has three Memory states: the ' 0 ', ' 1 ' and ' don't care ' enable the method to carry out exact matching search and fuzzy matching search.

There are three basic operations of TCAMs: the method comprises the following steps of write operation, read operation and search operation, wherein the write operation and the read operation are the same as those of a Random Access Memory (RAM), the search operation is the most main purpose of the TCAM, fast search can be carried out from a huge database, the best matching address is returned, and the fastest search speed can reach more than one hundred million times per second.

The bit cell (bitcell) of the TCAM generally includes two basic memory cells, and thus two write cycles are required to complete the information input to one memory cell, which takes a long time.

Disclosure of Invention

The technical problem to be solved by the application is to provide a TCAM, a bit cell thereof and a write operation method, which can greatly shorten the write-in time.

To solve the above technical problem, the present application provides a TCAM bit cell, including: the information storage unit is used for storing information and comprises a first storage unit and a second storage unit; a multi-bit write unit connected to the first and second memory cells, the multi-bit write unit configured to write to the first and second memory cells simultaneously.

In the embodiment of the application, the first memory cell is connected with a first word line, the second memory cell is connected with a second word line, and the multi-bit writing unit is connected with a third word line.

In this embodiment, when different data is written into the first memory cell and the second memory cell at the same time, the first word line or the second word line is turned on, and the third word line is turned on; and when the same data is written into the first storage unit and the second storage unit at the same time, opening the first word line and the second word line, and closing the third word line.

In an embodiment of the present application, the multi-bit write unit includes: a source end of the fifth MOS tube is connected with the first storage unit, and a drain end of the fifth MOS tube is connected with the second storage unit; and the sixth MOS tube is connected with the fifth MOS tube through a gate end, the source end of the sixth MOS tube is connected with the second storage unit, and the drain end of the sixth MOS tube is connected with the first storage unit.

In the embodiment of the application, the gate ends of the fifth MOS transistor and the sixth MOS transistor are connected to the third word line.

In the embodiment of the present application, the first storage unit and the second storage unit are respectively connected to a first bit line and a second bit line, wherein the first storage unit includes a first MOS transistor, a first inversion unit and a second MOS transistor that are connected in sequence, and the second storage unit includes a third MOS transistor, a second inversion unit and a fourth MOS transistor that are connected in sequence.

In this embodiment of the present application, a drain terminal of the first MOS transistor is connected to the first bit line, a source terminal of the first MOS transistor is connected to the first inverting unit, and a gate terminal of the first MOS transistor is connected to the first word line; the drain end of the second MOS tube is connected with the first inverting unit, the source end of the second MOS tube is connected with the second bit line, and the gate end of the second MOS tube is connected with the first word line.

In this embodiment of the present application, a drain terminal of the third MOS transistor is connected to the first bit line, a source terminal of the third MOS transistor is connected to the second inverting unit, and a gate terminal of the third MOS transistor is connected to the second word line; the drain end of the fourth MOS tube is connected with the second inverting unit, the source end of the fourth MOS tube is connected with the second bit line, and the gate end of the fourth MOS tube is connected with the second word line.

In this embodiment of the present application, a source terminal of the fifth MOS transistor is connected to the output terminal of the first inverting unit, and a drain terminal of the fifth MOS transistor is connected to the input terminal of the second inverting unit; the source end of the sixth MOS tube is connected with the output end of the second inverting unit, and the drain end of the sixth MOS tube is connected with the input end of the first inverting unit.

In the embodiment of the application, the first inverting unit comprises a first inverter and a second inverter which are connected end to end; the second inversion unit comprises a third inverter and a fourth inverter which are connected end to end.

In this embodiment of the present application, the first storage unit is a data storage unit, and the second storage unit is a mask storage unit.

In an embodiment of the present application, the TCAM bit cell further includes: and the matching comparison unit is connected with the information storage unit and used for comparing the input information with the stored information and outputting a comparison result.

In this application embodiment, the matching comparison unit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a tenth MOS transistor that are connected in sequence, where: the grid end of the seventh MOS tube is connected with the first inverting unit, and the source end of the seventh MOS tube is connected with a comparison result output line; the source end of the eighth MOS transistor is connected to the drain end of the seventh MOS transistor, and the gate end of the eighth MOS transistor is used for receiving the input information; the drain end of the ninth MOS tube is connected with the drain end of the eighth MOS tube, and the gate end of the ninth MOS tube is used for receiving the input information; the drain end of the tenth MOS tube is connected with the source end of the ninth MOS tube, the source end of the tenth MOS tube is connected with the comparison result output line, and the gate end of the tenth MOS tube is connected with the second inverting unit.

The application also provides a write operation method, which adopts the TCAM bit cell, and the write operation method comprises the following steps: data is written into the first memory cell and the second memory cell simultaneously using a multi-bit write unit.

In the embodiment of the present application, when the write status is 0,0 is written in the first memory cell, and 1 is written in the second memory cell; when the write state is 1, writing 1 in the first memory cell and writing 0 in the second memory cell; when the writing state is X, writing 0 in the first storage unit, and writing 0 in the second storage unit; and when the writing state is the invalid state, writing 1 in the first storage unit and writing 1 in the second storage unit.

The present application further provides a TCAM, comprising: the TCAM bit cell described above.

According to the technical scheme, the multi-bit writing unit is designed in the logic circuit structure of the TCAM bitcell, the multi-bit writing unit is connected with each storage unit and can write each storage unit simultaneously through logic control of a peripheral circuit, so that one-time writing of the TCAM bitcell is realized, and the writing speed is greatly improved.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of a logic circuit of a TCAM bitcell;

fig. 2 is a schematic diagram of a logic circuit of a TCAM bitcell according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a current direction of a TCAM bitcell according to an embodiment of the present invention when writing into a state 0;

fig. 4 is a schematic view illustrating a current direction of a TCAM bitcell according to an embodiment of the present application when writing to a state 1;

FIG. 5 is a schematic diagram of a current direction of a TCAM bitcell according to an embodiment of the present invention when writing into a state X;

fig. 6 is a schematic structural diagram of a matching comparison unit in a TCAM bitcell according to an embodiment of the present application.

Detailed Description

The following description is presented to enable one of ordinary skill in the art to make and use the present disclosure. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

Referring to fig. 1, a TCAM bitcell includes a first storage unit 10, a second storage unit 11, and a matching comparison unit 13. When a write operation is performed, data D is written in the first memory cell 10, and data M is written in the second memory cell 11. < D, M > constitutes a data representing a memory state of "0" when < D, M > is <0,1 >; when < D, M > is <1,0>, this represents a memory state of "1"; when < D, M > is <0,0>, this represents a memory state of "X"; when < D, M > is <1,1>, this means that the memory state is meaningless.

When writing data < D, M >, it is necessary to perform a write operation on the first memory cell 10 and the second memory cell 11, respectively, and thus two write cycles are required to complete information input to one tcambit cell.

In order to shorten the writing time, the technical scheme of the application improves the circuit structure of the TCAM bitcell, and adds the multi-bit writing unit which is configured to write each storage unit in the information storage unit at the same time, so that the writing speed can be greatly improved.

The TCAM bitcell according to the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

Referring to fig. 2, a TCAM bitcell 100 according to an embodiment of the present application includes: an information storage unit, a multi-bit write unit 120, and a match compare unit 130. The information storage unit is used for storing information, and includes a first storage unit 111 and a second storage unit 112, where the first storage unit 111 may be a data storage unit, and the data storage unit may be, for example, a static random access memory (SRAM cell), and data D is written in the first storage unit 111 during a write operation. The second storage unit 112 may be a mask storage unit, which may be, for example, an SRAM cell, and data M is written in the second storage unit 112 during a write operation. The data stored in the first memory cell 111 and the second memory cell 112 form a two-bit state < D, M >, <0,1> is state 0, <1,0> is state 1, <0,0> is state X, <1,1> is invalid.

The first memory cell 111 is connected to a first word line WL1, a first bit line BL1, and a second bit line BL2. Specifically, the first storage unit 111 includes a first MOS transistor M1, a first inverting unit, and a second MOS transistor M2 that are connected in sequence, where a drain of the first MOS transistor M1 is connected to the first bit line BL, a source of the first MOS transistor M1 is connected to the first inverting unit, and a gate of the first MOS transistor M1 is connected to the first word line WL1; the drain end of the second MOS transistor M2 is connected to the first inverting unit, the source end of the second MOS transistor M2 is connected to the second bit line BL2, and the gate end of the second MOS transistor M2 is connected to the first word line WL1.

The first inversion unit comprises a first inverter X1 and a second inverter X2 which are connected end to end. The first inverter X1 and the second inverter X2 may be inverters of any structure as long as the inversion effect can be achieved.

The second memory cell 112 is connected to the first word line WL1, the first bit line BL1, and the second bit line BL2. Specifically, the second storage unit 112 includes a third MOS transistor M3, a second inversion unit, and a fourth MOS transistor M4 that are connected in sequence, where a drain terminal of the third MOS transistor M3 is connected to the first bit line BL1, a source terminal of the third MOS transistor M3 is connected to the second inversion unit, and a gate terminal of the third MOS transistor M3 is connected to the second word line WL2; the drain end of the fourth MOS transistor M4 is connected to the second inverting unit, the source end of the fourth MOS transistor M4 is connected to the second bit line BL2, and the gate end of the fourth MOS transistor M4 is connected to the second word line WL2.

The second inversion unit comprises a third inverter X3 and a fourth inverter X4 which are connected end to end. The structures of the third inverter X3 and the fourth inverter X4 are not particularly limited as long as the inversion effect can be achieved.

The multi-bit writing unit 120 includes a fifth MOS transistor M5 and a sixth MOS transistor M6, wherein a source terminal of the fifth MOS transistor M5 is connected to the first storage unit 111, and a drain terminal of the fifth MOS transistor M5 is connected to the second storage unit 112. In this embodiment of the application, a source end of the fifth MOS transistor M5 is connected to the first inverting unit of the first storage unit 111, and specifically, a source end of the fifth MOS transistor M5 may be connected to an output end of the first inverter X1 and an input end of the second inverter X2. A drain of the fifth MOS transistor M5 is connected to the second inverting unit of the second storage unit 112, for example, a drain of the fifth MOS transistor M5 is connected to an input end of the third inverter X3 and an output end of the fourth inverter X4. A source end of the sixth MOS transistor M6 is connected to the second inverting unit of the second storage unit 112, for example, a source end of the sixth MOS transistor M6 is connected to an output end of the third inverter X3 and an input end of the fourth inverter X4. A drain of the sixth MOS transistor M6 is connected to the first inverting unit of the first storage unit 111, for example, the drain of the sixth MOS transistor M6 is connected to an input end of the first inverter X1 and an output end of the second inverter X2. The gate ends of the fifth MOS transistor and the sixth MOS transistor are connected with each other and connected to the third word line WL3.

By controlling the switching states of the first word line WL1, the second word line WL2 and the third word line WL3 and inputting correct data from the first bit line or the second bit line, writing operation on all memory cells in one writing cycle is realized, and further, writing in different states is realized. Specifically, when different data is written into the first memory cell 111 and the second memory cell 112 at the same time, the first word line WL1 or the second word line WL2 is turned on, and the third word line WL3 is turned on; when the same data is written into the first memory cell 111 and the second memory cell 112 at the same time, the first word line WL1 and the second word line WL2 are turned on, and the third word line WL3 is turned off.

In the embodiment of the present application, the writing operation on the first storage unit 111 and the second storage unit 112 simultaneously in one writing cycle may be implemented by: when writing state 0, that is, < D, M > is <0,1>, the first word line WL1 and the third word line WL3 are simultaneously turned on, the second word line WL2 is turned off, the first word line BL1 is turned low, the second word line BL2 is turned high (the direction of current is shown by an arrow in fig. 3), and writing state 1, that is, < D, M > is <1,0>, the first word line WL1 and the third word line WL3 are simultaneously turned on, the second word line WL2 is turned off, the first word line BL1 is turned high, and the second word line BL2 is turned low (the direction of current is shown by an arrow in fig. 4); when writing state X, that is, < D, M > is <0,0>, the first word line WL1 and the second word line WL2 are turned on simultaneously, the third word line WL3 is turned off, the first bit line BL1 is set low, and the second bit line BL2 is set high (the current direction is as indicated by the arrow in fig. 5); when an invalid state is written, the first word line WL1 and the second word line WL2 are simultaneously turned on, the third word line WL3 is turned off, the first bit line BL1 is set to be high, and the second bit line BL2 is set to be low.

In other embodiments, the following method may be used to simultaneously complete the writing operation on the first storage unit 111 and the second storage unit 112 in one writing cycle: when a state 0 is written, the second word line WL2 and the third word line WL3 are simultaneously turned on, the first word line WL1 is turned off, the first bit line BL1 is set to be high, and the second bit line BL2 is set to be low; when writing in a state 1, the second word line WL2 and the third word line WL3 are simultaneously turned on, the first word line WL1 is turned off, the first bit line BL1 is set low, and the second bit line BL2 is set high; when in a writing state X, the first word line WL1 and the second word line WL2 are simultaneously turned on, the third word line WL3 is turned off, the first bit line BL1 is set to be low, and the second bit line BL2 is set to be high; when an invalid state is written, the first word line WL1 and the second word line WL2 are simultaneously turned on, the third word line WL3 is turned off, the first bit line BL1 is set to be high, and the second bit line BL2 is set to be low.

Therefore, the embodiment of the application can realize the one-time writing of the TCAM bitcell by adding the multi-bit writing unit in the TCAM bitcell and matching with the logic control of the peripheral circuit, thereby reducing half of the writing time.

Referring to fig. 6, the matching comparing unit 130 is configured to compare the input information with the stored information and output a comparison result, and may include a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a tenth MOS transistor M10, which are connected in sequence, where: a gate end of the seventh MOS transistor M7 is connected to the first inverting unit, specifically, a gate end of the seventh MOS transistor M7 is connected to an output end of the first phase inverter X1 and an input end of the second phase inverter, and a source end of the seventh MOS transistor M7 is connected to a comparison result output line HL; the source end of the eighth MOS transistor M8 is connected to the drain end of the seventh MOS transistor M7, and the gate end of the eighth MOS transistor M8 is used for receiving the input information; a drain terminal of the ninth MOS transistor M9 is connected to a drain terminal of the eighth MOS transistor M8, and a gate terminal of the ninth MOS transistor M9 is configured to receive the input information, where the input information includes first input information KEY and second input information KEYB that are opposite to each other, and the first input information KEY and the second input information KEYB are respectively received by the gate terminal of the eighth MOS transistor M8 and the gate terminal of the ninth MOS transistor M9; a drain terminal of the tenth MOS transistor M10 is connected to a source terminal of the ninth MOS transistor M9, a source terminal of the tenth MOS transistor M10 is connected to the comparison result output line HL, a gate terminal of the tenth MOS transistor M10 is connected to the second inverting unit, and specifically, a gate terminal of the tenth MOS transistor M10 is connected to an output terminal of the third phase inverter X3 and an input terminal of the fourth phase inverter X4.

The embodiment of the present application further provides a write operation method, where the TCAM bit cell is adopted, and the write operation method includes: data is written into the first memory cell and the second memory cell simultaneously using a multi-bit write unit. In some embodiments, when the write status is 0, writing 0 in the first memory cell and writing 1 in the second memory cell; when the writing state is 1, writing 1 in the first storage unit and writing 0 in the second storage unit; when the writing state is X, writing 0 in the first storage unit, and writing 0 in the second storage unit; and when the writing state is an invalid state, writing 1 into the first memory cell and writing 1 into the second memory cell.

The embodiment of the application further provides a TCAM, which comprises the TCAM bit cell.

In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, even though not expressly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will also be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (16)

1. A TCAM bit cell, comprising:

the information storage unit is used for storing information and comprises a first storage unit and a second storage unit;

a multi-bit write unit connected to the first and second memory cells, the multi-bit write unit configured to write to the first and second memory cells simultaneously.

2. The TCAM bit cell of claim 1, in which the first memory cell is connected to a first word line, the second memory cell is connected to a second word line, and the multi-bit write cell is connected to a third word line.

3. The TCAM bit cell of claim 2, wherein the first word line or the second word line is turned on and the third word line is turned on when different data is written to the first memory cell and the second memory cell simultaneously; and when the same data is written into the first storage unit and the second storage unit at the same time, opening the first word line and the second word line, and closing the third word line.

4. The TCAM bit cell of claim 3, in which the multi-bit write cell comprises:

a source end of the fifth MOS tube is connected with the first storage unit, and a drain end of the fifth MOS tube is connected with the second storage unit;

and the sixth MOS tube is connected with the fifth MOS tube through a gate end, the source end of the sixth MOS tube is connected with the second storage unit, and the drain end of the sixth MOS tube is connected with the first storage unit.

5. The TCAM bit cell of claim 4, wherein gate terminals of the fifth and sixth MOS transistors are connected to the third word line.

6. The TCAM bit cell of claim 4, wherein the first and second memory cells are each connected to a first and second bit line, respectively, wherein the first memory cell comprises a first MOS transistor, a first inverter cell and a second MOS transistor connected in sequence, and the second memory cell comprises a third MOS transistor, a second inverter cell and a fourth MOS transistor connected in sequence.

7. The TCAM bit cell of claim 6, wherein a drain of the first MOS transistor is coupled to the first bit line, a source of the first MOS transistor is coupled to the first inverting unit, and a gate of the first MOS transistor is coupled to the first word line; the drain end of the second MOS tube is connected with the first inverting unit, the source end of the second MOS tube is connected with the second bit line, and the gate end of the second MOS tube is connected with the first word line.

8. The TCAM bit cell of claim 6, wherein a drain of the third MOS transistor is coupled to the first bit line, a source of the third MOS transistor is coupled to the second inverting unit, and a gate of the third MOS transistor is coupled to the second word line; the drain terminal of the fourth MOS transistor is connected to the second inverting unit, the source terminal of the fourth MOS transistor is connected to the second bit line, and the gate terminal of the fourth MOS transistor is connected to the second word line.

9. The TCAM bit cell of claim 6, wherein a source of the fifth MOS transistor is connected to the output of the first inverting unit, and a drain of the fifth MOS transistor is connected to the input of the second inverting unit; the source end of the sixth MOS tube is connected with the output end of the second inverting unit, and the drain end of the sixth MOS tube is connected with the input end of the first inverting unit.

10. The TCAM bit cell of claim 6, wherein the first inverting unit includes a first inverter and a second inverter connected end-to-end; the second inversion unit comprises a third inverter and a fourth inverter which are connected end to end.

11. The TCAM bit cell of claim 1, wherein the first storage cell is a data storage cell and the second storage cell is a mask storage cell.

12. The TCAM bit cell of claim 6, further comprising: and the matching comparison unit is connected with the information storage unit and used for comparing the input information with the stored information and outputting a comparison result.

13. The TCAM bit cell of claim 12, wherein the matching comparison unit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor connected in sequence, wherein:

the grid end of the seventh MOS tube is connected with the first inverting unit, and the source end of the seventh MOS tube is connected with a comparison result output line;

the source end of the eighth MOS transistor is connected with the drain end of the seventh MOS transistor, and the gate end of the eighth MOS transistor is used for receiving the input information;

the drain end of the ninth MOS tube is connected with the drain end of the eighth MOS tube, and the gate end of the ninth MOS tube is used for receiving the input information;

the drain end of the tenth MOS tube is connected with the source end of the ninth MOS tube, the source end of the tenth MOS tube is connected with the comparison result output line, and the gate end of the tenth MOS tube is connected with the second inverting unit.

14. A method of writing using the TCAM bit cell of any one of claims 1 to 13, the method comprising: data is written into the first memory cell and the second memory cell simultaneously using a multi-bit write unit.

15. The write operation method according to claim 14, wherein when the write status is 0,0 is written in the first memory cell, and 1 is written in the second memory cell; when the writing state is 1, writing 1 in the first storage unit and writing 0 in the second storage unit; when the writing state is X, writing 0 in the first storage unit, and writing 0 in the second storage unit; and when the writing state is the invalid state, writing 1 in the first storage unit and writing 1 in the second storage unit.

16. A TCAM, comprising: the TCAM bit cell of any one of claims 1 to 13.

Images