CN115688655A - FPGA pre-wiring method, system, medium, equipment and terminal - Google Patents

Abstract

The invention belongs to the technical field of computer automation design and discloses an FPGA pre-wiring method, a system, a medium, equipment and a terminal, wherein the FPGA pre-wiring method comprises virtual net construction and virtual net pre-wiring, and virtual connection is constructed on an FPGA and an optimal wiring path is calculated; respectively constructing a group of virtual nets on the FPGA for different types of connecting wires, wherein the abstraction degree of the virtual nets is higher than that of the nets in an actual circuit, and each virtual net is mapped to different areas on the FPGA; an optimal routing scheme is found for the virtual nets, and the congestion cost of routing resource nodes is not considered when the virtual nets are routed. The FPGA pre-wiring method firstly constructs virtual connection on the FPGA and calculates the optimal wiring path, and then the pre-wiring result can be directly utilized in the actual wiring process. Compared with the current mainstream FPGA layout and wiring tool VPR 8.0, the time required by wiring is reduced by 48 percent.

Description

FPGA pre-wiring method, system, medium, equipment and terminal

Technical Field

The invention belongs to the technical Field of computer automation design, mainly relates to the Field of integrated circuit aided design, in particular to wiring of a Field Programmable Gate Array (FPGA), and particularly relates to a virtual net-based FPGA pre-wiring method, system, medium, device and terminal. The method is mainly applied to the design process of the FPGA system in the fields of industry, military, scientific research and the like, and improves the design efficiency of the system.

Background

At present, as a semi-custom circuit, the FPGA has the advantages of flexible use, low cost, rich logic resources, and the like, and is widely applied to the fields of civil electronic equipment, military affairs, and aerospace. When the FPGA system is designed, support of an Electronic Design Automation (EDA) software needs to be used, and the FPGA chip and the EDA software are matched with each other. China started late in the field of FPGA, and is still monopolized by Xilinx and Intel companies in the aspect of FPGA EDA software in the United states.

The FPGA EDA design flow mainly comprises design input, behavior level synthesis, process mapping, packaging, layout and wiring. The wiring is the most complex step and the longest time-consuming step, and directly determines the performance such as time sequence, power consumption and the like after the circuit is realized on the FPGA. On the basis of layout, the FPGA wiring is to configure connection resources inside the FPGA so as to communicate all connections in the circuit, and the circuit performance is optimized under the constraint conditions of mutually exclusive use of wiring resources and the like. The FPGA chip needs to be modeled before routing, and the routing algorithm routes the circuit over the model. The FPGA wiring model is also called as a wiring resource graph G = < V, E >, wherein V is a set of nodes and represents resources such as metal wires, logic block pins and the like; e is a set of edges representing programmable switches between two nodes in V. The wiring resource diagram bridges the FPGA chip and the wiring algorithm, and FPGA wiring actually runs on the abstract wiring resource diagram. Two problems are mainly solved in the wiring process: (1) All nets in the circuit are connected on the premise of ensuring legal use of wiring resources. When the circuit scale is large, there may be competition of wiring resources during wiring, resulting in failure of wiring. Therefore, the routing algorithm needs to reasonably distribute routing resources and route all nets by using limited resources. (2) The performance of the circuit, including critical path delay, power consumption, area, etc., is optimized as much as possible while ensuring that the wiring is legal. Obviously, the wiring problem is a multi-objective optimization problem, and it takes much time to wire when the circuit scale is large.

With the progress of modern semiconductor technology, the integration level of the FPGA is higher and higher, so that the time required by the FPGA for wiring is more and more. For a larger industrial FPGA circuit, the wiring time is even 2 days, and the design efficiency of the FPGA system is seriously reduced.

For the FPGA wiring problem, the current PathFinder algorithm based on congestion negotiation still takes a leading position in the academic world and the industrial world. For an actual FPGA circuit, the algorithm searches for the lowest-cost wiring path for nets in the circuit one by one, and the optimal wiring path is often also the path using the least amount of wiring resources or the least delay. Additionally, the routing resource specifications and distribution patterns within a given FPGA chip are known. Therefore, the invention performs pre-wiring on the given FPGA, and can utilize the pre-wiring result in the following actual wiring process, thereby remarkably shortening the path searching time and further improving the wiring efficiency.

The invention searches the patent literature and published journal articles at home and abroad, and reports or literatures which are closely related and the same as the invention are not found.

Through the above analysis, the problems and defects of the prior art are as follows: when the circuit scale is large, the existing FPGA wiring method has the defect of long time consumption in FPGA wiring application, and the problem of time consumption of FPGA wiring is more and more prominent along with the improvement of FPGA integration level.

Disclosure of Invention

Aiming at the defect that the traditional FPGA wiring algorithm consumes a long time in FPGA wiring application, the invention provides an FPGA pre-wiring method, an FPGA pre-wiring system, a medium, an FPGA pre-wiring device and a terminal, and particularly relates to an FPGA pre-wiring method based on a virtual net.

The invention is different from the traditional FPGA wiring algorithm in that the node-level wiring is carried out on the actual net, but creatively provides the concept of the virtual net, and the virtual net is constructed and wired on the FPGA in advance, so that the calculated amount in the actual wiring process is reduced. The FPGA pre-wiring method comprises virtual net construction and virtual net pre-wiring, firstly, a group of abstract virtual nets are respectively constructed on the FPGA according to the connection mode of various types of connection resources, and each virtual net can be mapped to different areas on the FPGA so as to form different actual nets. And then, pre-wiring the virtual net, and constructing an optimal wiring scheme by using the virtual wiring resources.

Further, the FPGA pre-wiring method comprises the following steps:

calculating various types of connection resources in the FPGA, generally integrating a large number of programmable connections in the FPGA to flexibly realize interconnection among logic modules, extracting different types of connection resource information including connection length, time delay, programmable point distribution conditions and the like from < segment > and < device > modules of an FPGA chip model file, and recording the type number of the FPGA interconnection resource types as types;

and step two, constructing a virtual line network which takes the type of connection as a source point and takes different relative positions on the FPGA as a terminal point for the ith connection resource. Because the connection resources are distributed along the horizontal x axis and the vertical y axis in the FPGA, each connection resource has four trends of "up, down, left, and right", so virtual nets need to be respectively constructed for the four trends of each connection, and each virtual net can be expressed as a two-dimensional coordinate (x, y). Unlike the actual nets in traditional FPGA wiring problems, the constructed virtual nets essentially only describe the source point and shape information of the connections, with no fixed locations on the FPGA. By constructing a virtual net instead of an actual net on the FPGA, the problem of explosion of the number of nets is avoided. The virtual net corresponding to the ith connection type forms a virtual net set H _i For a given FPGA, a virtual net set is finally obtained: c = { H = _i |0≤i＜types}；

Step three, because the abstract virtual nets cannot be directly wired, each virtual net in the set C is mapped to be connected with an actual net on the FPGA, the virtual net and the mapped actual net are required to be consistent in a source point connection type and a target relative position, and the connection line and the target point which form the actual net after mapping are respectively marked as w and t;

step four, in the wiring resource diagramActually wiring the actual net connections, and searching the optimal wiring path from w to t by using an A-x algorithm, wherein each virtual net connection has a plurality of optimal wiring schemes under the normal condition; because the abstraction level of the virtual net is higher than that of the actual net after mapping, all programmable points of the connecting line are sequentially numbered as { p 'according to the rule of' from left to right and from front to back _i L1 is not less than i not more than 2L +1, wherein L represents the length of the connecting line, p _i The ith programmable point representing a wire is then saved as a sequence of wire programmable points { p } for each wire path _i I is more than or equal to 1}, rather than the traditional node index sequence;

step five, for the virtual net set

The corresponding pre-wiring result is noted as P _i ＝{Ω _x,y X is | -W ≦ x ≦ W, -H ≦ y ≦ H }, where Ω _x,y Is P _i A set formed by all optimal wiring paths of a middle virtual wire net (x, y);

further, in the second step, the specific method for constructing the virtual net on each type of connection line on the FPGA is as follows:

(1) And establishing a corresponding two-dimensional coordinate system for each trend of the connecting line. With this coordinate system, each virtual net connection can be accurately represented in two-dimensional coordinates.

(2) For the ith type of connecting line, a virtual line network is constructed for the upper, lower, left and right connecting line trends, specifically, a virtual connection from the type of connecting line to all target positions on the FPGA is constructed, and each target position can be uniquely represented as (x, y) in the constructed two-dimensional coordinate system. The connections in the virtual connections are not specific connections within the FPGA, and each virtual connection may be mapped to an actual connection in a different region on the FPGA.

(3) When virtual nets are constructed for all types of nets, a virtual net set C = { H } is obtained _i I is more than or equal to 0 and less than types, and the virtual net H corresponding to the ith connection type _i The device comprises four parts: h _i ＝{U _i ,D _i ,L _i ,R _i In which U is _i 、D _i 、L _i 、R _i Are respectively asAnd the ith type of connecting line goes up, down, left and right to the corresponding virtual line network set. Wherein

X＝{(x,y)|-W≤x≤W,-H≤y≤H}。

Further, in the fourth step, the specific method for pre-wiring each virtual net "w-t" is as follows:

(1) The optimal path cost is marked as cost, and the cost is initially set as-1; the Path cost Path (w) for w is calculated and added to the small top heap (denoted as Q). Path (w) is defined as:

Path(w)＝c(w)+α×est _wt ；

where c (w) represents the cost of node w, est _wt Representing the path estimation cost from node w to t, and the parameter a is used to balance the effect of the path estimation cost in the total path cost. c (w) is defined as:

c(w)＝d _w +b _w ；

wherein d is _w And d _w Respectively, the delay and the basic use cost of the slave node w.

(2) Removing cost minimum node v from Q _min (ii) a If v is _min If the target leakage end point t is the target leakage end point t, the step (4) is carried out.

(3) For v _min The Path cost Back (n) from the net source end s to n and the Path cost Path (n) from s to t are calculated, and the step (2) is executed. Back (n) and Path (n) are as follows:

Back(n)＝Back(v _min )+c(n)；

Path(n)＝Back(n)+α×est _nt ；

wherein est _nt Representing the path estimation cost from node n to t, the parameter α is used to balance the impact of the path estimation cost in the total path cost, and c (n) represents the cost of use for node n.

(4) And establishing and saving a path from the t to a net source terminal s. If the cost is equal to-1 or the cost of the node with the minimum cost in the Q is equal to the cost of the current path, setting the cost as the cost of the current path, and continuing to execute the step (2); otherwise, the pre-wiring is finished.

Another object of the present invention is to provide an FPGA pre-wiring system using the FPGA pre-wiring method, the FPGA pre-wiring system including:

the connection resource counting module is used for counting the number of the internal connection types of the FPGA;

the virtual net building module is used for building a virtual net for each type of connection resource;

and the virtual net wiring module is used for wiring the virtual net.

Another object of the invention is to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of the FPGA pre-wiring method.

It is a further object of the present invention to provide a computer readable storage medium, storing a computer program which, when executed by a processor, causes the processor to perform the steps of the FPGA pre-wiring method.

The invention also aims to provide an information data processing terminal, which is used for realizing the FPGA pre-wiring system.

By combining the technical scheme and the technical problem to be solved, the technical scheme to be protected by the invention has the advantages and positive effects that:

first, aiming at the technical problems existing in the prior art and the difficulty in solving the problems, the technical problems to be solved by the technical scheme of the present invention are closely combined with the technical scheme to be protected and the results and data in the research and development process, and some creative technical effects brought after the problems are solved are analyzed in detail and deeply. The specific description is as follows:

the invention provides an FPGA pre-wiring method based on a virtual net, which is used for constructing the virtual net on an FPGA in advance and calculating an optimal wiring path, so that the path search time in the actual wiring process can be reduced. Before actual wiring, a large number of virtual net connections are constructed on the FPGA, and each virtual net can be mapped into an actual net in different areas of the FPGA. By adopting the virtual net, the invention can obviously reduce the number of the wire net connections in the pre-wiring process and improve the query efficiency of the pre-wiring result in the actual wiring process. Next, the invention wires all virtual nets and saves the wiring result, only considering the time delay and the basic use cost of the wiring resource in the wiring process; a virtual wire network often has a plurality of optimal wiring paths, search time can be shortened by utilizing a pre-wiring result in an actual wiring process, and the method is mainly applied to design and development of an auxiliary FPGA in the fields of civil use, military, aerospace and the like.

Firstly, respectively constructing a group of virtual nets for different types of connecting wires on the FPGA, wherein the abstraction degree of the virtual nets is higher than that of the nets in an actual circuit, and each virtual net can be mapped to different areas on the FPGA; an optimal routing plan is then found for the virtual nets, without regard to the congestion cost of routing resource nodes when routing the virtual nets. According to simulation experiments and data results, compared with the current mainstream VPR 8.0 wiring method, the virtual net-based pre-wiring method provided by the invention has the advantage that the wiring time is reduced by 48% under the condition of keeping delay and wire length. Wherein the time delay is basically kept unchanged, and the line length is optimized by 1.4 percent. When the circuit is larger, the acceleration effect of the invention on FPGA wiring is better. According to the invention, by utilizing the priori information of the internal wiring resources of the FPGA and wiring on the FPGA in advance, the optimal wiring scheme in different connection modes is found out, so that a large amount of time is not required to be consumed in the actual wiring process, the actual wiring time consumption is reduced, the practical value is very high, and the method is particularly beneficial to promoting the research and development of domestic FPGA EDA software.

Compared with the traditional FPGA wiring algorithm, the invention also has the following beneficial technical effects:

(1) According to the FPGA pre-wiring method provided by the invention, the optimal wiring scheme of each connection mode in the FPGA is calculated in advance, so that the calculation amount in the actual wiring process can be reduced, and the wiring speed is obviously accelerated.

(2) The virtual net construction only concerns the shape of the net connection, and does not need to construct corresponding nets for all connection modes on the FPGA, so that the problem of explosion of the net connection number is avoided.

(3) The invention aims at the constructed virtual net for wiring, and has the characteristic of high abstraction degree, thereby greatly reducing the calculation amount in the pre-wiring stage and the scale of the pre-wiring result.

(4) The wiring is carried out on the FPGA in advance before the actual wiring, and the pre-wiring result can be directly used in the actual wiring process, so that the path search in the actual wiring process is reduced, and the wiring efficiency is improved.

(5) The invention better solves the problems of long CPU consumption time and low efficiency in the existing FPGA wiring process.

Secondly, considering the technical scheme as a whole or from the perspective of products, the technical effect and advantages of the technical scheme to be protected by the invention are specifically described as follows:

the FPGA pre-wiring method provided by the invention firstly constructs virtual connection on the FPGA and calculates the optimal wiring path, and then the pre-wiring result can be directly utilized in the actual wiring process, thereby reducing the path searching time in the actual wiring. The invention obviously reduces the wiring time on the premise of not reducing the quality of the wiring result, and compared with the current mainstream FPGA layout wiring tool VPR 8.0, the time required by wiring is reduced by 48 percent.

Third, as an inventive supplementary proof of the claims of the present invention, there are also presented several important aspects:

(1) The expected income and commercial value after the technical scheme of the invention is converted are as follows:

the FPGA pre-wiring method provided by the invention innovatively adopts a pre-wiring technology, so that the wiring efficiency is obviously improved. Although some FPGA manufacturers in China develop their own FPGA CAD software, such as Fuxi software of Jing Weiqi and HqFpga of Xian Zhi polycrystal company, the FPGA manufacturers have the disadvantages of low efficiency, poor stability and the like, and are only applied to respective products in a small range at present. Most FPGA vendors in the country still rely on Xilinx and Intel corporation's FPGAEDA software. The FPGA pre-wiring method can be used as a submodule to be applied to the research and development of the domestic FPGAEDA software, so that the performance of the domestic FPGAEDA software is improved.

(2) The technical scheme of the invention fills the technical blank in the industry at home and abroad:

in the field of FPGA wiring, researchers at home and abroad adopt a large number of optimization strategies to improve wiring speed, so that the optimization space of an FPGA algorithm is smaller and falls into a bottleneck gradually. The invention firstly proposes the idea of pre-wiring, improves the wiring speed from the perspective of reducing the actual wiring task amount, and provides a new optimization direction for the FPGA wiring so as to break through the bottleneck of the existing FPGA wiring optimization.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of an FPGA pre-wiring method provided by an embodiment of the invention;

fig. 2 is a schematic diagram of an FPGA pre-wiring method provided in an embodiment of the present invention, which generally includes three parts: inquiring and counting the types of internal connecting lines of the FPGA; constructing a virtual wire network on the FPGA according to the counted connection type; finally, wiring the constructed virtual net;

fig. 3 is a diagram of setting four directions and coordinate origins of a connection line provided in the embodiment of the present invention, and for a connection line with any direction, a two-dimensional coordinate system is constructed with the "front left" position of the connection line as the origin;

fig. 4 is a diagram illustrating virtual net representations in a coordinate system, where each virtual net can be accurately represented by two-dimensional coordinates in the coordinate system.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In view of the problems in the prior art, the present invention provides a method, a system, a medium, a device and a terminal for FPGA pre-wiring, and the present invention is described in detail with reference to the accompanying drawings.

1. Illustrative embodiments are explained. This section is an explanatory embodiment expanding on the claims so as to fully understand how the present invention is embodied by those skilled in the art.

Example 1

The invention relates to an FPGA pre-wiring method based on a virtual net, which is characterized in that the virtual net is constructed on a given FPGA, the optimal wiring scheme of different connections on the FPGA is calculated by pre-wiring the virtual net, and the actual wiring application reduces the calculation amount by inquiring the pre-wiring result. The used FPGA is an island FPGA structure which is mainstream in the current market, and different types of connection resources are integrated inside the FPGA structure. The constructed virtual nets are all simple nets with single connection, and no fixed position is arranged on the FPGA. The virtual net pre-wiring result uses the wiring resources contained in the FPGA to connect each virtual net, and only the wiring delay and the basic use cost are considered during pre-wiring.

As shown in fig. 1, the FPGA pre-wiring method provided in the embodiment of the present invention includes the following steps:

s101, counting the number of types of internal connecting lines of the FPGA and calculating the number of types as types;

s102, constructing a virtual wire network for each type of wire connection resource;

s103, wiring the virtual net.

As a preferred embodiment, as shown in fig. 2, the FPGA pre-wiring method provided in the embodiment of the present invention includes virtual net building and virtual net pre-wiring, and specifically includes the following steps:

step 1, counting the types of the internal connection resources of the FPGA, and recording the number of the connection types as types. Each type of connection resource has differences in connection length, delay, etc.

Step 2, respectively constructing corresponding virtual nets for each type of connecting resources, and finally obtaining a virtual net set: c = { H = _i I is more than or equal to |0 and less than types }, wherein H _i And representing the virtual net set corresponding to the ith connection type. Because the connecting line resources are distributed in a horizontal or vertical channel in the FPGA, each type of connecting line resources correspond to four trends, namely an upper trend, a lower trend, a left trend and a right trend. Respectively constructing a virtual net aiming at four trends of each connection, and specifically comprising the following steps:

(1) And establishing a corresponding two-dimensional coordinate system for each direction of the connecting line, so as to describe the connection of the created virtual line network.

(2) For the ith type of connecting line, a virtual line network is constructed for the upper, lower, left and right connecting line trends, specifically, a virtual connection from the type of connecting line to all target positions on the FPGA is constructed, and each target position can be uniquely represented as (x, y) in the constructed two-dimensional coordinate system. And finally, the virtual net of the ith type of connecting line is composed of four parts, namely: h _i ＝{U _i ,D _i ,L _i ,R _i In which U is _i 、D _i 、L _i 、R _i And the virtual net sets are respectively corresponding to the upper, lower, left and right trends of the ith type of connecting line.

The virtual net construction only concerns the shape of the net connection, and does not need to construct corresponding nets for all connection modes on the FPGA, so that the problem of explosion of the net connection number is avoided.

The wire mesh pre-wiring method provided by the invention is used for wiring the constructed virtual wire mesh, and the congestion cost of wiring resource nodes is not considered in the wiring process. For a net connection, the corresponding optimal routing schemes are typically not unique, and each routing scheme corresponds to a routing path. The pre-wiring of nets comprises the following steps:

step 1, for a virtual net, mapping the corresponding connection type and target position to the actual wiring resource nodes w and t on the wiring resource diagram.

And step 2, finding the optimal wiring path from w to t on the wiring resource diagram. The method specifically comprises the following steps:

(1) The cost Path (w) of w is calculated and added to the small top heap Q. Path (w) is defined as:

Path(w)＝c(w)+α×est _wt

where c (w) represents the cost of node w, est _wt Representing the path estimation cost from node w to t, and the parameter a is used to balance the effect of the path estimation cost in the total path cost. c (w) is defined as:

c(w)＝d _w +b _w

wherein d is _w And d _w Respectively, the delay and the basic use cost of the slave node w.

(2) Removing cost minimum node v from Q _min . If v is _min If the target leakage end point t is the target leakage end point t, turning to the step (4);

(3) For v _min The Path cost Back (n) from the net source end s to n and the Path cost Path (n) from s to t through n are calculated, and the step 2 is executed. Back (n) and Path (n) are as follows:

Back(n)＝Back(v _min )+c(n)

Path(n)＝Back(n)+α×est _nt

wherein est _nt Representing the path estimation cost from node n to t, the parameter α being used to balance the effect of the path estimation cost in the total path cost, c (n) representing the cost of use of node n;

(4) A path is established from t to the net source s.

According to the FPGA pre-wiring method based on the virtual net, the optimal wiring scheme of each connection mode in the FPGA is calculated in advance, so that the calculated amount in the actual wiring process can be reduced, and the wiring speed is remarkably increased.

The FPGA pre-wiring system provided by the embodiment of the invention comprises:

the connection number counting module is used for counting the number of the connection types in the FPGA;

the virtual net building module is used for building a virtual net for each type of connection resources;

and the virtual net wiring module is used for wiring the virtual net.

Example 2

The FPGA pre-wiring method provided by the embodiment of the invention comprises the following steps:

firstly, in a first stage of FPGA pre-wiring, counting various types of connection resources in the FPGA, and recording the number of the connection types as types.

Secondly, each type of connection resource comprises four trends, namely an upper trend, a lower trend, a left trend and a right trend, and a corresponding virtual line network and a corresponding coordinate system are respectively constructed for each trend, so that a virtual line network set is finally obtained: c = { U = _i ,D _i ,L _i ,R _i I is more than or equal to |0 and less than types }, wherein U is more than or equal to I and less than types _i 、D _i 、L _i 、R _i And the virtual line network sets are respectively corresponding to the i-th type connecting line in the upper, lower, left and right directions.

Thirdly, in the second stage of FPGA pre-wiring, C = { U ] on FPGA _i ,D _i ,L _i ,R _i And (3) wiring the virtual nets in the I0 is more than or equal to i and less than types, only considering the time delay and the basic use cost of the nodes in the pre-wiring process, and usually, a plurality of optimal wiring paths exist in each virtual net connection.

Preferably, the method for fast FPGA wiring provided by the embodiment of the present invention includes the specific steps of:

firstly, counting the number typeof the connection resources contained in the FPGA, wherein the connection resources of each type have differences in connection length, time delay and the like.

And secondly, each type of connection resources run in four directions of up, down, left and right in the FPGA, as shown in FIG. 3. Respectively constructing a group of virtual net aiming at each trend of each connection line, and finally obtaining a virtual net set: c = { H _i I is more than or equal to |0 and less than types }, wherein H _i And representing the virtual net set corresponding to the ith connection type, wherein the virtual net set comprises four trend conditions of the connection of the type. The method specifically comprises the following steps:

step 1, establishing a corresponding two-dimensional coordinate system for each trend of the connecting line, wherein the origin of the coordinate system is the right front position of the connecting line, as shown in fig. 3. With this coordinate system, each virtual net connection can be accurately represented in two-dimensional coordinates.

And 2, constructing a virtual wire network for the ith type of connecting wire in four connecting wire directions of upper, lower, left and right, specifically constructing virtual connections from the type of connecting wire to all target positions on the FPGA, wherein each target position can be uniquely represented as (x, y) in the constructed two-dimensional coordinate system, as shown in FIG. 4. The connections in the virtual connections are not specific connections within the FPGA, and each virtual connection may be mapped to an actual connection in a different region on the FPGA.

Step 3, when the virtual nets are constructed for all types of nets, a virtual net set C = { H } is obtained _i I is more than or equal to 0 and less than types, and the virtual net H corresponding to the ith connection type _i The method comprises the following four steps: h _i ＝{U _i ,D _i ,L _i ,R _i In which U is _i 、D _i 、L _i 、R _i And the virtual net sets are respectively corresponding to the upper, lower, left and right trends of the ith type of connecting line. Wherein

X = { (X, y) | -W ≦ X ≦ W, -H ≦ y ≦ H }, where (X, y) represents one virtual net connection, and W and H represent the width and height of the FPGA, respectively.

And thirdly, mapping each virtual net in the set C into actual net connection on the FPGA, requiring the virtual net and the mapped actual net to keep consistent in the connection type and the target relative position, and recording the connection and target points which form the actual net after mapping as w and t respectively.

And fourthly, routing the actual net connection on the routing resource graph, specifically, using an A-star algorithm to find the optimal routing path from w to t. The method specifically comprises the following steps:

step 1, recording the optimal path cost as cost, and initially setting the cost as-1. The Path cost Path (w) for w is calculated and added to the small top heap (denoted as Q). Path (w) is defined as:

Path(w)＝c(w)+α×est _wt

wherein c (w) represents the cost of node w, est _wt Representing the path estimation cost from node w to t, and the parameter a is used to balance the effect of the path estimation cost in the total path cost. c (w) is defined as:

c(w)＝d _w +b _w

wherein d is _w And d _w Respectively representing the delay and the basic usage cost of the slave node w.

Step 2, removing the node v with the minimum cost from Q _min . If v is _min If the target leakage end point t is obtained, the step 4 is executed.

Step 3. For v _min The Path cost Back (n) from the net source end s to n and the Path cost Path (n) from s to t through n are calculated, and the step 2 is executed. Back (n) and Path (n) are as follows:

Back(n)＝Back(v _min )+c(n)

Path(n)＝Back(n)+α×est _nt

wherein est is _nt Representing the path estimation cost from node n to t, the parameter a is used to balance the effect of the path estimation cost in the total path cost, and c (n) represents the cost of use for node n.

And 4, establishing and storing a path from the t to the net source end s. If the cost is equal to-1 or the cost of the node with the minimum cost in the Q is equal to the cost of the current path, setting the cost as the cost of the current path, and continuing to execute the step 2; otherwise, the pre-wiring is finished.

The fifth step, finally, for the virtual net set

The corresponding pre-wiring result is noted as P _i ＝{Ω _x,y X is | -W ≦ x ≦ W, -H ≦ y ≦ H }, where Ω _x,y Is P _i And (4) a set formed by all optimal wiring paths of the middle virtual wire net (x, y).

2. Application examples. In order to prove the creativity and the technical value of the technical scheme of the invention, the part is the application example of the technical scheme of the claims on specific products or related technologies.

The first application embodiment: pre-wiring is performed on an FPGA that contains only a single wiring resource.

Description of the problems: the pre-wiring is performed on the following specifications of the FPGA: the length and the width of the FPGA are respectively 25 and 30, and a connecting wire with the length of 4 is integrated inside the FPGA.

Constructing a virtual wire net: because only one type of connection resources exists inside the FPGA, the type of connection is distributed in horizontal and vertical channels in the FPGA. A two-dimensional coordinate system and a group of virtual nets are constructed for the four distributions of the upper, lower, left and right directions of the connecting line, and the virtual net distributions corresponding to the four directions are stored in a set U ₀ 、 D ₀ 、L ₀ 、R ₀ In (1). Each group of virtual nets contains connections for all possible shapes on the FPGA, e.g., set U ₀ The method specifically comprises the following steps: u shape ₀ = { (x, y) | -25 ≦ x ≦ 25, -30 ≦ y ≦ 30}, any of them

A virtual net is represented. Finally, a virtual wire net set C = { { U) corresponding to the FPGA is obtained ₀ ,D ₀ ,L ₀ ,R ₀ }}。

Pre-wiring of a virtual net: because the virtual nets have no fixed coordinates on the FPGA, when each virtual net (x, y) is wired, it is necessary to map it onto the FPGA and obtain an actual net, which can be represented as w-t, where w is a specific connection of the same type in the FPGA, t represents a logic unit at a target position, and t is (x, y) with respect to the coordinates of w. Next, an A-algorithm is used to find all optimal wiring paths from w to t, each represented as a sequence of programmable points { c } ₁ ,c ₂ ,., and saving the found optimal wiring path in the set Ω _x,y In (1). When the FPGA is actually wired, an optimal wiring path does not need to be searched node by node, and the routing of the path level can be realized by calculating the shape of an actual net and inquiring the pre-wiring result of a corresponding virtual net, so that the required time is far shorter than that of the traditional node level wiring strategy.

Application example two: and pre-wiring is carried out on the FPGA containing the multi-type connecting resources.

Problem description: the pre-wiring is performed on the following specifications of the FPGA: the length and the width of the FPGA are respectively 25 and 30, and connecting wires with the lengths of 4 and 6 are integrated inside the FPGA.

Constructing a virtual wire net: for in FPGAEach connection type respectively constructs a two-dimensional coordinate system and a group of virtual nets for the four directions of upper, lower, left and right, and the virtual net distribution corresponding to the four directions is stored in a set U _i 、D _i 、L _i 、R _i (i =0,1). Each group of virtual nets contains connections for all possible shapes on the FPGA, e.g., set U ₀ The method specifically comprises the following steps: u shape ₀ = { (x, y) | -25 ≦ x ≦ 25, -30 ≦ y ≦ 30}, any of them

A virtual net is represented. Finally, a virtual wire net set C = { { U) corresponding to the FPGA is obtained _i ,D _i ,L _i ,R _i }|i＝0,1}。

Pre-wiring of a virtual net: because the virtual nets have no fixed coordinates on the FPGA, when each virtual net (x, y) is wired, it is necessary to map it onto the FPGA and obtain an actual net, which can be represented as w-t, where w is a specific connection of the same type in the FPGA, t represents a logic unit at a target position, and t is (x, y) with respect to the coordinates of w. Next, the A-algorithm is used to find all optimal wiring paths from w to t, each represented as a programmable sequence of points { c } for the wire resources ₁ ,c ₂ ,., and saving the found optimal wiring path in the set Ω _x,y In (1). When the FPGA is actually wired, an optimal wiring path does not need to be searched node by node, and the routing of the path level can be realized by calculating the shape of an actual net and inquiring the pre-wiring result of a corresponding virtual net, so that the required time is far shorter than that of the traditional node level wiring strategy.

3. Evidence of the relevant effects of the examples. The embodiment of the invention achieves some positive effects in the process of research and development or use, and has great advantages compared with the prior art, and the following contents are described by combining data, diagrams and the like in the test process.

The effects of the present invention can be further illustrated by the following simulations:

1. and (3) simulating conditions, namely simulating on a Linux system, wherein a hardware platform comprises two Intel Xeon E5-2630 v4 processors and a 128GB memory. The FPGA pre-wiring method based on the virtual net is realized on an FPGA layout and wiring tool VPR (Versatile layout and Routing) 8.0 developed by Toronto theory. VPR 8.0 is one of the best tools currently in the academia for Field Programmable Gate Array (FPGA) place and route issues.

2. Simulation content, the pre-wiring method based on the virtual net and a VPR 8.0 wiring tool which is commonly used internationally are respectively adopted to carry out simulation experiments, and the CPU time consumption in the wiring process and the time delay and the wire length of a circuit after the wiring result are compared. Wherein, the delay represents the final circuit key path delay and determines the operation speed of the final circuit; the wire length represents the total wire length to be used by the final circuit. And repeating the simulation for 10 times every time, and averaging the simulation experiment results to obtain the comparison between the wiring speed and the quality simulation of the pre-wiring method and the conventional VPR 8.0 wiring method.

3. Simulation result (see Table 1)

TABLE 1 comparison of the Pre-routing method of the present invention with the VPR 8.0 routing results

According to the simulation experiment and the data result, compared with the current mainstream VPR 8.0 wiring method, the virtual net-based pre-wiring method provided by the invention has the advantage that the wiring time is reduced by 48% under the condition of keeping the delay and the wire length. Wherein the time delay is basically kept unchanged, and the line length is optimized by 1.4 percent. When the circuit is larger, the acceleration effect of the invention on FPGA wiring is better.

In summary, the invention relates to a virtual net-based FPGA pre-wiring method, belonging to the field of computers. According to the invention, the optimal wiring scheme in different connection modes is found out by wiring on the FPGA in advance by utilizing the priori information of the internal wiring resources of the FPGA, so that a large amount of time is not required to be consumed in the actual wiring process, the actual wiring time consumption is reduced, the practical value is very high, and the research and development of the domestic FPGA EDA software are particularly facilitated.

It should be noted that the embodiments of the present invention can be realized by hardware, software, or a combination of software and hardware. The hardware portions may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus of the present invention and its modules may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, or software executed by various types of processors, or a combination of hardware circuits and software, e.g., firmware.

The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. Firstly, respectively constructing a group of abstract virtual nets on the FPGA according to the connection mode of various types of connection resources, wherein each virtual net can be mapped to different areas on the FPGA to further form different actual nets; and then, pre-wiring the virtual net, and constructing an optimal wiring scheme by using the virtual wiring resources.

2. The FPGA pre-wiring method of claim 1, wherein the FPGA pre-wiring method comprises the steps of:

step one, calculating various types of connection resources in the FPGA, and recording the number of the connection types as types;

step two, respectively constructing corresponding virtual nets for each type of connecting line resources, and finally obtaining a virtual net set C = { H = (H) } _i I is more than or equal to |0 and less than types }, wherein H _i Representing a virtual line network set corresponding to the ith connection type;

step three, mapping the virtual net into actual net connection on the FPGA for each virtual net in the set C; the virtual net and the mapped actual net are kept consistent in the connection type and the target relative position, and the connection line and the target point which form the actual net after mapping are respectively marked as w and t;

step four, wiring the actual net connections on the wiring resource graph, searching the optimal wiring path from w to t by using an A-x algorithm, wherein each virtual net connection has a plurality of optimal wiring schemes;

step five, for the virtual net set

The corresponding pre-wiring result is noted as P _i ＝{Ω _x,y X is | -W ≦ x ≦ W, -H ≦ y ≦ H }, where Ω _x,y Is P _i And (5) a set formed by all the optimal wiring paths of the middle virtual wire network (x, y).

3. The FPGA pre-wiring method of claim 2, wherein in step one, each type of wiring resource has a difference in wiring length and delay.

4. The FPGA pre-wiring method of claim 2, wherein in the second step, each type of wiring resource corresponds to four directions, i.e., up, down, left, and right, in the FPGA, and a virtual net is constructed for each of the four directions of the wiring.

5. The FPGA pre-wiring method of claim 2, wherein in step two, constructing a virtual net for each type of connection on the FPGA comprises:

(1) Establishing a corresponding two-dimensional coordinate system for each trend of the connecting lines, wherein each virtual line network connection is represented by a two-dimensional coordinate;

(2) For the ith type of connecting wire, constructing a virtual wire network for the upper, lower, left and right connecting wire trends respectively; constructing virtual connections from the type connecting lines to all target positions on the FPGA, wherein each target position can be uniquely represented as (x, y) in the constructed two-dimensional coordinate system; the connection lines in the virtual connections are not specific connection lines in the FPGA, and each virtual connection is mapped to actual connection of different areas on the FPGA;

(3) When virtual nets are constructed for all types of nets, a virtual net set C = { H } is obtained _i I is more than or equal to 0 and less than types, and the virtual net H corresponding to the ith connection type _i The device comprises four parts: h _i ＝{U _i ,D _i ,L _i ,R _i In which U is _i 、D _i 、L _i 、R _i The virtual net sets are respectively corresponding to the upper, lower, left and right trends of the ith type of connecting line; wherein

X＝{(x,y)|-W≤x≤W,-H≤y≤H}。

6. The FPGA pre-wiring method of claim 2, wherein in step four, constructing a virtual net for each type of wire comprises:

(1) The optimal path cost is marked as cost, and the cost is initially set as-1; calculating Path cost Path (w) of w, and adding w to the small top heap, denoted as Q, path (w) is defined as:

Path(w)＝c(w)+α×est _wt ；

wherein c (w) represents the cost of node w, est _wt Representing the path estimation cost from node w to t, with a parameter α used to balance the impact of the path estimation cost in the total path cost, and c (w) defined as:

c(w)＝d _w +b _w ；

wherein, d _w And d _w Respectively representing the time delay and the basic use cost of the slave node w;

(2) Removing cost minimum node v from Q _min (ii) a If v is _min If the target leakage end point t is the target leakage end point t, turning to the step (4);

(3) For v _min The neighbor node n calculates the Path cost Back (n) from the net source end s to n and the Path cost Path (n) from s to t, and the step (2) is executed; back (n) and Path (n) are as follows:

Back(n)＝Back(v _min )+c(n)；

Path(n)＝Back(n)+α×est _nt ；

wherein est is _nt Representing the path estimation cost from node n to t, the parameter α being used to balance the impact of the path estimation cost in the total path cost, c (n) representing the cost of use of node n;

(4) Establishing and storing a path from t to a net source end s; if the cost is equal to-1 or the cost of the node with the minimum cost in the Q is equal to the cost of the current path, setting the cost as the cost of the current path, and continuing to execute the step (2); otherwise, the pre-wiring is finished.

7. An FPGA pre-wiring system applying the FPGA pre-wiring method according to any one of claims 1 to 6, characterized in that the FPGA pre-wiring system comprises:

the connection quantity counting module is used for counting the number of the internal connection types of the FPGA;

the virtual net building module is used for building a virtual net for each type of connection resource;

and the virtual net wiring module is used for wiring the virtual net.

8. Computer arrangement, characterized in that the computer arrangement comprises a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of the FPGA pre-wiring method according to any one of claims 1 to 6.

9. A computer-readable storage medium, storing a computer program which, when executed by a processor, causes the processor to carry out the steps of the FPGA pre-wiring method of any one of claims 1 to 6.

10. An information data processing terminal, characterized in that the information data processing terminal is used for implementing the FPGA pre-wiring system as claimed in claim 7.

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