CN115688509A - Electric-thermal joint simulation method for multi-chip SiC MOSFET parallel power semiconductor module - Google Patents
Electric-thermal joint simulation method for multi-chip SiC MOSFET parallel power semiconductor module Download PDFInfo
- Publication number
- CN115688509A CN115688509A CN202211192923.2A CN202211192923A CN115688509A CN 115688509 A CN115688509 A CN 115688509A CN 202211192923 A CN202211192923 A CN 202211192923A CN 115688509 A CN115688509 A CN 115688509A
- Authority
- CN
- China
- Prior art keywords
- chip
- sic mosfet
- simulation
- power semiconductor
- semiconductor module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses an electric-thermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module, which comprises the following steps: 1) Initializing an SPICE simulation file and a COMSOL finite element simulation file based on the three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module; 2) Under the condition of simulating a given working condition, when the multi-chip SiC MOSFET parallel power semiconductor module works in a steady state, calculating the bus voltage and the load current of the multi-chip SiC MOSFET parallel power semiconductor module, and writing the bus voltage and the load current into an SPICE simulation file; 3) Giving an iteration initial temperature, a convergence condition and a maximum iteration number of the joint simulation; 4) Modifying the junction temperature of the SiC MOSFET chip in the SPICE simulation file to be an iteration initial temperature, and simulating by operating SPICE software; 5) Solving the power loss of each SiC MOSFET chip in the multi-chip SiC MOSFET parallel power semiconductor module; 6) The junction temperature of each SiC MOSFET chip is extracted, and the method has the characteristics of good convergence, high simulation efficiency, high simulation accuracy and wide adaptability.
Description
Technical Field
The invention relates to an electric-heating joint simulation method, in particular to an electric-heating joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module.
Background
Compared with the traditional silicon-based power semiconductor device, the wide bandgap power semiconductor device represented by silicon carbide (SiC) and gallium nitride (GaN) has the excellent characteristics of high blocking voltage, high switching frequency, low on-resistance and the like, and is expected to replace the traditional silicon-based device in high-power electronic applications such as electric automobiles, new energy power generation grid-connection, full-electric airplanes and ships and the like. The area and the current capacity of a single chip of the novel power semiconductor device are far smaller than those of the traditional silicon-based power semiconductor device, and the novel power semiconductor device is required to be used by connecting multiple chips in parallel under a high-power application scene so as to meet the requirement of working conditions.
The current distribution among parallel chips is obviously influenced by circuit parasitic parameter differences brought by chip layout, the loss among the chips is different due to the current imbalance among the chips, and finally the junction temperature difference of the chips is caused. Many characteristic parameters of the power semiconductor device are temperature-sensitive parameters, and the junction temperature difference further influences current distribution among chips, so that the problems of unbalanced current and junction temperature difference are solved. The power semiconductor chip is the most main heating source in the module, and the accurate evaluation of the temperature of each parallel chip of the power semiconductor module and the temperature difference among the parallel chips has important significance and value on the early design verification and the service life prediction of the module and the evaluation of the thermal stability and the thermal reliability in the whole life cycle.
Circuit simulation of multi-chip parallel power semiconductor modules typically uses simulation software based on the SPICE language, such as PSpice, LTspice, and the like. The software can accurately describe the change of voltage and current in the switching process of the chip by matching with an SPICE model of the power semiconductor device, so that a simulation result of single switching loss is obtained. The mainstream control method of the converter is based on Pulse Width Modulation (PWM) control, and the current converter is developed toward high frequency. Under most working conditions, the switching frequency of the converter is high when the converter works in a steady state, if the module loss in the steady state is obtained by starting simulation under the module zero initial condition, the simulation time is long, the simulation switching times are large, and the simulation efficiency is seriously reduced.
The chip loss and the chip junction temperature have a strong coupling relation, and in order to couple the chip loss and the chip junction temperature, a one-dimensional RC thermal network is added into SPICE circuit software to represent a heat dissipation part of a power module in the traditional method. The application of the one-dimensional RC thermal network method in the multi-chip parallel power semiconductor module has the following problems: the method is limited by the size of a module, the chip spacing of the multi-chip parallel power module is small, the thermal coupling phenomenon among chips is serious, the traditional one-dimensional RC thermal network model cannot effectively describe the thermal coupling relation of each chip in the module, and an accurate chip junction temperature simulation result cannot be obtained; some scholars propose a three-dimensional RC thermal network model to reflect the thermal coupling relation among chips, so that the accuracy of the RC model is improved, but the construction of the model either needs to solve a partial differential equation set or needs finite element simulation software to assist in calculation, so that the process is very complicated; and the RC thermal network model can only evaluate the junction temperature of the chip, lacks the temperature results of other important components in the module, such as a bonding wire and a welding layer, and cannot provide technical support for reliability evaluation and service life prediction of the whole module.
Finite element simulation software represented by Ansys and COMSOL can obtain complete temperature distribution of the multi-chip parallel Si C MOSFET power semiconductor module including all components. The temperature simulation of the module by using the finite element software needs to give the loss of the chip as an initial boundary condition required by the simulation in advance. However, the chip loss and the chip junction temperature have a strong coupling relationship, and the temperature given by the initial calculation loss and the temperature obtained by software simulation have a considerable difference, which seriously affects the accuracy of the result. The two types of finite element software are internally provided with circuit simulation sub-software or modules: compatibility problem exists when circuit simulation software ANSYS Twin Builder in AN SYS imports a device SPICE model provided by a third-party device manufacturer, and convergence of a calculation result is poor; the AC/DC module in COMSOL has certain circuit simulation capability, but does not support the SPICE model of the lead-in device, has low simulation precision, and can not be directly coupled with the solid and fluid heat transfer module in COMSOL. For some power semiconductor modules in liquid cooling heat dissipation forms, the flow channels of the power semiconductor modules are specially designed, transient simulation is carried out in finite element software, and the convergence is poor. The chip-level electrothermal coupling simulation of the module cannot be well performed only by using finite element software.
Through the above analysis, the existing simulation techniques have problems including: the simulation time of the full switching period is long, and the efficiency is low; the precision of simulation by using single software is not high enough, the temperature of all components of the multi-chip parallel power module cannot be fully reflected, and the adaptability is poor; and aiming at the partial liquid cooling heat dissipation structure form, the convergence of transient simulation by using finite element software is poor.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an electrothermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module, which has the characteristics of good convergence, high simulation efficiency, high simulation accuracy and wider adaptability.
In order to achieve the aim, the invention discloses an electric-thermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module, which comprises the following steps of:
1) Initializing an SPICE simulation file and a COMSOL finite element simulation file based on the three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module;
2) Under the condition of simulating a given working condition, when the multi-chip SiC MOSFET parallel power semiconductor module works in a steady state, calculating the bus voltage and the load current of the multi-chip SiC MOSFET parallel power semiconductor module, and writing the bus voltage and the load current into an SPICE simulation file;
3) Giving an iteration initial temperature, a convergence condition and a maximum iteration number of the joint simulation;
4) Modifying the junction temperature of the SiC MOSFET chip in the SPICE simulation file to be an iteration initial temperature, and simulating by operating SPICE software;
5) Solving the power loss of each SiC MOSFET chip in the multi-chip SiC MOSFET parallel power semiconductor module according to the simulation result obtained in the step 4);
6) Modifying the heat source power of each SiC MOSFET chip in the COMSOL simulation file, controlling the heat source power to simulate the heat source power, and extracting the junction temperature of each SiC MOSFET chip;
7) Judging whether the simulation result is converged or not, simultaneously judging whether the maximum iteration number is reached or not, and outputting the simulation result and ending the simulation when the simulation result is converged; when the simulation result is not converged and reaches the maximum iteration number, outputting a simulation non-convergence prompt and ending the simulation; otherwise, the junction temperature of each SiC MOSFET chip obtained by the simulation is used as the input of a new iteration, and the steps 4) to 6) are repeated until the simulation is finished.
The specific operation of the step 1) is as follows:
determining the chip layout and size parameters of the multi-chip SiC MOSFET parallel power semiconductor module, constructing a three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module in CAD software, and initializing an SPICE simulation file and a COMSOL finite element simulation file based on the multi-chip SiC MOSFET parallel power semiconductor module.
In the step 2), in MATLAB, under the condition of simulating a given working condition, when the multi-chip SiC MOSFET parallel power semiconductor module works in a steady state, calculating the bus voltage and the load current of the multi-chip SiC MOSFET parallel power semiconductor module.
In the step 4), MATLAB is used for modifying the junction temperature of the SiC MOSFET chip in the SPICE simulation file to be the iteration initial temperature.
And 5) solving the loss power of each SiC MOSFET chip in the power module by using a loss modeling method.
The specific operation of step 6) is as follows: and modifying the heat source power of each SiC MOSFET chip in the COMSOL simulation file through MATLAB, controlling the SiC MOSFET chips to start simulation, reading a preset temperature data table to extract the junction temperature of the SiC MOSFET chips after the simulation is finished, and storing the junction temperature of the SiC MOSFET chips into the MATLAB.
In the step 3), the iteration initial temperature is set as the circulating cooling temperature of the heat dissipation system.
Switching loss E of ith SiC MOSFET chip in multi-chip SiC MOSFET parallel power semiconductor module at given junction temperature ion And turn-off loss E ioff Respectively as follows:
E ion ＝f(I load )＝B 1 I load 2 +B 2 I load +B 3
E ioff ＝f(I load )＝C 1 I load 2 +C 2 I load +C 3
the switching loss E of the ith SiC MOSFET chip iswitch ＝E ion +E ioff 。
The invention has the following beneficial effects:
when the electric-heat joint simulation method of the multi-chip SiC MOSFET parallel power semiconductor module is specifically operated, the SPICE simulation file and the COMSOL finite element simulation file are initialized based on the three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module, so that main factors influencing the junction temperature of the SiC MOSFET chip are taken into consideration, the simulation is more consistent with the actual working condition, and the simulation precision is higher. In addition, in the simulation process, under the condition of a given working condition of simulation, when the multi-chip SiC MOSFET parallel power semiconductor module works in a steady state, the bus voltage and the load current of the multi-chip SiC MOSFET parallel power semiconductor module are calculated and written into an SPICE simulation file, namely the steady-state working condition is mainly considered, so that the simulation in a transition stage from the initial state to the steady state is avoided, and the simulation efficiency is improved; transient simulation of fluid and heat transfer of the heat dissipation system is avoided, and simulation convergence is improved. Finally, it should be noted that the application of the invention is not limited by the limitations of a specific circuit topology, control strategy, device model and heat dissipation mode, and the invention can adapt to simulation calculation of different actual working conditions and has wide adaptability.
Drawings
FIG. 1 is a schematic view of the present invention;
FIG. 2 is a schematic diagram of the present invention;
FIG. 3 is a flow chart of the present invention;
FIG. 4 is a three-dimensional model diagram of a module built in CAD software;
FIG. 5 is a diagram of the results of grid division by importing a model into COMSOL multiphysics finite element simulation software;
FIG. 6 is a schematic diagram of chip on-resistance extraction and fitting by a data sheet;
FIG. 7 is a waveform diagram of a chip switch for SPICE simulation;
FIG. 8 is a graph of SPICE simulation results and fitting according to the results for chip switching losses;
FIG. 9 is a graph illustrating the junction temperature of the chips over a number of iterations;
FIG. 10 is a schematic diagram of module heat sink temperature at steady state;
fig. 11 is a schematic diagram of die source power bond wire temperature in a module at steady state.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, and do not limit the scope of the disclosure of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
There is shown in the drawings a schematic block diagram of a disclosed embodiment in accordance with the invention. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of the various regions, layers and their relative sizes, positional relationships are shown in the drawings as examples only, and in practice deviations due to manufacturing tolerances or technical limitations are possible, and a person skilled in the art may additionally design regions/layers with different shapes, sizes, relative positions, according to the actual needs.
The invention adopts MATLAB as an intermediate script language to program, so as to control the proceeding of joint simulation, provide a coupling interface between simulation software and perform necessary calculation and data processing; the method for realizing the coupling interface with the simulation software of the SPIC E circuit comprises the following steps: a) Both a circuit file and a result file simulated by the SPICE software are unencrypted text files, and the reading and writing can be realized through a file reading and writing function built in the MATLAB software; b) The running of the simulation software can be realized through an operating system command line command of the MATLAB; c) And reading out output files formed in the simulation process of the SPICE software to know the simulation progress and judge whether the simulation is finished. The implementation method of the coupling interface with COMSOL finite element software is as follows: parameter modification, simulation process control and result reading of COMSOL software are all realized by a COMSOL Livelink with MATLAB module provided by COMSOL officials, and the module is written by using Java language.
The invention adopts circuit simulation software supporting SPICE language to simulate and fit the loss of each power semiconductor device in a multi-chip parallel SiC MOSFET module; simulating by COMSOL multi-physical-field finite element simulation software to obtain the temperature of each component in the module under a given heat dissipation condition; and obtaining the steady-state loss and the chip junction temperature of the multi-chip parallel power semiconductor module under the given working condition and the heat dissipation condition by an iterative method.
Referring to fig. 1 to fig. 11, specifically, the method for electrothermal joint simulation of a multi-chip SiC MOSFET parallel power semiconductor module according to the present invention includes the following steps:
1) Determining chip layout and size parameters of the multi-chip parallel power module, constructing a three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module in CAD software, and initializing an SPICE simulation file and a COMSOL finite element simulation file based on the three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module;
an electrical simulation part: extracting a parasitic parameter network according to a three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module established in CAD software to build a simulation circuit, wherein the parasitic parameter network can be extracted by using finite element simulation software, such as Ansys Q3D; the calculation can also be carried out by using a multiport network PEEC method or an empirical formula and combining size parameters. Establishing two SPICE circuit simulation files including a parasitic parameter network and a device model, wherein the topology is a half-bridge structure; and the two files are respectively an upper bridge arm and a lower bridge arm which are connected with a current source in parallel so as to simulate an inductive constant-current load.
The thermal simulation part: and importing the three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module into COMSOL multi-physical field finite element simulation software, setting materials for the three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module, dividing grids, giving other corresponding boundary conditions except chip loss power, setting the loss power of the SiC MOSFET chip as a variable as a heat source, and setting a temperature probe to obtain a temperature data table of the power semiconductor device for extracting the junction temperature of the SiC MOSFET chip.
2) According to the given working condition of simulation, under the working condition obtained by calculation in MATLAB, when the multi-chip SiC MOSFET parallel power semiconductor module works in a steady state, the multi-chip SiC MOSFET T is connected in parallel with the bus voltage and the load current of the power semiconductor module, and the bus voltage and the load current are written into parameters such as a direct current bus voltage source value, an output load current source value, and the switching frequency and duty ratio of PW M driven by the power module of an SPICE simulation file, wherein the given working condition of simulation comprises input/output and load conditions, a control strategy and a heat dissipation condition;
3) Giving an iteration initial temperature, a convergence condition and a maximum iteration number of the joint simulation;
the iteration initial temperature is set as the circulating cooling temperature of the heat dissipation system, namely the lowest temperature inside the multi-chip SiC MOSFET parallel power semiconductor module under the steady-state working condition. The judgment condition of iteration termination is set to be that the error of the junction temperature simulation results of the chips continuously twice is less than 1%, the judgment condition of iteration termination is adjusted according to the requirement of simulation precision, when the design is in an early stage of design verification, the design may have defects, for example, when the heat dissipation capacity is not matched with the working condition, the junction temperature of the SiC MOSFET chip is too high, and the simulation results are not converged. Therefore, when the early design verification is carried out, the termination judgment condition of the simulation iteration is also taken into consideration for judging the iteration times, and when the iteration times exceed the limit value, the simulation result is not converged, the simulation iteration is terminated and the design needs to be improved.
4) Using MATLAB to modify the junction temperature of a SiC MOSFET chip in SPICE to be an iteration initial temperature, and operating SPICE software to simulate, read out a file and judge whether the simulation is finished;
5) Reading a simulation result after simulation of SPICE software is finished, and solving the loss power of each SiC MOSFET chip in the multi-chip SiC MOSFET parallel power semiconductor module by using a loss modeling method;
the method for realizing the loss power modeling comprises the following steps:
because the switching frequency of the power semiconductor device is high, under the condition of common inductive load, the total current flowing through the load in one switching period has small change and is approximately constant. Meanwhile, the parameter difference between chips, dead time, the loss of the body diode in the dead time and the leakage current loss when the device is closed are ignored during the loss calculation. The loss of the SiC MOSFET chip mainly comprises conduction loss and switching loss, and loss modeling is also carried out in two parts.
The conduction losses include losses of forward and reverse conduction of the SiC MOSFET chip. No matter the current direction is, when calculating the conduction loss, the SiC MOSFET chip is similar to a resistor, and the resistance value is the on-resistance R of the SiC MOSFET chip dson (ii) a Meanwhile, the drive current of the grid electrode of the SiC MOSFET chip is ignored, and the current flowing through the drain electrode and the source electrode when the SiC MOSFET chip is conducted is approximately considered to be equal. Extracting the on-resistance R of the SiC MOSFET chip from a data manual of the SiC MOSFET chip provided by a manufacturer dson And (3) obtaining a curve which changes along with the junction temperature of the SiC MOSFET chip by fitting by using a quadratic function:
R dson (T junc )＝f(T junc )＝A 1 T junc 2 +A 2 T junc +A 3
wherein, T junc Because the junction temperature of the SiC MOSFET chips is different, the on-resistance between the SiC MOSFET chips in a steady state also existsIn the difference, when the SiC MOSFET chips are connected in parallel and are conducted in a steady state, according to kirchhoff's law, there are:
I load ＝∑I id
I 1d ×R 1dson ＝I 2d ×R 2dson ＝…＝I id ×R idson ＝…
wherein, I id Is the current, R, flowing through the ith SiC MOSFET chip idson Solving the equation set for the on-resistance of the ith SiC MOSFET chip to obtain the current flowing through each SiC MOSFET chip in parallel connection in the on state, and the on-loss E of the ith SiC MOSFET chip in the switching period icond Comprises the following steps:
E icond ＝I id 2 ×R idson ×T cond
wherein, T cond The time that the SiC MOSFET chip is on during the switching period.
The grid of the SiC MOSFET chip is turned on by a threshold voltage V GSth Is a temperature sensitive parameter, so the switching loss of the SiC MOSFET chip is also affected by the junction temperature of the SiC MOSFET, which is already considered in the SPICE model of the SiC MOSFET chip. And calculating the switching loss of each SiC MOSFET chip under a steady-state working condition, and considering the voltage and current stress born by the switching transient SiC MOSFET chip while considering the junction temperature of the SiC MOSFET chip. For the DC-DC topology, the voltage and current stress borne by the SiC MOSFET chip in the switching process during steady-state work under a given working condition is a fixed value, the value is assigned to a bus voltage source and a load current source in two SPICE simulation files through an MATLAB script, the switching waveforms of the chips of an upper bridge arm and a lower bridge arm are respectively solved, and the switching loss of each SiC MOSFET chip is calculated through the waveforms; for the DC-AC topology, the voltage stress borne by the SiC MOSFET chip is the DC bus voltage, but the total load current is AC variation, and the method for solving the switching loss by simulating hundreds to thousands of switching cycles in one AC cycle is inefficient. Therefore, 20 to 50 points are selected from the total load current 0 to the peak value for simulation, and then simulation results of all nodes are respectively extractedAnd waveforms in the switching-on and switching-off processes are obtained, and loss values of the switching-on and switching-off of each SiC MOSFET chip at each node are calculated respectively. Finally, a curve of the loss of turn-on and turn-off of each SiC MOSFET chip in the module under the given bus voltage and junction temperature along with the change of the total load current is fitted through a quadratic function, namely the turn-on loss E of the ith SiC MOSFET chip in the module under the given junction temperature ion And turn-off loss E ioff Respectively as follows:
E ion ＝f(I load )＝B 1 I load 2 +B 2 I load +B 3
E ioff ＝f(I load )＝C 1 I load 2 +C 2 I load +C 3
the switching loss E of the ith SiC MOSFET chip iswitch ＝E ion +E ioff 。
In summary, the total loss E of the ith SiC MOSFET chip in a switching period itotal ＝E iswitch +E icond 。
For the DC-DC topology, when the steady state of the given working condition is realized, the voltage and current stress of the SiC MOSFET chips in the module is a fixed value, the loss of each SiC MOSFET chip in the switching period is the same, and then the dissipated power P of the ith SiC MOSFET chip is i ＝E itotal ×f switch Wherein f is switch The switching frequency of the power semiconductor device; for a DC-AC topology, the load current varies in alternating current, and each AC output alternating current period T under a steady state condition out The loss of the SiC MOSFET chip is the same, the total loss is obtained by adding the losses of all the switching periods in each AC period, and the dissipation power of the SiC MOSFET chip in the AC period, namely P, is obtained i ＝∑E itotal ×f out 。
6) Modifying the heat source power of each SiC MOSFET chip in a COMSOL simulation file through MATLAB, controlling the SiC MOSFET chip to start simulation, reading a preset temperature data table to extract the junction temperature of the SiC MOSFET chip after the simulation is finished, and storing the junction temperature of the SiC MOSFET chip into MA TLAB;
7) Performing convergence judgment and maximum iteration number judgment in MATLAB, and outputting a simulation result and ending the simulation when the simulation result is converged; when the simulation result is not converged and reaches the maximum iteration number, outputting a simulation non-convergence prompt and ending the simulation; and when the simulation result is not converged and the maximum iteration number is not reached, the junction temperature of each SiC MOSFET chip obtained by the simulation is used as the input of a new iteration, and the steps 4) to 6) are repeated until the simulation is finished.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (8)
1. An electric-thermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module is characterized by comprising the following steps:
1) Initializing an SPICE simulation file and a COMSOL finite element simulation file based on the three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module;
2) Under the condition of simulating a given working condition, when the multi-chip SiC MOSFET parallel power semiconductor module works in a steady state, calculating the bus voltage and the load current of the multi-chip SiC MOSFET parallel power semiconductor module, and writing the bus voltage and the load current into an SPICE simulation file;
3) Giving an iteration initial temperature, a convergence condition and a maximum iteration number of the joint simulation;
4) Modifying the junction temperature of the SiC MOSFET chip in the SPICE simulation file to be an iteration initial temperature, and simulating by operating SPICE software;
5) Solving the power loss of each SiC MOSFET chip in the multi-chip SiC MOSFET parallel power semiconductor module according to the simulation result obtained in the step 4);
6) Modifying the heat source power of each SiC MOSFET chip in the COMSOL simulation file, controlling the heat source power to simulate, and extracting the junction temperature of each SiC MOSFET chip;
7) Judging whether the simulation result is converged or not, simultaneously judging whether the maximum iteration number is reached or not, and outputting the simulation result and ending the simulation when the simulation result is converged; when the simulation result is not converged and reaches the maximum iteration number, outputting a simulation non-convergence prompt and ending the simulation; otherwise, the junction temperature of each SiC MOSFET chip obtained by the simulation is used as the input of a new iteration, and the steps 4) to 6) are repeated until the simulation is finished.
2. The electrothermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module according to claim 1, wherein the specific operations of step 1) are as follows:
determining the chip layout and size parameters of the multi-chip SiC MOSFET parallel power semiconductor module, constructing a three-dimensional model of the multi-chip SiC MOSFET parallel power semiconductor module in CAD software, and initializing an SPICE simulation file and a COMSOL finite element simulation file based on the multi-chip SiC MOSFET parallel power semiconductor module.
3. The electrothermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module according to claim 1, wherein in step 2), in MATLAB, under a given working condition of simulation, when the multi-chip SiC MOSFET parallel power semiconductor module is in steady-state operation, the bus voltage and the load current of the multi-chip SiC MOSFET parallel power semiconductor module are calculated.
4. The method for electrothermal joint simulation of a multi-chip SiC MOSFET parallel power semiconductor module according to claim 1, wherein in step 4), MATLAB is used to modify the junction temperature of the SiC MOSFET chip in the SPICE simulation file to an iterative initial temperature.
5. The method for electrothermal joint simulation of a multi-chip SiC MOSFET parallel power semiconductor module according to claim 1, wherein in step 5), the loss power of each SiC MOSFET chip in the power module is solved using a loss modeling method.
6. The electrothermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module according to claim 1, wherein the specific operation of step 6) is: and modifying the heat source power of each SiC MOSFET chip in the COMSOL simulation file through MATLAB, controlling the SiC MOSFET chips to start simulation, reading a preset temperature data table to extract the junction temperature of the SiC MOSFET chips after the simulation is finished, and storing the junction temperature of the SiC MOSFET chips into the MATLAB.
7. The method for electrothermal joint simulation of a multi-chip SiC MOSFET parallel power semiconductor module according to claim 1, wherein in step 3), the iterative initial temperature is set to be a circulating cooling temperature of the heat dissipation system.
8. The electrothermal joint simulation method of a multi-chip SiC MOSFET parallel power semiconductor module according to claim 1, wherein the turn-on loss E of the ith SiC MOSFET chip in the multi-chip SiC MOSFET parallel power semiconductor module at a given junction temperature ion And turn-off loss E ioff Respectively as follows:
E ion ＝f(I load )＝B 1 I load 2 +B 2 I load +B 3
E ioff ＝f(I load )＝C 1 I load 2 +C 2 I load +C 3
switching loss E of the ith SiC MOSFET chip iswitch ＝E ion +E ioff 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211192923.2A CN115688509A (en) | 2022-09-28 | 2022-09-28 | Electric-thermal joint simulation method for multi-chip SiC MOSFET parallel power semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211192923.2A CN115688509A (en) | 2022-09-28 | 2022-09-28 | Electric-thermal joint simulation method for multi-chip SiC MOSFET parallel power semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115688509A true CN115688509A (en) | 2023-02-03 |
Family
ID=85065528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211192923.2A Pending CN115688509A (en) | 2022-09-28 | 2022-09-28 | Electric-thermal joint simulation method for multi-chip SiC MOSFET parallel power semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115688509A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116341471A (en) * | 2023-03-30 | 2023-06-27 | 深圳信创产业发展有限公司 | Layout structure simulation design method for semiconductor power device characteristics |
-
2022
- 2022-09-28 CN CN202211192923.2A patent/CN115688509A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116341471A (en) * | 2023-03-30 | 2023-06-27 | 深圳信创产业发展有限公司 | Layout structure simulation design method for semiconductor power device characteristics |
| CN116341471B (en) * | 2023-03-30 | 2023-11-24 | 广西中科蓝谷半导体科技有限公司 | Layout structure simulation design method for semiconductor power device characteristics |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107341326B (en) | Service life evaluation method for modular multilevel converter | |
| CN113657064B (en) | Multi-physical-field joint simulation method for power semiconductor module | |
| CN110765601B (en) | IGBT junction temperature estimation method based on IGBT thermoelectric coupling model | |
| CN113435090B (en) | IGBT module electro-thermal-fluid multi-field coupling simulation method based on working conditions | |
| CN110245414A (en) | Crimping type IGBT module multi-physical field coupling simulation method | |
| CN112560318B (en) | Temperature monitoring simulation method for each physical layer of IGBT device under different working conditions | |
| CN115629553A (en) | High-spatial-temporal-resolution IGBT module electric heating stress calculation method | |
| CN103324843A (en) | Modular multilevel converter (MMC) valve loss calculation method applicable to different sub-module types | |
| CN109274255A (en) | The wind electric converter IGBT power module dynamic junction temperature calculation method that meter and stray inductance influence | |
| CN113536627B (en) | Multi-chip IGBT module thermal safety operation domain describing method | |
| CN115688509A (en) | Electric-thermal joint simulation method for multi-chip SiC MOSFET parallel power semiconductor module | |
| Mauromicale et al. | Sic power modules for traction inverters in automotive applications | |
| Li et al. | Using multi time-scale electro-thermal simulation approach to evaluate SiC-MOSFET power converter in virtual prototyping design tool | |
| CN114091286A (en) | MMC submodule IGBT on-state loss analysis method based on characteristic curve | |
| Yang et al. | An automated electro-thermal-mechanical co-simulation methodology based on pspice-matlab-comsol for sic power module design | |
| WO2022227657A1 (en) | Electric thermal performance analysis method and system of intelligent power unit and computer device | |
| Tran et al. | Multi-fidelity electro-thermal optimization of multiport converter employing SiC MOSFET and indirect liquid cooling | |
| Azuma et al. | Research on the power loss and junction temperature of power semiconductor devices for inverter | |
| CN115436769A (en) | Method and device for determining junction temperature of semiconductor power device | |
| Fang | Design and implementation of a thermal hardware-in-the-loop (THIL) platform for evaluating physical cooling systems in real-time simulation | |
| Pan et al. | Construction and application of electro-thermal co-simulation platform | |
| CN113759229A (en) | Power semiconductor switching loss measurement method and system based on temperature measurement | |
| CN113138329A (en) | Power cycle main circuit suitable for GaN power semiconductor device | |
| Goldmann et al. | Virtual double pulse tests to reduce measuring time and effort in semiconductor loss modeling | |
| CN117217153B (en) | LFBGA packaged electric heating joint simulation method based on field path coupling |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |