CN115687242A - FPGA for realizing module signal sharing by utilizing built-in local series module - Google Patents

Abstract

The application discloses an FPGA for realizing module signal sharing by utilizing a built-in local series module, which relates to the field of the FPGA, wherein the built-in local series module in the FPGA comprises at least one local interconnection line connected with a local control switch in series, each local interconnection line is respectively connected with a plurality of sharing ports belonging to the same signal sharing group, a local control switch is arranged between two adjacent sharing ports, and each sharing port is respectively one port of a preset resource module; and the configuration bits are used for controlling the conduction of local control switches on the local interconnection lines, and the multiple shared ports in the same signal sharing group realize signal transmission through the local interconnection lines. The signal transmission can be directly realized among the plurality of sharing ports needing to be connected in series in the FPGA through the local series module so as to share the signals, and the signal sharing is not required to be completed through a winding framework, so that the wiring congestion degree is reduced, the wiring elasticity is increased, the wiring rate is improved, and the time delay can be effectively reduced.

Description

FPGA for realizing module signal sharing by utilizing built-in local series module

Technical Field

The invention relates to the field of FPGA, in particular to an FPGA for realizing module signal sharing by utilizing a built-in local series module.

Background

An FPGA (Field Programmable Gate Array) internally contains a large number of resource modules such as CLBs, BRAMs, DSPs, IOBs, etc., which implement signal interconnections through a wire-wound architecture to implement a desired user design.

When user design is realized, a situation that signals need to be shared among resource modules often occurs, that is, a signal generated by the same signal source needs to be fanned out to a plurality of resource modules, and at this time, the signal generated by the signal source needs to be respectively connected to each resource module through different winding paths in a winding framework, so that the requirement for wiring resources is high, wiring congestion is easily caused, and the routing rate can be reduced.

Disclosure of Invention

In view of the above problems and technical needs, the present applicant proposes an FPGA for implementing module signal sharing by using a built-in local serial module, and the technical scheme of the present application is as follows:

an FPGA for realizing module signal sharing by utilizing a built-in local series module is internally provided with the local series module, the local series module comprises at least one local interconnection line which is connected with a local control switch in series, each local interconnection line is respectively connected with a plurality of shared ports belonging to the same signal sharing group, a local control switch is arranged between every two adjacent shared ports, and each shared port is a port of a preset resource module;

the local control switch on the local interconnection line is controlled to be conducted through the configuration bit, and a plurality of sharing ports in the same signal sharing group realize signal transmission through the local interconnection line; or the configuration bit controls the local control switch on the local interconnection line to be turned off, and the plurality of sharing ports in the same signal sharing group respectively realize respective signal transmission through the wire winding framework.

The further technical scheme is that a plurality of sharing ports in the same signal sharing group respectively belong to a plurality of preset resource modules, and the distance between the layout positions of the preset resource modules does not exceed a preset distance.

When a local control switch on a local interconnection line is controlled to be switched on through a configuration bit, the same signal is input into the local series module and is shared to other shared ports through the local interconnection line.

The further technical scheme is that a plurality of sharing ports of the same signal sharing group respectively belong to a plurality of BRAM modules, and when a configuration bit is used for controlling a local control switch on a local interconnection line in a local series module to be conducted, the plurality of BRAM modules realize a width expansion function or a depth expansion function through the local series module.

The method has the further technical scheme that address ports of a plurality of BRAM modules form a signal sharing group and are connected with a first local interconnection line, enable ports of the plurality of BRAM modules form a signal sharing group and are connected with a second local interconnection line, and control ports of the plurality of BRAM modules form a signal sharing group and are connected with a third local interconnection line;

local control switches on three local interconnection lines connected with the plurality of BRAM modules are controlled to be conducted through the configuration bits, and address signals are shared to address ports of the BRAM modules through the first local interconnection line; enabling signals are input through a connecting line of the winding framework and one enabling port and are shared to the enabling port of each BRAM module through a second local interconnecting line; the control signal is shared to the control port of each BRAM module through a third local interconnection line; the data ports of the BRAM modules respectively acquire data signals through the winding architecture, and the width expansion function is realized by the BRAM modules.

The data ports of a plurality of BRAM modules form a signal sharing group and are connected with a fourth local interconnection line, the address ports of a plurality of BRAM modules form a signal sharing group and are connected with a fifth local interconnection line, and the control ports of a plurality of BRAM modules form a signal sharing group and are connected with a sixth local interconnection line;

local control switches on three local interconnection lines connected with the plurality of BRAM modules are controlled to be conducted through the configuration bits, and data signals are input through a connection line of the winding framework and one control port and are shared to the data ports of the BRAM modules through a fourth local interconnection line; the control signal is shared to the control port of each BRAM module through a sixth local interconnection line; and partial signal bits of the address signals are shared to the address ports of the BRAM modules through a fifth local interconnection line, the enabling ports of the BRAM modules respectively obtain the rest signal bits of the address signals through the winding framework, and the BRAM modules realize the deep expansion function.

The further technical scheme is that address signals and control signals shared to each BRAM module through a local interconnection line are input by a winding framework; alternatively, the address signals and control signals shared to the various BRAM modules via local interconnect lines are both input by a FIFO controller.

When the number of the shared ports in the same signal sharing group is less than a preset threshold value, a local control switch on a local interconnection line connected with the shared ports in the signal sharing group is realized by adopting an NMOS (N-channel metal oxide semiconductor) tube, a transmission gate or a bidirectional three-state buffer;

when the number of the shared ports in the same signal sharing group reaches a preset threshold value, the local control switch on the local interconnection line connected with the shared ports in the signal sharing group is realized by adopting a bidirectional three-state buffer.

The technical scheme is that one or more local series modules are built in the FPGA, and each local series module is respectively arranged between the corresponding preset resource module and the winding framework; each local series module comprises one or more local interconnection lines, and each local interconnection line is used for connecting different signal sharing groups.

When the FPGA is applied, all local control switches on the local interconnection lines are controlled to be conducted through the configuration bits, so that all sharing ports in the same signal sharing group realize signal transmission through the local interconnection lines; or the configuration bit controls the conduction of part of local control switches on the local interconnection line and the disconnection of other part of local control switches, so that part of shared ports in the same signal sharing group realize signal transmission through the local interconnection line, and other part of shared ports realize signal transmission through the wire winding framework respectively.

The beneficial technical effect of this application is:

the application discloses utilize built-in local tandem module to realize FPGA of module signal sharing, this FPGA passes through the built-in local tandem module of hardware resource, can directly realize signal transmission through local tandem module between a plurality of sharing ports that need establish ties in order to carry out signal sharing, and need not to accomplish through the wire winding framework again, can reduce the signal of via the transmission of wire winding framework to reduce the wiring crowdedness degree, increase wiring elasticity, improve the wiring rate, and can effectively reduce the time delay.

The newly added local series modules do not affect the connection relationship between the resource modules and the winding framework, and when the local series modules are configured to be disconnected, the resource modules can still be connected with the corresponding signal sources through the winding framework, so that the normal operation of the original functions of the resource modules is not affected.

The width expansion and the depth expansion of a plurality of BRAM modules can be conveniently and rapidly realized by utilizing the local series module built in the FPGA, and the FIFO function can be expanded and formed.

Drawings

Fig. 1 is a schematic diagram of a signal transmission path of an address signal Addr in a conventional FPGA fanned out to two BRAM modules via a wire-wrapped architecture.

Fig. 2 is a schematic diagram of a signal transmission path of an address signal Addr in an FPGA fanned out to two BRAM modules implementing width expansion via a built-in local serial module in one embodiment of the present application.

Fig. 3 is a schematic diagram of a signal transmission path of a Data signal Data in an FPGA fanned out to four BRAM modules implementing depth expansion via a built-in local serial module in one embodiment of the present application.

Fig. 4 is a schematic diagram of a signal transmission path of a FIFO controller configured by a built-in local serial module and two BRAM modules for implementing width expansion according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application refers to the accompanying drawings.

The application discloses utilize built-in local tandem module to realize FPGA of module signal sharing, this FPGA is the same with conventional FPGA framework, and inside includes all kinds of resource modules and wire winding framework, and the resource module can be arranged according to determinant framework according to common mode, and every resource module includes a plurality of port, thereby each port of resource module inserts wire winding framework respectively and realizes communication interconnection.

On the basis, the FPGA of the application is also provided with a local series module (BOX module) through a newly added hardware resource, and the local series module comprises at least one local interconnection line which is connected with a local control switch in series. Each local interconnection line is respectively connected with a plurality of sharing ports belonging to the same signal sharing group, a local control switch N1 is arranged between every two adjacent sharing ports, each sharing port is a port of a preset resource module, and the preset resource module is a resource module which needs to realize module signal sharing in the FPGA. In one embodiment, there are a plurality of shared ports belonging to the same predetermined resource module in the same signal sharing group, but in another embodiment, more commonly, a plurality of shared ports in the same signal sharing group respectively belong to a plurality of predetermined resource modules, and further, the plurality of predetermined resource modules are identical, and the same ports in a plurality of identical predetermined resource modules respectively form a signal sharing group as shared ports, for example, the enable ports EN in a plurality of identical BRAM modules respectively form a signal sharing group as shared ports, and the signal sharing group includes the enable ports EN belonging to different BRAM modules. The reason is that multiple identical resource modules are generally obtained by copying the same resource module during design, and have the same layout design, so that the identical ports in the multiple identical resource modules occupy the metal wire Track at the same position, and at this time, the implementation of the local series module only needs to add one local control switch N1 between two adjacent shared ports, which is relatively low in implementation cost.

Based on the framework, the configuration bits are used for controlling the conduction of the local control switches on the local interconnection lines, so that the multiple sharing ports in the same signal sharing group realize signal transmission through the local interconnection lines without passing through a winding framework, the wiring congestion can be reduced, and the wiring rate is improved. In an embodiment, the signal transmission implemented by the multiple shared ports in the same signal sharing group through the local interconnection line includes that the same signal is input into the local series module and shared to other shared ports through the local interconnection line, that is, the same signal is simultaneously fanned out to the shared ports in the multiple predetermined resource modules through the local series module, so that the multiple predetermined resource modules share the same signal, which is a common application scenario in an FPGA application process, and typically, when the multiple BRAM modules are subjected to width expansion or depth expansion to form a large-capacity RAM, part of the same ports of the multiple BRAM modules need to share the same signal. In other scenarios, the transmitting of signals by the plurality of shared ports in the signal-sharing group through the local interconnect line further includes transmitting, by one shared port in the signal-sharing group, signals to other shared ports in the signal-sharing group through the local interconnect line.

Taking the case of implementing a width expansion function on two BRAM modules with a maximum capacity of 1024x32 and obtaining a RAM with a capacity of 1024x64 as an example, please compare fig. 1 and fig. 2, this embodiment compares the implementation method of a conventional FPGA with the implementation method of the present application using a local serial module as follows, since the read end and the write end of a BRAM module are similar, this example only takes the write end of a BRAM module as an example. In implementing the width expansion function, it is necessary to fan out a clock signal to the clock ports WCLK of the two BRAM modules at the same time, fan out an enable signal to the enable ports EN of the two BRAM modules at the same time, fan out a control signal to the control ports WEN of the two BRAM modules at the same time, fan out an address signal to the address ports WA [ 9. In order to implement the width expansion function, the clock signal, the enable signal, the control signal and the address signal need to be fanned out to two BRAM modules, wherein the clock signal is more specific, and is generally fanned out to the two BRAM modules through the same clock tree to reduce clock skew, so the clock signal is generally not connected through a wire winding framework, and the clock signal is not considered in the following application.

For other enable signals, control signals and address signals which need to be fanned out to two BRAM modules, taking address signal Addr as an example, as shown in fig. 1, in a conventional FPGA, a signal source of address signal Addr needs to be fanned out to IP1 and IP2 of a wire-wound architecture simultaneously via the wire-wound architecture, a schematic diagram of fanning out address signal Addr to IP1 and IP2 is shown in fig. 1 by using a dotted line only, which is not a straight line trace as shown in fig. 1, and is generally a more complex trace structure, so that address signal Addr can be connected to address port WA [9 0] of BRAM1 through IP1 of INT1, and simultaneously connected to address port WA [9 ] 0] of BRAM2 through IP2 of INT2, and a signal transmission path is shown by an arrow in fig. 1. In addition to the address signal Addr, both the enable signal and the control signal need to be fanned out to two BRAMs through the winding structure, in practical cases, more BRAMs are used for expansion, and the same signal needs to be fanned out to more BRAMs through the winding structure, so that as described in the background section, the requirement for wiring resources is large, wiring congestion is easily caused, and the routing rate is reduced. And the distances between the IP1 and the IP2 of the winding architecture are large, especially when a large RAM is composed of a plurality of BRAM modules, the BRAM modules are usually arranged in the FPGA to form a column, and the plurality of BRAM modules are arranged up and down, so that the occupied height is large, the signal connection needs to occupy more wiring resources, a longer winding path is taken, the wiring resource pressure is increased, and meanwhile, the path delay is increased.

However, according to the FPGA of the present application, as shown in fig. 2, the address port WA [ 9. The other signals that BRAM1 and BRAM2 need to share are also similar, and the same is true when there are more BRAM modules to implement the extension. Because the branch line is not required to be connected to the BRAM2 through the IP2, the wiring requirement is reduced, the wiring elasticity is increased, the wiring process is more favorably realized, and the path delay is favorably reduced. When there are more BRAM modules to implement function extension, such an optimization effect is more obvious, for example, fig. 4 shows a connection diagram of a large-capacity RAM formed by extending four BRAM modules in another example, in a conventional FPGA, data signals Data need to be respectively connected to INT1, INT2, INT3, INT4 and then input into Data ports WD [31 [ 0] of the four BRAM modules, whereas in the FPGA of the present application, the Data signals Data are connected to the Data ports WD [31 ] of BRAM1 through INT1 and transmitted to the Data ports WD [31 ] of BRAM2, BRAM3, BRAM4 through local interconnect lines L4, and a signal transmission path is shown by an arrow in fig. 3.

When signal sharing is not needed, the configuration bits are used for controlling local control switches on the local interconnection lines to be turned off, and the multiple sharing ports in the same signal sharing group respectively achieve respective signal transmission through the winding framework. That is, for example, as in fig. 2, when there is no RAM expansion requirement, by controlling the local control switch N1 to turn off, the two BRAM modules are respectively connected to the winding architecture for independent use and are not connected to each other, and the conventional use of the two BRAM modules is not affected.

Based on the architecture of the local series modules and the functions realized by the architecture, one or more local series modules are built in the FPGA, and each local series module is respectively arranged between the corresponding preset resource module and the winding architecture. Each local series module comprises one or more local interconnection lines, and each local interconnection line is used for connecting different signal sharing groups.

Based on the above example, it can also be seen that each predetermined resource module may have only one port as a shared port to be connected to the local interconnect line corresponding to the signal sharing group to which the predetermined resource module belongs, or each predetermined resource module has multiple ports to be respectively connected to the local interconnect lines corresponding to the respective shared ports in different signal sharing groups, for example, in fig. 2, the control port address port WA [ 9. In practical implementation, different local interconnection lines connected to different ports of one predetermined resource module may belong to different local series modules, or may belong to the same local series module. It is common that a plurality of local interconnection lines connected to different ports of one predetermined resource module belong to the same local series module, and the local series module is disposed between the corresponding connected predetermined resource modules and the winding framework, for example, in fig. 2, the local interconnection lines L1, L2, and L3 belong to the same local series module.

The above example takes a case where one local interconnection line is connected to two sharing ports as an example, but there is no such limitation in practical implementation, one local interconnection line may be connected to a plurality of sharing ports, and one local control switch N1 is respectively disposed between any two adjacent sharing ports. Then, when one local interconnect connects to the shared port in the multiple predetermined resource modules, the distance between the layout positions of the multiple predetermined resource modules does not exceed a predetermined distance, for example, the layout positions of the multiple predetermined resource modules are usually adjacent, or are in diagonal layout positions, etc., so that the local series implemented by the local interconnect is closer to each other, and does not occupy too much area.

When the number of the shared ports in the same signal sharing group is less than a preset threshold value, the local control switch N1 on the local interconnection line connected with the shared ports in the signal sharing group is realized by adopting an NMOS tube, a transmission gate or a bidirectional three-state buffer. When the number of the shared ports in the same signal sharing group reaches a preset threshold value, the local control switch on the local interconnection line connected with the shared ports in the signal sharing group is realized by adopting a bidirectional tri-state buffer, so that the problem of delay increase when signal sharing is carried out through the local interconnection line can be avoided.

When more than two sharing ports are connected to one local interconnection line, all local control switches on the same local interconnection line can be controlled to be conducted through the configuration bits, and therefore all sharing ports in the same signal sharing group can achieve signal transmission through the local interconnection lines. Or the configuration bits can control the conduction of part of local control switches on the local interconnection lines and the disconnection of other part of local control switches, so that part of shared ports in the same signal sharing group realize signal transmission through the local interconnection lines, and other part of shared ports realize signal transmission through the wire winding framework respectively. For example, in the example shown in fig. 3, the local interconnect L4 is connected to the data ports WD [31 [ 0] of four BRAM modules, and in application, the configuration bits can control the three local control switches N1 to be turned on, so that the data ports WD [31 ] of the four BRAM modules can all implement signal transmission through the local interconnect L4, and the four BRAM modules can be used to form a large-capacity RAM by extension. Or only the local control switch N1 between BRAM1 and BRAM2 can be controlled to be turned on through the configuration bit, the local control switches N1 between BRAM2 and BRAM3 and between BRAM3 and BRAM4 are kept to be turned off, at the moment, only the data ports WD [ 31.

As shown in the foregoing examples of fig. 2 and fig. 3, when the local serial module built in the FPGA of the present application is used to implement module signal sharing, a common application is to implement capacity expansion of the BRAM module, that is, when a plurality of shared ports of the same signal sharing group belong to a plurality of BRAM modules respectively, and a local control switch on a local interconnection line in the local serial module is controlled to be turned on by a configuration bit, when the plurality of BRAM modules implement a width expansion function or a depth expansion function through the local serial module.

1. The method realizes the width expansion function of a plurality of BRAM modules, namely realizes the RAM with large data bit width by utilizing a plurality of BRAM modules with small data bit width.

In this case, the address ports of the plurality of BRAM modules constitute a signal share group and are connected to the first local interconnect line L1, the enable ports of the plurality of BRAM modules constitute a signal share group and are connected to the second local interconnect line L2, and the control ports of the plurality of BRAM modules constitute a signal share group and are connected to the third local interconnect line L3, as shown in fig. 2.

Local control switches on three local interconnection lines connected with the plurality of BRAM modules are controlled to be conducted through the configuration bits, and address signals are shared to address ports of the BRAM modules through the first local interconnection line L1. The enabling signal is input through a wiring of the wire winding framework and one of the enabling ports and is shared to the enabling port of each BRAM module through the second local interconnection line. And the control signals are shared to the control port of each BRAM module through the third local interconnection line. And the data ports of the plurality of BRAM modules respectively acquire data signals through the winding architecture.

That is, the address signal, the enable signal, the control signal and the clock signal are shared, and the data signal is separated and independent, so that the plurality of BRAM modules realize the width expansion function, and the writing end and the reading end are applicable.

2. The method realizes the deep expansion function of a plurality of BRAM modules, namely realizes the RAM with large address bit width by utilizing a plurality of BRAM modules with small address bit width.

In this case, the data ports of the plurality of BRAM modules constitute a signal share group and are connected to the fourth local interconnect line L4, the address ports of the plurality of BRAM modules constitute a signal share group and are connected to the fifth local interconnect line L5, and the control ports of the plurality of BRAM modules constitute a signal share group and are connected to the sixth local interconnect line L6, as shown in fig. 3.

And local control switches on three local interconnection lines connected with the plurality of BRAM modules are controlled to be conducted through the configuration bits. The data signal is input through the wiring structure and the connection line of one control port, and is shared to the data port of each BRAM module through the fourth local interconnection line L4. The control signal is shared to the control port of each BRAM module through the sixth local interconnection line L6. And partial signal bits of the address signals are shared to the address ports of the BRAM modules through a fifth local interconnection line L5, and the enabling ports of the BRAM modules respectively acquire the rest signal bits of the address signals through a winding framework.

That is, part of signal bits of the address signal, the control signal, the data signal and the clock signal are shared, and the enabling signals are separated and independent, so that the plurality of BRAM modules realize the depth expansion function, and the write-in end and the read-out end are both applicable. For example, taking two BRAM modules to implement depth extension, the lower 10 bits Addr [9 ] of the address signal are shared with BRAM1 and BRAM2, the highest bit Addr [10] of the address signal is used as an enable signal, and when Addr [10] =0, the enable signal of BRAM1 is valid; when Addr [10] =1, the enable signal of BRAM2 is effective, so that a RAM with capacity of 2048x32 can be formed by performing depth expansion by using two BRAM modules with capacity of 1024x 32.

In both the above-described case of width expansion and the case of depth expansion, the address signals and control signals shared to the individual BRAM modules via the local interconnect have two sources: (1) The address and control signals shared to the various BRAM modules via local interconnect lines are both input by the wire-wound architecture, as shown in fig. 2 and 3. Or, (2) the address signals and the control signals shared to the various BRAM modules via the local interconnection lines are both input by the FIFO controller.

The configuration of the FIFO is another common application of the BRAM modules, and at this time, a FIFO controller is required, and the FIFO controller can output control signals and address signals required for reading and writing the corresponding BRAM modules in the FIFO mode, so that the FIFO function can be realized. Based on the framework of the application, address signals and control signals generated by one FIFO controller can be fanned out to a plurality of BRAMs through local interconnection lines, and the plurality of BRAMs are subjected to width expansion or depth expansion, so that a FIFO with larger capacity can be realized by using the FIFO controller to combine a plurality of BRAM modules.

As shown in fig. 4, the wire-wound architecture and FIFO controller is connected to two inputs of MUX1, an output of MUX1 is connected to a first local interconnect line L1, the wire-wound architecture and FIFO controller is connected to two inputs of MUX2, and an output of MUX2 is connected to a third local interconnect line L3. The address signals and control signals from the wire-wound architecture can be selected to be shared to BRAM1 and BRAM2 by controlling MUX1 and MUX 2. Or the address signal and the control signal from the FIFO controller can be selected to be shared to BRAM1 and BRAM2 by controlling MUX1 and MUX2, thereby realizing FIFO with larger capacity.

Claims (10)

1. An FPGA for realizing module signal sharing by utilizing a built-in local serial module is characterized in that the FPGA is internally provided with the local serial module, the local serial module comprises at least one local interconnection line connected with a local control switch in series, each local interconnection line is respectively connected with a plurality of sharing ports belonging to the same signal sharing group, one local control switch is arranged between every two adjacent sharing ports, and each sharing port is a port of a preset resource module;

controlling a local control switch on a local interconnection line to be conducted through a configuration bit, and realizing signal transmission through the local interconnection line by a plurality of sharing ports in the same signal sharing group; or the configuration bit controls the local control switch on the local interconnection line to be turned off, and the plurality of sharing ports in the same signal sharing group respectively realize respective signal transmission through the wire winding framework.

2. The FPGA according to claim 1, wherein the plurality of shared ports in the same signal sharing group belong to a plurality of predetermined resource modules respectively, and the distance between the layout positions of the plurality of predetermined resource modules does not exceed a predetermined distance.

3. The FPGA of claim 1 wherein when a local control switch on a local interconnect is controlled to be conductive by a configuration bit, the same signal is input to said local series module and shared to each of the other shared ports by the local interconnect.

4. The FPGA as claimed in claim 1, wherein the shared ports of the same signal sharing group belong to a plurality of BRAM modules respectively, and when the configuration bits control the conduction of local control switches on local interconnection lines in the local series modules, the BRAM modules realize a width expansion function or a depth expansion function through the local series modules.

5. The FPGA of claim 4, wherein address ports of a plurality of BRAM modules form a signal sharing group and are connected with a first local interconnection line, enable ports of the plurality of BRAM modules form a signal sharing group and are connected with a second local interconnection line, and control ports of the plurality of BRAM modules form a signal sharing group and are connected with a third local interconnection line;

local control switches on three local interconnection lines connected with the plurality of BRAM modules are controlled to be conducted through a configuration bit, and address signals are shared to address ports of the BRAM modules through the first local interconnection line; enabling signals are input through a connection line of the wire winding framework and one of the enabling ports and are shared to the enabling port of each BRAM module through the second local interconnection line; control signals are shared to the control port of each BRAM module through the third local interconnection line; and the data ports of the plurality of BRAM modules respectively acquire data signals through a wire-winding architecture, and the plurality of BRAM modules realize the width expansion function.

6. The FPGA of claim 4, wherein the data ports of a plurality of BRAM modules form a signal sharing group and are connected with a fourth local interconnection line, the address ports of the plurality of BRAM modules form a signal sharing group and are connected with a fifth local interconnection line, and the control ports of the plurality of BRAM modules form a signal sharing group and are connected with a sixth local interconnection line;

the local control switches on the three local interconnection lines connected with the plurality of BRAM modules are controlled to be conducted through the configuration bits, and data signals are input through a connection line of the winding framework and one control port and are shared to the data port of each BRAM module through the fourth local interconnection line; control signals are shared to the control port of each BRAM module through the sixth local interconnection line; and partial signal bits of the address signals are shared to the address ports of the BRAM modules through the fifth local interconnection line, the enabling ports of the BRAM modules respectively obtain the rest signal bits of the address signals through a wire winding framework, and the BRAM modules realize a deep expansion function.

7. The FPGA of claim 5 or 6, wherein the address signals and control signals shared to each BRAM module via local interconnect lines are input by a wire-wound architecture; alternatively, the address signals and control signals shared to the various BRAM modules via the local interconnect are both input by the FIFO controller.

8. The FPGA of claim 1,

when the number of the shared ports in the same signal sharing group is less than a preset threshold value, the local control switch on the local interconnection line connected with the shared ports in the signal sharing group is realized by adopting an NMOS (N-channel metal oxide semiconductor) tube, a transmission gate or a bidirectional three-state buffer;

and when the number of the shared ports in the same signal sharing group reaches the preset threshold value, the local control switch on the local interconnection line connected with the shared ports in the signal sharing group is realized by adopting a bidirectional three-state buffer.

9. The FPGA of claim 1, wherein one or more local tandem modules are built into the FPGA, and each local tandem module is respectively disposed between a respective predetermined resource module and a winding architecture; each local series module comprises one or more local interconnection lines, and each local interconnection line is used for connecting different signal sharing groups.

10. The FPGA of claim 1, wherein when applied, the FPGA controls all local control switches on a local interconnection line to be turned on through a configuration bit, so that all sharing ports in the same signal sharing group realize signal transmission through the local interconnection line; or the configuration bits control the conduction of part of local control switches on the local interconnection lines and the disconnection of other part of local control switches, so that part of shared ports in the same signal sharing group realize signal transmission through the local interconnection lines, and other part of shared ports realize signal transmission through the wire winding framework respectively.

Images