CN115685126A

CN115685126A - Direction-of-arrival calculation method, device, equipment and storage medium

Info

Publication number: CN115685126A
Application number: CN202211384717.1A
Authority: CN
Inventors: 轩阳; 刘黛琳; 王震; 龙超
Original assignee: China Automotive Innovation Co Ltd
Current assignee: China Automotive Innovation Co Ltd
Priority date: 2022-11-07
Filing date: 2022-11-07
Publication date: 2023-02-03

Abstract

The application discloses a method, a device, equipment and a storage medium for calculating a direction of arrival, which are interactively completed by using a logic end and a system end of a system on chip, wherein the logic end reads azimuth array element data and pitch array element data from the system end under the condition of acquiring a first interrupt signal, and respectively carries out independent parallel operation on the azimuth array element data and the pitch array element data to generate an independent parallel operation result and a second interrupt signal for the system end to read, and the system end is used for carrying out multi-core direction of arrival calculation on the independent parallel operation result and determining the direction of arrival of a target object. The method and the device utilize the characteristic that the logic end can perform parallel operation, the logic end performs operation on the azimuth array element data and the pitch array element data simultaneously, and utilize the characteristic that the system end has multiple cores, and perform direction-of-arrival calculation on independent parallel operation results of different target objects simultaneously, so that the time for calculating the direction-of-arrival is greatly shortened, and the efficiency for calculating the direction-of-arrival is improved.

Description

Direction-of-arrival calculation method, device, equipment and storage medium

Technical Field

The present application relates to the field of radar imaging, and in particular, to a method, an apparatus, a device, and a storage medium for calculating a direction of arrival.

Background

When 4-dimensional radar imaging design is carried out, long-time operation is usually consumed for estimating the direction of arrival, and when the number of targets is too large, the time for calculating the direction of arrival is exponentially increased, so that the calculation time is long, and the operation efficiency is low. Therefore, a method capable of improving the calculation efficiency of the direction of arrival is needed.

Disclosure of Invention

In order to solve at least one technical problem, shorten the time of direction of arrival calculation and improve the operating efficiency, the application provides a direction of arrival calculation method, device, equipment and storage medium.

According to an aspect of the disclosure, a method for calculating a direction of arrival is provided, where the method is applied to a logic side of a system on chip, and the method includes:

under the condition of acquiring a first interrupt signal, reading array element data from a system end, wherein the array element data comprises azimuth array element data and elevation array element data, the system end is used for carrying out array element reconstruction on position information data of at least one target object and acquiring the array element data and the first interrupt signal, and the first interrupt signal represents that the logic end is allowed to read the array element data;

performing independent parallel operation on the azimuth array element data and the elevation array element data to obtain an independent parallel operation result and a second interrupt signal, wherein the second interrupt signal represents that the system end is allowed to read the independent parallel operation result;

and storing the independent parallel operation result into a first memory for the system end to read, wherein the system end is also used for carrying out multi-core DOA calculation based on the independent parallel operation result.

In some possible embodiments, the first interrupt signal includes a first azimuth interrupt signal and a first pitch interrupt signal, and the method includes:

the reading of the array element data from the system end under the condition of acquiring the first interrupt signal includes:

reading the azimuth array element data under the condition of acquiring the first azimuth interrupt signal;

and under the condition of acquiring the first pitching interrupt signal, reading the pitching array metadata.

In some possible embodiments, the independent parallel operation result includes an azimuth operation result and a pitch bit operation result, the second interrupt signal includes a second azimuth interrupt signal and a second pitch interrupt signal, and the method includes:

the above-mentioned independent parallel operation to above-mentioned azimuth array element data and above-mentioned every single move array element data, obtain independent parallel operation result and second interrupt signal, include:

under the condition that the azimuth array element data are read, carrying out azimuth independent parallel operation on the azimuth array element data to obtain an azimuth operation result and the second azimuth interrupt signal;

and under the condition that the pitching array element data are read, performing independent pitching parallel operation on the pitching array element data to obtain the pitching operation result and the second pitching interrupt signal.

In some possible embodiments, the logic end includes at least two operation cores, and the performing independent parallel operations on the azimuth array element data and the elevation array element data includes:

and distributing the array element data to different operation cores to perform independent parallel operation based on the type of the array element data and the number of the operation cores.

According to a second aspect of the present disclosure, there is provided a method for calculating a direction of arrival, the method being applied to a system side of a system on chip, the method including:

carrying out array element reconstruction on position information data of at least one target object to obtain array element data and a first interrupt signal, wherein the first interrupt signal represents that a logic end is allowed to read the array element data;

storing the array element data into a second memory for being read by the logic end, wherein the logic end is used for carrying out independent parallel operation on the array element data and obtaining an independent parallel operation result and a second interrupt signal, and the second interrupt signal represents that the system end is allowed to read the independent parallel operation result;

reading the independent parallel operation result under the condition of acquiring the second interrupt signal;

and performing multi-kernel DOA calculation on the independent parallel operation result to obtain a point cloud image representing the DOA.

In some possible embodiments, the system side includes at least two operation cores, and the performing multi-core radar computation on the independent parallel operation result includes:

and distributing the independent parallel operation results to different operation cores according to the number of the operation cores to perform multi-core DOA calculation.

In some possible embodiments, the second interrupt signal includes a second azimuth interrupt signal and a second pitch interrupt signal, the independent parallel operation result includes an azimuth operation result and a pitch operation result, and the method includes:

the reading of the independent parallel operation result when the second interrupt signal is acquired includes:

reading the azimuth operation result under the condition of acquiring the second azimuth interrupt signal;

and reading the pitching operation result when the second pitching interrupt signal is acquired.

In some possible embodiments, the performing multi-kernel DOA computation on the independent parallel operation result to obtain a point cloud image representing a DOA includes:

under the condition that the azimuth calculation result is read, calculating at least one azimuth angle based on the azimuth calculation result;

under the condition that the pitching operation result is read, calculating at least one pitching angle based on the pitching operation result;

and carrying out angle matching based on the azimuth angle and the pitch angle to obtain the point cloud image.

In some possible embodiments, the performing angle matching based on the azimuth angle and the pitch angle to obtain the point cloud image includes:

determining an azimuth angle and a pitch angle corresponding to each target object respectively;

and obtaining a corresponding point cloud image of the target object based on the azimuth angle and the pitch angle.

According to a third aspect of the present disclosure, there is provided a direction of arrival calculation apparatus, which is applied to a logic terminal of a system on chip, the apparatus including:

an array element reading module, configured to read array element data from a system end under a condition that a first interrupt signal is obtained, where the array element data includes azimuth array element data and pitch array element data, the system end is configured to perform array element reconstruction on position information data of at least one target object, and obtain the array element data and the first interrupt signal, and the first interrupt signal represents that the logic end is allowed to read the array element data;

an independent parallel operation module, configured to perform independent parallel operation on the azimuth array element data and the pitch array element data to obtain an independent parallel operation result and a second interrupt signal, where the second interrupt signal represents an instruction that allows the system side to read the independent parallel operation result;

and the system end is also used for carrying out multi-core wave reaching calculation based on the independent parallel operation result.

According to a fourth aspect of the present disclosure, there is provided a direction of arrival calculation apparatus, which is applied to a system side of a system on chip, the apparatus including:

the array element reconstruction module is used for performing array element reconstruction on position information data of at least one target object to obtain array element data and a first interrupt signal, and the first interrupt signal represents that a logic end is allowed to read the array element data;

a second storage module, configured to store the array element data in a second memory for the logic end to read, where the logic end is configured to perform independent parallel operation on the array element data and obtain an independent parallel operation result and a second interrupt signal, and the second interrupt signal indicates that the system end is allowed to read the independent parallel operation result;

an operation result reading module, configured to read the independent parallel operation result when the second interrupt signal is obtained;

and the multinuclear DOA calculation module is used for carrying out multinuclear DOA calculation on the independent parallel operation result to obtain a point cloud image representing the DOA.

According to a fifth aspect of the present disclosure, there is provided a direction of arrival computing apparatus, the apparatus comprising a processor and a memory, the memory having at least one instruction or at least one program stored therein, the at least one instruction or the at least one program being loaded and executed by the processor to implement one of the above-mentioned direction of arrival computing methods.

According to a sixth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement a direction of arrival calculation method as described above.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

The application has the following beneficial effects:

when the FPGA on-chip system is used for carrying out 4-dimensional radar imaging design, the direction-of-arrival estimation module is often at the PS end, namely the system end of the application, and the system end is carried out in a complete serial mode, the array element data of the pitch dimension and the array element data of the azimuth dimension cannot be operated simultaneously, so that the calculation efficiency of the direction-of-arrival is low, the PS end (the system end) and the PL end (the logic end) of the FPGA on-chip system are adopted for interaction, the characteristic that an IP core in the PL end can be operated in parallel is utilized, the parallel operation is carried out on the array element data of the pitch dimension and the array element data of the azimuth, so that the array element data of the pitch dimension and the array element data of the azimuth can be operated simultaneously, the operation efficiency of the IP core of the PL end is higher than that of the PS end, and the time for data operation is greatly shortened.

And because a plurality of operation cores exist in the PS end, the PL end can write the result generated after parallel operation into the memory and read by the PS end, and the parallel operation result is divided into different cores to simultaneously perform angle calculation and angle matching by utilizing the characteristic of multi-core, so that the operation efficiency of the direction of arrival calculation is improved, and the time for calculation is shortened.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic flowchart illustrating a method for calculating a direction of arrival at a logic terminal according to an embodiment of the present application;

FIG. 2 is a diagram illustrating a first interrupt signal read scenario in an embodiment of the present application;

FIG. 3 is a schematic diagram of independent parallel operations according to an embodiment of the present application;

FIG. 4 is a schematic diagram illustrating a logic-side multi-target independent parallel operation according to an embodiment of the present application;

fig. 5 is a schematic flow chart illustrating a method for calculating a direction of arrival at a system end according to an embodiment of the present application;

FIG. 6 is a flow diagram of a logic side read data state machine according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a system-side direction of arrival calculation according to an embodiment of the present application;

FIG. 8 is a diagram illustrating a second interrupt signal read scenario according to an embodiment of the present application;

FIG. 9 illustrates a schematic diagram of a multi-core direction of arrival calculation according to an embodiment of the present application;

FIG. 10 is a schematic flow chart illustrating an angle matching method according to an embodiment of the present application;

FIG. 11 is a block diagram of a logical side direction of arrival computing apparatus according to an embodiment of the present application;

fig. 12 is a block diagram of a system-side direction-of-arrival calculation apparatus according to an embodiment of the present application;

fig. 13 is a block diagram showing a first structure of an electronic device according to an embodiment of the present application;

fig. 14 shows a block diagram of a second electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only a part of the embodiments of the present specification, and not all of the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present description without making any creative effort belong to the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of a, B, C, and may mean including any one or more elements selected from the group consisting of a, B, and C.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present application.

According to an aspect of the present disclosure, a method for calculating a direction of arrival is provided, please refer to fig. 1, where fig. 1 is a schematic flow chart illustrating a method for calculating a direction of arrival at a logic terminal according to an embodiment of the present disclosure, where the method is applied to a logic terminal of a system on chip, and the method includes:

step S101: under the condition of acquiring a first interrupt signal, reading array element data from a system end, wherein the array element data comprises azimuth array element data and elevation array element data, the system end is used for carrying out array element reconstruction on position information data of at least one target object and acquiring the array element data and the first interrupt signal, and the first interrupt signal represents that the logic end is allowed to read the array element data;

step S102: performing independent parallel operation on the azimuth array element data and the elevation array element data to obtain an independent parallel operation result and a second interrupt signal, wherein the second interrupt signal represents that the system end is allowed to read the independent parallel operation result;

step S103: and storing the independent parallel operation result into a first memory for the system end to read, wherein the system end is also used for carrying out multi-core DOA calculation based on the independent parallel operation result.

In the embodiment of the application, when a PL (logic) end reads a first interrupt signal in a memory, array element data is continuously read from the memory, wherein the array element data includes two-dimensional array element data, which is usually obtained by reconstructing an array element after radar two-dimensional constant false alarm rate acquisition, namely, azimuth array element data and pitch array element data, and after the two kinds of data are read, two kinds of array element data are independently and concurrently operated, that is, FFT (fourier transform operation) synthesis digital beams can be simultaneously performed on the pitch array element data and the azimuth array element data.

In a specific embodiment, in a conventional manner, a PS terminal (system terminal) is generally used to perform FFT on the pitch array element data and the azimuth array element data, but the PS terminal can only perform serial operation, and the pitch array element data and the azimuth array element data cannot be simultaneously subjected to FFT, in the conventional manner, for example, the time required for performing FFT on the azimuth array element data of a target is T11, the time required for performing FFT on the pitch array element data of the target is T12, and then the time required for performing FFT on the two data of a target using the conventional manner is T11+ T12.

In another specific embodiment, the FFT of the pitch array element data and the azimuth array element data by using the PL side (logic side) in the present application has the advantage that the IP core in the PL side can perform parallel operation, if the time required for performing the FFT of the azimuth array element data of a target at the PL side is T21, the time required for performing the FFT of the pitch array element data of the target at the PL side is T22, because the number of the pitch array element data is small, the used operation time is also short, compared with the conventional mode, T11> T12 and T21> T22 can be obtained, and because the operation efficiency of the PL side is higher than that of the PS side, T11> T21, because the PL side can perform parallel operation, the time for performing the FFT operation of the pitch array element data can be completely covered by the time for performing the FFT operation of the azimuth array element data, the shortest time for completing the FFT of both data is T21, which obviously saves much time compared with the FFT in the conventional mode.

In one embodiment, please refer to fig. 2, fig. 2 is a schematic diagram illustrating a first interrupt signal read situation according to an embodiment of the present application, where the first interrupt signal includes a first azimuth interrupt signal and a first elevation interrupt signal, and the method includes:

the reading of the array element data from the system side under the condition of acquiring the first interrupt signal includes:

reading the azimuth array metadata under the condition of acquiring the first azimuth interrupt signal;

In the embodiment of the application, the array element data with different dimensions correspond to different interrupt signals, and when the PL end reads one of the interrupt signals corresponding to the array element data, the PL end can directly read the corresponding array element data to perform subsequent operations, so that the time for calculating the direction of arrival is saved, and the time for calculating the direction of arrival is shortened to the maximum efficiency.

It can be understood that the first interrupt signal indicates that the PL side can read the array element data from the memory, and also indicates that the PS side has completed the array element reconstruction of the corresponding data, and writes the corresponding array element data into the memory for the PL side to read.

In a specific embodiment, if the PL end reads the first azimuth interrupt signal from the memory but does not read the first pitch interrupt signal, it means that the PS end has completed the reconstruction of the array elements of the azimuth array element data and writes the array elements into the memory, but has not completed the reconstruction of the array elements of the pitch array element data, and at this time, the PL end may read the azimuth array element data first to perform the subsequent FFT. Similarly, if the PL reads the first pitch interrupt signal but does not read the first azimuth interrupt signal, the PL may read the pitch array metadata in advance for the subsequent FFT.

In another specific embodiment, the PL end comprises two modules, namely an azimuth module and a pitch module, wherein the azimuth module is responsible for reading the first azimuth interrupt signal and reading azimuth array element data for subsequent operation under the condition of reading the first azimuth interrupt signal; and the pitching module is responsible for reading the first pitching interrupt signal and reading the pitching array metadata for subsequent operation under the condition that the first pitching interrupt signal is read.

In one embodiment, referring to fig. 3, fig. 3 shows a schematic diagram of independent parallel operations according to an embodiment of the present application, where the independent parallel operation result includes an azimuth operation result and a pitch bit operation result, and the second interrupt signal includes a second azimuth interrupt signal and a second pitch interrupt signal, and the method includes:

and under the condition that the pitching array element data are read, independently and parallelly performing pitching operation on the pitching array element data to obtain a pitching operation result and the second pitching interrupt signal.

In the embodiment of the application, the FFT of the azimuth array element data and the FFT of the pitch array element data are two mutually independent operation processes, which are not affected by each other, in order to minimize the time in each step of the calculation of the direction of arrival, if the PL end reads only one of the array element data, the FFT of the array element data can be performed in advance, and the time for waiting for the other array element data is saved.

In a specific embodiment, if the PL end only reads the azimuth array element data but not the elevation array element data, the PL end directly performs FFT on the azimuth array element data; similarly, if the PL end only reads the pitching array element data but not reads the azimuth array element data, the FFT is directly carried out on the pitching array element data; if the PL end reads the azimuth array element data and the elevation array element data at the same time, FFT is carried out on the azimuth array element data and the elevation array element data at the same time.

In another specific embodiment, the PL end includes two modules, namely an azimuth module and a pitch module, and the reading and the operation of the azimuth array element data are completed in the azimuth module, for example, after the azimuth module reads the first azimuth interrupt signal, the azimuth array element data are continuously read, and the FFT is performed on the azimuth array element data; similarly, the reading and the operation of the related pitching array element data are completed in the pitching module.

In an embodiment, please refer to fig. 4, fig. 4 is a schematic diagram illustrating a logic-side multi-target independent parallel operation according to an embodiment of the present application, where the logic side includes at least two operation cores, and the performing independent parallel operation on the azimuth array element data and the elevation array element data includes:

In the embodiment of the present application, DDR _ WR indicates writing data into the memory and DDR _ RD indicates reading data from the memory in fig. 4. Because there are at least two array element data and the two array element data are independently operated in parallel, at least two operation cores are needed to complete the parallel operation of the two array element data. In the calculation of the direction of arrival of the multi-target object, more operation cores can be arranged, and the different operation cores are used for calculating the direction of arrival of different target objects, so that the calculation time can be shortened.

In a specific embodiment, the PL end comprises two operation cores, the two operation cores are respectively responsible for the FFT of the azimuth array element data and the FFT of the pitch array element data, and the two operation cores operate independently and do not affect each other. Referring to fig. 4, fig. 4 shows a schematic diagram of independent parallel operation of multiple logical end targets in the embodiment of the present application, where each target has corresponding azimuth array element data and pitch array element data, two operation cores perform parallel FFT on the azimuth array element data and pitch array element data of target 1 respectively and simultaneously, and perform FFT on the azimuth array element data and pitch array element data of target 2, target 3, and target 4 sequentially.

In another specific embodiment, the PL side includes 4 operation cores, and in the case that there are multiple target objects, for example, there are 4 target objects, the array element data of the target objects may be first allocated, for example, the azimuth array element data of the target 1 and the target 2 are allocated to the operation core1, the pitch array element data of the target 1 and the target 2 are allocated to the operation core2, the azimuth array element data of the target 3 and the target 4 are allocated to the operation core3, and the pitch array element data of the target 3 and the target 4 are allocated to the operation core 4. The first operation stage: the operation core1 performs FFT on the azimuth array element data of the target 1, the operation core2 performs FFT on the pitch array element data of the target 1, the operation core3 performs FFT on the azimuth array element data of the target 3, and the operation core 4 performs FFT on the pitch array element data of the target 3; and a second operation stage: the operation core1 performs FFT on the azimuth array element data of the target 2, the operation core2 performs FFT on the pitch array element data of the target 2, the operation core3 performs FFT on the azimuth array element data of the target 4, and the operation core 4 performs FFT on the pitch array element data of the target 4; each computational core corresponds to two computational phases, and if a certain computational core completes the first computational phase, the second computational phase can be directly performed, for example, the computational core1 completes the FFT of the azimuth array element data of the target 1, and the computational core1 starts the FFT of the azimuth array element data of the target 2 regardless of whether other computational cores complete or not.

According to a second aspect of the present disclosure, a method for calculating a direction of arrival is provided, please refer to fig. 5, fig. 6, and fig. 7, where fig. 5 illustrates a schematic flow diagram of a method for calculating a direction of arrival at a system side in an embodiment of the present disclosure, fig. 6 illustrates a schematic flow diagram of a state machine for reading data at a logic side in an embodiment of the present disclosure, and fig. 7 illustrates a schematic flow diagram of calculating a direction of arrival at a system side in an embodiment of the present disclosure, where the method is applied to a system side of a system on chip, and includes:

step S501: carrying out array element reconstruction on position information data of at least one target object to obtain array element data and a first interrupt signal, wherein the first interrupt signal represents that a logic end is allowed to read the array element data;

step S502: storing the array element data into a second memory for being read by the logic end, wherein the logic end is used for carrying out independent parallel operation on the array element data and obtaining an independent parallel operation result and a second interrupt signal, and the second interrupt signal represents that the system end is allowed to read the independent parallel operation result;

in the embodiment of the application, a system end carries out array element reconstruction on position information data of a target object to obtain azimuth array element data and elevation array element data and generates a first interrupt signal, wherein the first interrupt signal comprises a first azimuth interrupt signal and a first elevation interrupt signal; similarly, after the system end completes the reconstruction of the pitching array elements, the first pitching interrupt signal and the pitching array element data are written into the memory for the logic end to read no matter whether the azimuth completes the reconstruction of the array elements.

Step S503: under the condition of acquiring the second interrupt signal, reading the independent parallel operation result;

step S504: and performing multi-kernel DOA calculation on the independent parallel operation result to obtain a point cloud image representing the DOA.

In the embodiment of the application, the system side performs multi-core DOA calculation on the independent parallel calculation result through a plurality of operation cores, and the operation can be performed simultaneously through the plurality of operation cores, so that the effect of saving DOA calculation time is achieved.

In a specific embodiment, please refer to fig. 6, fig. 6 shows a schematic flow chart of a logic terminal data reading state machine according to an embodiment of the present application, where when a first interrupt signal is written in a memory, the state machine jumps from an "initial state" to "start", then array element data is written in, and after a second interrupt signal is written in, the state machine starts to read an independent parallel operation result and then returns to the "initial state".

In a specific embodiment, please refer to fig. 7, fig. 7 shows a schematic diagram of a system-side direction of arrival calculation according to an embodiment of the present application, and 2D-CFAR in fig. 7 represents a two-dimensional constant false alarm rate, a radar sampling method; core0 represents an operation Core0, core1 represents an operation Core1, core2 represents an operation Core2, core3 represents an operation Core3, the embodiment of the application adopts ZYNQ type system on chip of FPGA, and 4 operation cores are included in PS terminal. The 4 operation cores simultaneously carry out array element reconstruction and DOA calculation on independent operation results generated by different target objects, and the interactive part of the PS end and the PL end is represented in a dotted line box. In the traditional operation mode, the single-core operation can only carry out the calculation of the direction of arrival on the independent operation result of one target object at the same time, if 4 target objects exist in total, the time for carrying out the calculation of the direction of arrival on a target 1, a target 2, a target 3 and a target 4 in sequence in the traditional operation mode is T, 4 operation cores are contained in a system end in the application, 4 operation cores can carry out the operation on 4 targets at the same time, and the time for calculating the direction of arrival of the system end in the application is T/4, so that the multi-core operation is adopted in the application, and the operation efficiency can be greatly improved.

In another specific embodiment, each operation core at the PS end further performs distance calculation on each target object according to the position information data of each target object before performing array element reconstruction on the position information data of the target object, and calculates a distance between the transmission source and the receiving radar; and after each operation core at the PS end carries out array element reconstruction on the position information data of the target object, the method also comprises the step of carrying out speed ambiguity resolution on the array element data so as to improve the detection range.

In an embodiment, please refer to fig. 7, where fig. 7 is a schematic diagram illustrating a system side direction of arrival calculation according to an embodiment of the present application, where the system side includes at least two operation cores, and the performing multi-core direction of arrival calculation on the independent parallel operation result includes:

In the embodiment of the application, the system end at least comprises two operation cores for calculating the direction of arrival, and different operation cores are responsible for calculating the direction of arrival of different target objects, so that the problem of low operation efficiency caused by sequentially calculating the direction of arrival of the target objects is solved.

In a specific embodiment, the PS end has 4 operation cores, 4 target objects exist during a certain direction of arrival calculation, the 4 operation cores perform array element reconstruction on position information data of the 4 target objects respectively, after the array element reconstruction is completed, corresponding array element data and a first interrupt signal are written into a memory, the PL end reads the array element data of each target in sequence to perform FFT, independent parallel operation results are written into the memory, and the independent parallel operation results of different target objects are distributed to different operation cores to perform the direction of arrival calculation.

In another specific embodiment, if there are 4 operation cores at the PS end and the number of the target objects is greater than 4, the target objects may be automatically grouped by the computer into 4 groups, and each operation core is responsible for calculating the direction of arrival of a group of target objects. The allocation method may also be that the target objects are numbered sequentially, the data of 4 target objects before the number are allocated to 4 operation cores respectively, and after one operation core completes the operation, the position information data of the target objects or the independent parallel operation results are acquired sequentially according to the order of the number to perform corresponding processing. It is to be understood that the present application is not limited to the particular dispensing method.

In one embodiment, please refer to fig. 8, fig. 8 is a schematic diagram illustrating a second interrupt signal reading situation according to an embodiment of the present application, where the second interrupt signal includes a second azimuth interrupt signal and a second pitch interrupt signal, and the independent parallel operation result includes an azimuth operation result and a pitch operation result, and the method includes:

the reading the independent parallel operation result when the second interrupt signal is acquired includes:

under the condition of acquiring the second azimuth interrupt signal, reading the azimuth operation result;

In the embodiment of the application, the second interrupt signal indicates that the PL end has completed independent parallel operation, and the independent parallel operation result is written into the memory, and if the PS end reads the second interrupt signal, the PS end can read the independent parallel operation result, where the second interrupt signal includes a second azimuth interrupt signal and a second pitch interrupt signal, and the PS end can directly read the corresponding independent parallel operation result to perform corresponding angle calculation without waiting for another interrupt signal when acquiring a certain second interrupt signal, thereby improving the operation efficiency of the PS end.

In a specific embodiment, when the PS terminal reads only the second azimuth interrupt signal but not the second pitch interrupt signal, the PS directly reads the azimuth operation result and calculates the azimuth of the target object.

In another specific embodiment, when there are multiple target objects, for example, 2 target objects, the PL side performs independent parallel operations on target 1 and target 2 in sequence, if there are 2 operation cores on the PS side, when the PL side completes the independent parallel operation on target 1, the PS side assigns it to operation core1, reads the independent parallel operation result on target 1 to perform angle calculation, and when the PL side completes the independent parallel operation on target 2, the PS side assigns it to operation core2 regardless of whether operation core1 completes the angle calculation. It can be understood that, for the target 1, if the azimuth parallel operation result is read first, the operation core1 calculates the azimuth angle first, and when the pitch parallel operation result can be read, the operation core1 calculates the pitch angle again. The operation content of the operation core1 and the operation content of the operation core2 are relatively independent.

In an embodiment, please refer to fig. 9, where fig. 9 shows a schematic diagram of multi-kernel radar calculation according to an embodiment of the present application, where the performing multi-kernel radar calculation on the independent parallel operation result to obtain a point cloud image representing a direction of arrival includes:

step S911: under the condition that the azimuth calculation result is read, calculating at least one azimuth angle based on the azimuth calculation result;

step S912: under the condition that the pitching operation result is read, calculating at least one pitching angle based on the pitching operation result;

step S920: and carrying out angle matching based on the azimuth angle and the pitch angle to obtain the point cloud image.

In the embodiment of the application, the multi-kernel arrival calculation of the PS terminal comprises angle calculation and angle matching, and finally point cloud is output. And the PS terminal firstly calculates the angle according to the read independent parallel operation result, starts to match the azimuth angle and the pitch angle after finishing the calculation of the azimuth angle and the pitch angle so as to restore the position of the target object and finally outputs the position in a point cloud mode.

In a specific embodiment, the multi-kernel radar calculation of each target object is performed in different operation cores, because there is at least one target object, then the PS end calculates at least one elevation angle and at least one azimuth angle during the angle calculation, and each target object corresponds to one azimuth angle and one elevation angle.

In another embodiment, the azimuth angle is an angle in the horizontal plane, and the pitch angle is an angle in a plane perpendicular to the horizontal plane, so that the position and distance of the target object can be restored according to the azimuth angle and the pitch angle.

In an embodiment, please refer to fig. 10, fig. 10 is a schematic flowchart illustrating a multi-kernel direction of arrival calculation method according to an embodiment of the present application, where the obtaining the point cloud image by performing angle matching based on the azimuth angle and the pitch angle includes:

step S1001: determining an azimuth angle and a pitch angle corresponding to each target object respectively;

step S1002: and obtaining a corresponding point cloud image of the target object based on the azimuth angle and the pitch angle.

In the embodiment of the application, the azimuth angle and the pitch angle corresponding to each target object are determined, the position and the distance of the target object are restored through the azimuth angle and the pitch angle corresponding to each target object, then the direction of arrival of the target object is determined, and the calculation of the direction of arrival of the emission source is completed.

In a specific embodiment, after the calculation of the azimuth angle and the pitch angle of a target object is completed in each operation core, the two angles are matched to determine the arrival direction of the target object.

In another specific embodiment, when the number of the target objects is greater than the number of the operation cores, each operation core performs angle calculation and angle matching on one target object each time, outputs a corresponding result, and performs angle calculation and angle matching on other target objects after outputting the result.

According to a third aspect of the present disclosure, there is provided a direction of arrival calculating apparatus, please refer to fig. 11, fig. 11 shows a block diagram of a direction of arrival calculating apparatus of a logic terminal according to an embodiment of the present disclosure, where the apparatus is applied to a logic terminal of a system on chip, and the apparatus includes:

an array element reading module 1110, configured to read array element data from a system side when a first interrupt signal is obtained, where the array element data includes azimuth array element data and pitch array element data, the system side is configured to perform array element reconstruction on position information data of at least one target object and obtain the array element data and the first interrupt signal, and the first interrupt signal indicates that the logic side is allowed to read the array element data;

in a specific embodiment, the array element reading module 1110 is configured to read the first interrupt signal and the array element data from the memory.

In a specific embodiment, the array element reading module is further divided into an azimuth dimension array element reading unit and a pitch dimension array element reading unit, wherein the azimuth dimension array element reading unit is configured to read the first azimuth interrupt signal and the azimuth dimension array element data, and the pitch dimension array element reading unit is configured to read the first pitch interrupt signal and the pitch dimension array element data.

An independent parallel operation module 1120, configured to perform independent parallel operation on the azimuth array element data and the pitch array element data to obtain an independent parallel operation result and a second interrupt signal, where the second interrupt signal represents that the system side is allowed to read the independent parallel operation result;

in a specific embodiment, the independent parallel operation module 1120 includes an azimuth parallel operation module and a pitch parallel operation module, wherein the azimuth parallel operation module is used for performing FFT on the azimuth array element data, and the pitch parallel operation module is used for performing FFT on the pitch array element data.

The first storage module 1130 is configured to store the independent parallel operation result in a first memory for the system side to read, where the system side is further configured to perform multi-core radar calculation based on the independent parallel operation result.

In a specific embodiment, the first storage module 1130 is used for storing the independent parallel operation result of the FFT and the second interrupt signal.

In a specific embodiment, the first storage module 1130 includes a first orientation storage module and a first pitch storage module, wherein the first orientation storage module is configured to store the orientation parallel operation result and the second orientation interrupt signal, and the first pitch storage module is configured to store the pitch parallel operation result and the second pitch interrupt signal.

According to a fourth aspect of the present disclosure, there is provided a direction of arrival calculating apparatus, please refer to fig. 12, fig. 12 shows a block diagram of a system-side direction of arrival calculating apparatus according to an embodiment of the present disclosure, the apparatus is applied to a system side of a system on chip, the apparatus includes:

an array element reconstruction module 1210, configured to perform array element reconstruction on position information data of at least one target object to obtain array element data and a first interrupt signal, where the first interrupt signal represents that a logic end is allowed to read the array element data;

in a specific embodiment, the array element reconstruction module 1210 is configured to perform array element reconstruction on raw data, where the raw data may be data representing source location information acquired by running a radar at a two-dimensional constant false alarm rate.

In a specific embodiment, the array element reconstructing module 1210 includes an azimuth dimension array element reconstructing module and a pitch dimension array element reconstructing module, where the azimuth dimension array element reconstructing module is configured to perform array element reconstruction on original data of an azimuth dimension and generate a first azimuth interrupt signal, and the pitch dimension array element reconstructing module is configured to perform array element reconstruction on original data of a pitch dimension and generate a first pitch interrupt signal.

A second storage module 1220, configured to store the array element data in a second memory for the logic terminal to read, where the logic terminal is configured to perform independent parallel operation on the array element data, and obtain an independent parallel operation result and a second interrupt signal, where the second interrupt signal indicates that the system terminal is allowed to read the independent parallel operation result;

in a specific embodiment, the second storage module 1220 is used for storing the array element data and the first interrupt signal.

In a specific embodiment, the second storage module 1220 includes a second orientation storage module for storing the orientation dimensional array metadata and the first orientation interrupt signal and a second pitch storage module for storing the pitch dimensional array metadata and the first pitch interrupt signal.

An operation result reading module 1230, configured to read the independent parallel operation result when the second interrupt signal is obtained;

in a specific embodiment, the operation result reading module 1230 includes an orientation operation result reading module and a pitching operation result reading module, wherein the orientation operation result reading module is configured to read the second orientation interrupt signal and the orientation parallel operation result, and the pitching operation result reading module is configured to read the second pitching interrupt signal and the pitching parallel operation result.

And the multinuclear wave arrival calculation module 1240 is used for carrying out multinuclear wave arrival calculation on the independent parallel operation result to obtain a point cloud image representing the wave arrival direction.

In a specific embodiment, the multi-core radar calculation module 1240 is configured to read the parallel azimuth calculation result and the parallel pitch calculation result, calculate an azimuth angle and a pitch angle, and determine a direction of arrival of the target object.

Referring to fig. 13, a first block diagram of an electronic device according to an embodiment of the present application is shown. The electronic device may be a terminal. The electronic device is configured to implement the direction of arrival calculation method provided in the above embodiment. Specifically, the method comprises the following steps:

the electronic device 1300 includes: a processor 1301 and a memory 1302.

Processor 1301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 1301 may be implemented in at least one of a DSP (Digital Signal Processing), an FPGA (Field Programmable Gate Array), and a PLA (Programmable Logic Array). Processor 1301 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in a wake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 1301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content that the display screen needs to display. In some embodiments, processor 1301 may further include an AI (Artificial Intelligence) processor for processing computational operations related to machine learning.

Memory 1302 may include one or more computer-readable storage media, which may be non-transitory. The memory 1302 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer-readable storage medium in the memory 1302 is used to store at least one instruction, at least one program, set of codes, or set of instructions configured to be executed by one or more processors to implement the above described direction of arrival calculation method.

In some embodiments, the electronic device 1300 may further optionally include: a peripheral interface 1303 and at least one peripheral. The processor 1301, memory 1302 and peripheral interface 1303 may be connected by buses or signal lines. Each peripheral device may be connected to the peripheral device interface 1303 via a bus, signal line, or circuit board. Specifically, the peripheral device includes: at least one of radio frequency circuitry 1304, touch display 1305, camera assembly 1306, audio circuitry 1307, positioning assembly 1308, and power supply 1309.

Those skilled in the art will appreciate that the configuration shown in fig. 13 is not intended to be limiting of the electronic device 1300 and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components may be used.

Please refer to fig. 14, which illustrates a block diagram of an electronic device according to another embodiment of the present application. The electronic device may be a server for performing the above-described direction of arrival calculation method. Specifically, the method comprises the following steps:

the electronic apparatus 1400 includes a Central Processing Unit (CPU) 1401, a system Memory 1404 including a Random Access Memory (RAM) 1402 and a Read Only Memory (ROM) 1403, and a system bus 1405 connecting the system Memory 1404 and the Central Processing Unit 1401. The electronic device 1400 also includes a basic Input/Output system (I/O) 1406 that facilitates transfer of information between devices within the computer, and a mass storage device 1407 for storing an operating system 1413, application programs 1414, and other program modules 1411.

The basic input/output system 1406 includes a display 1408 for displaying information and an input device 1409, such as a mouse, keyboard, etc., for user input of information. Wherein a display 1408 and an input device 1409 are both connected to the central processing unit 1401 via an input-output controller 1410 connected to the system bus 1405. The basic input/output system 1406 may also include an input/output controller 1410 for receiving and processing input from a number of other devices, such as a keyboard, mouse, or electronic stylus. Similarly, input-output controller 1410 also provides output to a display screen, a printer, or other type of output device.

The mass storage device 1407 is connected to the central processing unit 1401 through a mass storage controller (not shown) connected to the system bus 1405. The mass storage device 1407 and its associated computer-readable media provide non-volatile storage for the electronic device 1400. That is, the mass storage device 1407 may include a computer readable medium (not shown) such as a hard disk or CD-ROM (Compact disk Read-Only Memory) drive.

Without loss of generality, computer readable media may comprise computer storage media and communication media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes RAM, ROM, EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash Memory or other solid state Memory technology, CD-ROM, DVD (Digital Video Disc) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices. Of course, those skilled in the art will appreciate that computer storage media is not limited to the foregoing. The system memory 1404 and the mass storage device 1407 described above may collectively be referred to as memory.

According to various embodiments of the present application, the computer device 1400 may also operate as a remote computer connected to a network through a network, such as the Internet. That is, the computer device 1400 may be connected to the network 1412 through the network interface unit 1411 connected to the system bus 1405, or may be connected to other types of networks or remote computer systems (not shown) using the network interface unit 1411.

The memory also includes a computer program stored in the memory and configured to be executed by the one or more processors to implement the direction of arrival calculation method described above.

In an exemplary embodiment, a computer readable storage medium is also provided, in which at least one instruction, at least one program, a set of codes, or a set of instructions is stored, which when executed by a processor, implements the above-mentioned direction of arrival calculation method.

Optionally, the computer-readable storage medium may include: ROM (Read Only Memory), RAM (Random Access Memory), SSD (Solid State drive), or optical disc. The Random Access Memory may include a ReRAM (resistive Random Access Memory) and a DRAM (Dynamic Random Access Memory).

In an exemplary embodiment, a computer readable storage medium including program code, such as a memory including program code, executable by a processor to perform the video display method described above is also provided. Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a Random Access Memory (RAM), a compact-disc-read-only memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.

In an exemplary embodiment, a computer program product is also provided, comprising a computer program which, when executed by a processor, implements the direction of arrival calculation method described above.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A method for calculating a direction of arrival, the method being applied to a logic side of a system on a chip, the method comprising:

under the condition of acquiring a first interrupt signal, reading array element data from a system end, wherein the array element data comprises azimuth array element data and elevation array element data, the system end is used for carrying out array element reconstruction on position information data of at least one target object and obtaining the array element data and the first interrupt signal, and the first interrupt signal indicates that the logic end is allowed to read the array element data;

and storing the independent parallel operation result to a first storage for the system end to read, wherein the system end is also used for carrying out multi-core DOA calculation based on the independent parallel operation result.

2. The method of claim 1, wherein the first interrupt signal comprises a first azimuth interrupt signal and a first pitch interrupt signal, the method comprising:

under the condition of acquiring the first interrupt signal, reading array element data from a system end, including:

and under the condition that the first pitching interrupt signal is acquired, reading the pitching array metadata.

3. The method of claim 1 or 2, wherein the independent parallel operation results comprise an azimuth operation result and a pitch bit operation result, wherein the second interrupt signal comprises a second azimuth interrupt signal and a second pitch interrupt signal, and wherein the method comprises:

the independent parallel operation of the azimuth array element data and the elevation array element data is performed to obtain an independent parallel operation result and a second interrupt signal, and the method comprises the following steps:

and under the condition that the pitching array element data are read, performing independent pitching parallel operation on the pitching array element data to obtain a pitching operation result and the second pitching interrupt signal.

4. The method as claimed in any one of claims 1 to 3, wherein said logic terminal comprises at least two operation cores, and said performing independent parallel operation on said azimuth array element data and said elevation array element data comprises:

5. A method for calculating a direction of arrival, the method being applied to a system side of a system on a chip, the method comprising:

storing the array element data into a second memory for the logic end to read, wherein the logic end is used for carrying out independent parallel operation on the array element data and obtaining an independent parallel operation result and a second interrupt signal, and the second interrupt signal indicates that the system end is allowed to read the independent parallel operation result;

under the condition of acquiring the second interrupt signal, reading the independent parallel operation result;

and performing multi-core DOA calculation on the independent parallel operation result to obtain a point cloud image representing the DOA.

6. The method according to claim 5, wherein the system side includes at least two operation cores, and the performing multi-core DOA computation on the independent parallel operation results includes:

and distributing the independent parallel operation results to different operation cores according to the number of the operation cores and simultaneously performing multi-core DOA calculation.

7. The method of claim 5 or 6, wherein the second interrupt signal comprises a second azimuth interrupt signal and a second pitch interrupt signal, wherein the independent parallel operation results comprise an azimuth operation result and a pitch operation result, and wherein the method comprises:

and reading the pitching operation result under the condition of acquiring the second pitching interrupt signal.

8. The method of claim 7, wherein performing a multi-kernel DOA computation on the independent parallel operation results to obtain a point cloud image representing DOA, comprises:

under the condition that the azimuth operation result is read, calculating at least one azimuth angle based on the azimuth operation result;

9. The method of claim 8, wherein the performing angle matching based on the azimuth angle and the pitch angle to obtain the point cloud image comprises:

10. A direction-of-arrival computing apparatus, applied to a logic side of a system on chip, the apparatus comprising:

the array element reading module is used for reading array element data from a system end under the condition of acquiring a first interrupt signal, wherein the array element data comprises azimuth array element data and elevation array element data, the system end is used for carrying out array element reconstruction on position information data of at least one target object and acquiring the array element data and the first interrupt signal, and the first interrupt signal represents that the logic end is allowed to read the array element data;

the independent parallel operation module is used for independently and parallelly operating the azimuth array element data and the elevation array element data to obtain an independent parallel operation result and a second interrupt signal, and the second interrupt signal represents that the system end is allowed to read the independent parallel operation result;

and the first storage module is used for storing the independent parallel operation result to a first storage for the system end to read, and the system end is also used for carrying out multi-core DOA calculation based on the independent parallel operation result.

11. A direction-of-arrival calculation apparatus, applied to a system side of a system-on-chip, the apparatus comprising:

the array element reconstruction module is used for performing array element reconstruction on position information data of at least one target object to obtain array element data and a first interrupt signal, and the first interrupt signal indicates that a logic end is allowed to read the array element data;

the second storage module is used for storing the array element data to a second storage for the logic end to read, the logic end is used for carrying out independent parallel operation on the array element data and obtaining an independent parallel operation result and a second interrupt signal, and the second interrupt signal represents that the system end is allowed to read the independent parallel operation result;

the operation result reading module is used for reading the independent parallel operation result under the condition of acquiring the second interrupt signal;

and the multi-kernel DOA calculation module is used for carrying out multi-kernel DOA calculation on the independent parallel operation result to obtain a point cloud image representing the DOA.

12. A direction of arrival computing apparatus, the apparatus comprising a processor and a memory, the memory having stored therein at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement a direction of arrival computing method according to any one of claims 1 to 4 or a direction of arrival computing method according to any one of claims 5 to 9.

13. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement a direction of arrival calculation method of any one of claims 1 to 4 or a direction of arrival calculation method of any one of claims 5 to 9.