CN115684900A

CN115684900A - State monitoring method and system for power supply FPGA

Info

Publication number: CN115684900A
Application number: CN202211029768.2A
Authority: CN
Inventors: 张永超; 张阿珍
Original assignee: Beijing Topsec Technology Co Ltd; Beijing Topsec Network Security Technology Co Ltd; Beijing Topsec Software Co Ltd
Current assignee: Beijing Topsec Technology Co Ltd; Beijing Topsec Network Security Technology Co Ltd; Beijing Topsec Software Co Ltd
Priority date: 2022-08-25
Filing date: 2022-08-25
Publication date: 2023-02-03

Abstract

The embodiment of the application provides a method and a system for monitoring the state of an FPGA (field programmable gate array), and relates to the technical field of computers. The FPGA state monitoring method comprises the following steps: carrying out initialization state monitoring on the FPGA equipment to generate initialization state monitoring data; monitoring the state of the recognition rate of the FPGA equipment to generate the monitoring data of the state of the recognition rate; monitoring the connectivity state of the FPGA equipment to generate connectivity state monitoring data; monitoring the whole real-time state of the FPGA equipment to generate real-time state data; and generating processing instruction information according to the initialization state monitoring data, the identification rate state monitoring data, the connectivity state monitoring data and the real-time state data. The FPGA state monitoring method can achieve the technical effects of real-time monitoring and small occupied system resources.

Description

State monitoring method and system for power supply FPGA

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and a system for monitoring a state of an FPGA, an electronic device, and a computer-readable storage medium.

Background

At present, an abnormal handling mode of a logic code of a Field Programmable Gate Array (FPGA) is positioned according to an original overall investigation mode, and the positioning mode has the problems of slow positioning problem, complex positioning mode, difficult analysis and the like. The reason is that the logic code amount of an existing FPGA is huge, the FPGA is composed of a plurality of modules, corresponding relations exist among the modules, if a certain module has a problem, the problem is still relatively easy to be solved, but the problem of the modules can cause that the problem is solved to be extremely difficult; in addition, the risk of disassembling and assembling the equipment may exist in the examination, because the FPGA is generally a board card interconnected in the equipment, the problem positioning becomes more complicated and difficult, the design precision and integrity of some equipment are good, and the equipment is easily damaged by non-professional personnel during the disassembly, which causes additional economic loss.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method, a system, an electronic device, and a computer-readable storage medium for monitoring a state of an FPGA, which can achieve a technical effect of real-time monitoring and occupying less system resources.

In a first aspect, an embodiment of the present application provides a method for monitoring a state of an FPGA, including:

carrying out initialization state monitoring on the FPGA equipment to generate initialization state monitoring data;

monitoring the state of the recognition rate of the FPGA equipment to generate the monitoring data of the state of the recognition rate;

performing connectivity state monitoring on the FPGA equipment to generate connectivity state monitoring data;

monitoring the whole real-time state of the FPGA equipment to generate real-time state data;

and generating processing instruction information according to the initialization state monitoring data, the identification rate state monitoring data, the connectivity state monitoring data and the real-time state data.

In the implementation process, the FPGA state monitoring method monitors the initialization state, the recognition rate state, the connectivity state and the whole real-time state of the PGA device, generates processing instruction information according to the state data, and can record the FPGA state in time through the monitoring data when the FPGA is abnormal so as to acquire enough information and locate the cause of the problem, thereby realizing real-time monitoring, accurately locating the abnormal point and occupying less system resources; configuration commands are provided by processing the instruction information, and the FPGA can be recovered in time if necessary; therefore, the FPGA state monitoring method can achieve the technical effects of real-time monitoring and less occupied system resources.

Further, the step of performing initialization state monitoring on the FPGA device to generate initialization state monitoring data includes:

initializing the FPGA equipment;

executing preset operation on the network port up, the network port down and the network port up of the FPGA device to obtain register state value data;

monitoring the DDR initialization state of the FPGA equipment to obtain DDR initialization state data;

monitoring the state of an SM state monitoring register of the FPGA equipment to acquire SM state data;

and generating the initialization state monitoring data according to the register state value data, the DDR initialization state data and the SM state data.

Further, after the step of monitoring the DDR initialization state of the FPGA device and acquiring DDR initialization state data, the method includes:

performing pre-reading operation on the value of a DDR monitoring register of the FPGA device to acquire DDR monitoring register data;

and if the DDR monitoring register data is matched with the preset data, generating normal state information.

Further, the step of monitoring the identification rate state of the FPGA device to generate identification rate state monitoring data includes:

acquiring identification rate information of the FPGA equipment;

and generating recognition rate state monitoring data according to a preset equipment rate table and the recognition rate information.

Further, the step of performing connectivity state monitoring on the FPGA device to generate connectivity state monitoring data includes:

generating message information according to preset conditions;

counting the message information and forwarding the message information to generate message feedback information;

and generating connectivity state monitoring data according to the message information and the message feedback information.

Further, the step of monitoring the overall real-time state of the FPGA device to generate real-time state data includes:

adding a distributed monitoring point corresponding to each module in the logic code of the FPGA equipment, connecting the distributed monitoring points to a main monitoring module, and acquiring state feedback information through the main monitoring module;

and generating the real-time state data according to the state feedback information.

In a second aspect, an embodiment of the present application provides a status monitoring system for an FPGA, including:

the initialization state unit is used for carrying out initialization state monitoring on the FPGA equipment and generating initialization state monitoring data;

the recognition rate state unit is used for monitoring the recognition rate state of the FPGA equipment and generating recognition rate state monitoring data;

the connectivity state unit is used for monitoring the connectivity state of the FPGA equipment and generating connectivity state monitoring data;

the real-time state unit is used for monitoring the integral real-time state of the FPGA equipment and generating real-time state data;

and the processing unit is used for generating processing instruction information according to the initialization state monitoring data, the identification rate state monitoring data, the connectivity state monitoring data and the real-time state data.

Further, the initialization state unit is specifically configured to:

initializing the FPGA equipment;

executing preset operation on the network port up, the network port down and the network port up of the FPGA equipment to obtain register state value data;

monitoring the DDR initialization state of the FPGA equipment to acquire DDR initialization state data;

Further, the initialization status unit is further configured to:

Further, the rate state identification unit is specifically configured to:

acquiring identification rate information of the FPGA equipment;

Further, the connectivity status unit is specifically configured to:

generating message information according to preset conditions;

Further, the real-time status unit is specifically configured to:

In a third aspect, an electronic device provided in an embodiment of the present application includes: memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method according to any of the first aspect when executing the computer program.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having instructions stored thereon, which, when executed on a computer, cause the computer to perform the method according to any one of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer program product, which when run on a computer, causes the computer to perform the method according to any one of the first aspect.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the above-described techniques.

In order to make the aforementioned objects, features and advantages of the present application comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic flowchart of a method for monitoring a state of an FPGA according to an embodiment of the present disclosure;

fig. 2 is a block diagram of a structure of a state monitoring and protecting device of an FPGA according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of another method for monitoring a status of an FPGA according to an embodiment of the present disclosure;

fig. 4 is a block diagram of an initialization state comparison module according to an embodiment of the present disclosure;

fig. 5 is a block diagram of a device rate status comparison module according to an embodiment of the present disclosure;

fig. 6 is a block diagram of a device connectivity comparison module according to an embodiment of the present disclosure;

FIG. 7 is a block diagram of an overall module status comparison module according to an embodiment of the present disclosure;

fig. 8 is a block diagram of a state monitoring system of an FPGA according to an embodiment of the present disclosure;

fig. 9 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

The embodiment of the application provides a method and a system for monitoring the state of an FPGA (field programmable gate array), electronic equipment and a computer readable storage medium, which can be applied to a monitoring and protecting device facing the FPGA; according to the FPGA state monitoring method, the initialization state, the recognition rate state, the connectivity state and the whole real-time state of the PGA device are monitored, and processing instruction information is generated according to the state data, when the FPGA is abnormal, the FPGA state can be recorded in time through the monitoring data so as to obtain enough information and locate the cause of the problem, so that real-time monitoring is realized, the abnormal point can be accurately located, and less system resources are occupied; configuration commands are provided by processing the instruction information, and the FPGA can be recovered in time if necessary; therefore, the FPGA state monitoring method can achieve the technical effects of real-time monitoring and less occupied system resources.

Referring to fig. 1, fig. 1 is a schematic flow chart of a method for monitoring a state of an FPGA according to an embodiment of the present disclosure, where the method for monitoring the state of the FPGA includes the following steps:

s100: and carrying out initialization state monitoring on the FPGA equipment to generate initialization state monitoring data.

For example, after the FPGA device is powered on and started, the initialization state monitoring is a key part in the whole monitoring, the initialization process is normal on the premise that the system normally operates, and whether the initialization state is normal is judged by monitoring the state of the corresponding register.

S200: and monitoring the identification rate state of the FPGA equipment to generate identification rate state monitoring data.

For example, the device identification rate monitoring in S200 is an important means for ensuring that the operating state of the device is in accordance with the design performance expectation, because different devices have different compatibility with PCIE, the situation that the negotiation rates of the same FPGA board card on different devices are different may occur, which may cause the risk of reducing the bandwidth of the FPGA board card, thereby greatly reducing the performance of the device.

S300: and monitoring the connectivity state of the FPGA equipment to generate connectivity state monitoring data.

For example, the monitoring of the connectivity state in S300 may ensure that the hardware of the device remains unblocked; since the equipment is in an interrupted state due to the fact that the physical connection is broken under the normal initialization condition, the problem is greatly solved, especially the FPGA card is located inside the equipment, the problem is difficult to locate for technicians in the field, and the problem can be searched only by disassembling the equipment, which is extremely unfriendly for customers; and the monitoring of the connectivity state is carried out, and the monitoring data of the connectivity state is generated, so that the complex problem can be simplified, and the problem can be easily fed back without disassembling the equipment.

S400: and monitoring the integral real-time state of the FPGA equipment to generate real-time state data.

For example, in the overall status monitoring in S400, real-time status data is an important means for locating problems for developers, and is also a quick means for accurately locating problem modules in projects with numerous modules.

S500: and generating processing instruction information according to the initialized state monitoring data, the identification rate state monitoring data, the connectivity state monitoring data and the real-time state data.

For example, the processing instruction information of S500 may perform up and down operations on the port of the FPGA by processing the instruction information when the FPGA device is abnormal, so as to reset a part of logic functions of the FPGA and further restore the functions of the FPGA to normal, and if the whole FPGA is abnormal, the instruction information may also be issued by software to complete the whole logic reset of the FPGA.

In some implementation scenes, the FPGA state monitoring method monitors the initialization state, the recognition rate state, the connectivity state and the whole real-time state of the PGA device and generates processing instruction information according to the state data, when the FPGA is abnormal, the FPGA state can be recorded in time through the monitoring data so as to obtain enough information and locate the cause of the problem, thereby realizing real-time monitoring, accurately locating the abnormal point and occupying less system resources; configuration commands are provided by processing the instruction information, and the FPGA can be recovered in time if necessary; therefore, the FPGA state monitoring method can achieve the technical effects of real-time monitoring and less occupied system resources.

Referring to fig. 2, fig. 2 is a block diagram of a state monitoring and protecting device of an FPGA according to an embodiment of the present disclosure; the state monitoring and protecting device of the FPGA shown in fig. 2 corresponds to the embodiment of the method shown in fig. 1.

Referring to fig. 3, fig. 3 is a schematic flow chart of another method for monitoring a status of an FPGA according to an embodiment of the present disclosure.

Referring to fig. 4, fig. 4 is a block diagram of an initialization state comparison module according to an embodiment of the present disclosure.

Exemplarily, S100: the method comprises the following steps of monitoring the initialization state of the FPGA equipment and generating initialization state monitoring data, and comprises the following steps:

s110: initializing the FPGA equipment;

s120: executing preset operation on a network port up, a network port down and a network port up of the FPGA equipment to obtain register state value data;

s130: monitoring the DDR initialization state of the FPGA equipment to acquire DDR initialization state data;

s140: monitoring the state of an SM state monitoring register of the FPGA equipment to acquire SM state data;

s150: and generating the initialized state monitoring data according to the register state value data, the DDR initialized state data and the SM state data.

Illustratively, at S130: after the step of monitoring the DDR initialization state of the FPGA device and acquiring the DDR initialization state data, the method comprises the following steps:

performing pre-reading operation on the value of a DDR monitoring register of the FPGA device to obtain DDR monitoring register data;

and if the data of the DDR monitoring register is matched with the preset data, generating normal state information.

Exemplarily, with reference to fig. 2 to 4, the process of monitoring the initialization state of the FPGA device is as follows: firstly, in the initialization process, software is required to execute the operation of the network port up, the network port down and the network port up first, so that the normal operation of the network port can be ensured, and whether the register state value in the whole process is matched with a correct state value is monitored. Secondly, the initialization process needs to monitor the initialization state of the DDR, the value of the DDR monitoring register needs to be pre-read first, then the value of the DDR monitoring register is read continuously, and the state is not returned to be normal until the value of the register is detected to be matched with a preset correct value. Finally, monitoring the enabling state of the SM, firstly acquiring the value of an SM state monitoring register, then comparing the returned value in real time, and reporting that the state is normal when the returned value meets a preset value;

the detailed operation process is shown in fig. 4, the system initialization file shown in fig. 4 is generated by MATLAB software according to data of level values of initialized registers, the mif file is used as an initialization file of ram, the initialization state comparison module loads the mif file during operation to obtain correct state values of the registers, the initialization state acquisition module sequentially obtains actual state values of the registers according to set logic at the same time, in order to ensure the final correctness of acquired values, the actual state values are continuously acquired for 5 times according to the setting, then the acquired data and the actually loaded data are compared according to the sequence of the initialization registers until the comparison work of all the initialization registers is completed, and finally, according to all comparison results, the state values are fed back, if the feedback values are high levels, all the results are the same, that is, the initialization state is normal, otherwise, if the feedback values are low levels, the initialization state is abnormal.

Referring to fig. 5, fig. 5 is a block diagram of a device rate status comparison module according to an embodiment of the present disclosure.

Exemplarily, S200: the method comprises the following steps of monitoring the state of the identification rate of the FPGA equipment and generating monitoring data of the state of the identification rate, and comprises the following steps:

s210: acquiring identification rate information of the FPGA equipment;

s220: and generating recognition rate state monitoring data according to the preset equipment rate table and the recognition rate information.

Illustratively, the device rate comparison module shown in fig. 5 includes a device correct rate table, a device rate mapping module, and a device rate status processing module. The function of the equipment rate mapping module is to complete the identification of the actual negotiation rate, when the equipment rate state comparison module receives the sign that the equipment is running normally, the equipment rate comparison module starts to send a state monitoring command to the equipment rate mapping module, the module starts to carry out rate acquisition after receiving the command, in order to ensure the accuracy of acquisition, the program sets to carry out acquisition once every 5ms, carry out acquisition for three times continuously, and finally feed back to the equipment rate state processing module, at the moment, the module compares with the received feedback value according to a correct rate table, if the two values are consistent, the high level is fed back, otherwise, the low level is fed back.

Referring to fig. 6, fig. 6 is a block diagram of a device connectivity comparison module according to an embodiment of the present disclosure.

Exemplarily, S300: the method comprises the following steps of monitoring the connectivity state of FPGA equipment and generating connectivity state monitoring data, and comprises the following steps:

s310: generating message information according to preset conditions;

s320: counting and forwarding the message information to generate message feedback information;

s330: and generating connectivity state monitoring data according to the message information and the message feedback information.

Illustratively, the device connectivity comparison module in fig. 6 includes a message generation module and a message processing module. The message generation module can generate Ethernet messages with different sizes and different quantities according to requirements; the message processing module can perform statistics on the received and transmitted messages and has the message transmitting and receiving function, when the connectivity comparison module receives the monitoring command, the connectivity comparison module transmits the command to the message generation module according to the size and quantity requirements of the transmitted messages in the command, when the message processing module receives the message, the message statistics and the message transmission are performed, then the system processing module feeds back the message statistics received in the system, if the statistics data before the two are the same, the connectivity is normal, if one end has statistics, the statistics data at one end is 0, the connectivity is abnormal, and if the statistics data at the two ends are different, the processing at the two ends is abnormal.

Referring to fig. 7, fig. 7 is a block diagram of an overall module state comparison module according to an embodiment of the present disclosure.

Exemplarily, S400: the method comprises the steps of monitoring the whole real-time state of the FPGA equipment and generating real-time state data, and comprises the following steps:

s410: adding a distributed monitoring point corresponding to each module in the logic code of the FPGA equipment, connecting the distributed monitoring points to a main monitoring module, and acquiring state feedback information through the main monitoring module;

s420: and generating real-time state data according to the state feedback information.

Illustratively, the specific monitoring mode is that distributed monitoring points are added to each module in the logic code, then the distributed monitoring points are uniformly connected to the main monitoring module, the module receives state feedback of all the distributed monitoring points, and the principle of realizing state monitoring by the distributed monitoring points is as follows: 0 is written in a state monitoring register of the main module at regular time, and is read at regular time, when a returned value is a preset value, the state is normal, otherwise, the state is abnormal, and the current values of the FPGA debugging registers of all the distributed monitoring points are stored under the abnormal condition, and a specific block diagram is shown in FIG. 7.

Illustratively, in combination with fig. 2 and fig. 7, the state analysis processing module has two functions, one of which is a module that receives state feedback of each stage, and the module sorts the feedback states, classifies the feedback states according to a pre-designed priority, and sends the sorted feedback states to the health record for storage; and the other is the transmission and processing of the relevant commands of each monitoring module. And the function of the health record is to save the state of the device. The mode of combining software and hardware can not only reduce the occupation of the FPGA by the state monitoring, but also can comprehensively monitor the equipment.

For example, with reference to fig. 1 to fig. 7, the method for monitoring the state of the FPGA provided in the embodiment of the present application may be applied to design of an intelligent network accelerator card; the embodiment describes a state monitoring and protecting method based on a full-autonomous defined secure network acceleration product, and achieves the improvement of the efficiency of fault discharge by adding a distributed network state monitoring and protecting device in the full-autonomous defined secure network acceleration. According to the method in the detailed description of the present application, a specific flow example is as follows:

step 1: the method comprises the steps that after the equipment is powered on, a system starts initialization, the distributed state monitoring and protection device starts service automatically, a default initialization process starts, the optical port is closed firstly, initialization of the FPGA PCIe equipment is completed, then the optical port is opened, and the state of the optical port is uploaded.

Step 2: after the initialization is normally completed, the rate negotiation of the PCIE is completed, the monitoring of the network point starts to feed back the actual rate of the monitoring and compares the actual rate with the correct negotiation rate, if the actual rate is matched with the correct negotiation rate, the feedback rate is normal, otherwise, the feedback rate is abnormal, and the abnormal value is recorded.

And step 3: with the normal initialization and rate monitoring results, the equipment can perform normal packet receiving and sending operations, the monitoring network point can acquire the number of message receiving and sending in the FPGA in real time at the moment, the CPU direction can record the number of the received and sent messages at the moment, and whether the connectivity of the data path is normal or not can be fed back at any time by comparing the number of the message receiving and sending between the monitoring network point and the CPU.

And 4, step 4: finally, the above monitoring results are all in a normal state, and at this time, the functions of the whole project can be normally operated, so that normal data processing and network message acceleration can be performed.

And 5: after the equipment normally runs, the monitoring module is started in real time, the states of the following modules are monitored and compared, and abnormal conditions are reported.

Illustratively, the application focuses on an application scenario of FPGA state monitoring and protection, and the related technical key points are as follows: the whole monitoring mode of the system is more important to monitor the whole state, the FPGA and the software are combined, the FPGA can monitor the state of the state machine of each module in real time, and the software can record and alarm the abnormality in real time if the abnormality occurs.

Referring to fig. 8, fig. 8 is a block diagram of a structure of a state monitoring system of an FPGA according to an embodiment of the present disclosure, where the state monitoring system of the FPGA includes:

an initialization state unit 100, configured to perform initialization state monitoring on the FPGA device, and generate initialization state monitoring data;

the identification rate state unit 200 is used for monitoring the identification rate state of the FPGA device and generating identification rate state monitoring data;

a connectivity state unit 300, configured to perform connectivity state monitoring on the FPGA device, and generate connectivity state monitoring data;

the real-time state unit 400 is used for monitoring the overall real-time state of the FPGA equipment and generating real-time state data;

the processing unit 500 is configured to generate processing instruction information according to the initialization state monitoring data, the identification rate state monitoring data, the connectivity state monitoring data, and the real-time state data.

Illustratively, the initialization state unit 100 is specifically configured to:

initializing the FPGA equipment;

executing preset operation on a network port up, a network port down and a network port up of the FPGA equipment to obtain register state value data;

and generating the initialized state monitoring data according to the register state value data, the DDR initialized state data and the SM state data.

Illustratively, the initialization state unit 100 is further configured to:

Illustratively, the identify rate state unit 200 is specifically configured to:

acquiring identification rate information of the FPGA equipment;

and generating recognition rate state monitoring data according to the preset equipment rate table and the recognition rate information.

Exemplarily, the connectivity status unit 300 is specifically configured to:

generating message information according to preset conditions;

counting and forwarding the message information to generate message feedback information;

Illustratively, the real-time status unit 400 is specifically configured to:

and generating real-time state data according to the state feedback information.

Fig. 9 shows a block diagram of an electronic device according to an embodiment of the present disclosure, where fig. 9 is a block diagram of the electronic device. The electronic device may include a processor 510, a communication interface 520, a memory 530, and at least one communication bus 540. Wherein the communication bus 540 is used for realizing direct connection communication of these components. In this embodiment, the communication interface 520 of the electronic device is used for performing signaling or data communication with other node devices. Processor 510 may be an integrated circuit chip having signal processing capabilities.

The Processor 510 may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 510 may be any conventional processor or the like.

The Memory 530 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Read Only Memory (EPROM), an electrically Erasable Read Only Memory (EEPROM), and the like. The memory 530 stores computer readable instructions, and when the computer readable instructions are executed by the processor 510, the electronic device may perform the steps related to the method embodiments of fig. 1 to 7.

Optionally, the electronic device may further include a memory controller, an input output unit.

The memory 530, the memory controller, the processor 510, the peripheral interface, and the input/output unit are electrically connected to each other directly or indirectly, so as to implement data transmission or interaction. For example, these elements may be electrically coupled to each other via one or more communication buses 540. The processor 510 is used to execute executable modules stored in the memory 530, such as software functional modules or computer programs included in the electronic device.

The input and output unit is used for providing a task for a user to create and start an optional time period or preset execution time for the task creation so as to realize the interaction between the user and the server. The input/output unit may be, but is not limited to, a mouse, a keyboard, and the like.

It will be appreciated that the configuration shown in fig. 9 is merely illustrative and that the electronic device may include more or fewer components than shown in fig. 9 or have a different configuration than shown in fig. 9. The components shown in fig. 9 may be implemented in hardware, software, or a combination thereof.

The embodiment of the present application further provides a storage medium, where the storage medium stores instructions, and when the instructions are run on a computer, when the computer program is executed by a processor, the method in the method embodiment is implemented, and in order to avoid repetition, details are not repeated here.

The present application also provides a computer program product which, when run on a computer, causes the computer to perform the method of the method embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

Claims

1. A state monitoring method of an FPGA is characterized by comprising the following steps:

2. The method for monitoring the state of the FPGA according to claim 1, wherein the step of monitoring the initialization state of the FPGA device and generating the initialization state monitoring data comprises:

initializing the FPGA equipment;

3. The method for monitoring the state of the FPGA according to claim 2, wherein after the step of monitoring the DDR initialization state of the FPGA device and acquiring DDR initialization state data, the method comprises:

4. The method for monitoring the status of the FPGA according to claim 1, wherein the step of monitoring the status of the identification rate of the FPGA device to generate the monitoring data of the identification rate comprises:

acquiring identification rate information of the FPGA equipment;

and generating recognition rate state monitoring data according to a preset device rate table and the recognition rate information.

5. The method for monitoring the state of the FPGA according to claim 1, wherein the step of performing connectivity state monitoring on the FPGA device to generate connectivity state monitoring data comprises:

generating message information according to preset conditions;

6. The method for monitoring the state of the FPGA according to claim 1, wherein the step of performing the overall real-time state monitoring on the FPGA device to generate the real-time state data comprises:

7. A status monitoring system for an FPGA, comprising:

8. The FPGA status monitoring system of claim 7, wherein the initialization status unit is specifically configured to:

initializing the FPGA equipment;

9. An electronic device, comprising: memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method of status monitoring of an FPGA of one of claims 1 to 6 when executing the computer program.

10. A computer readable storage medium having stored thereon instructions which, when run on a computer, cause the computer to perform a method of monitoring the status of an FPGA of any one of claims 1 to 6.