CN115668159A

CN115668159A - Caching method, system and chip

Info

Publication number: CN115668159A
Application number: CN202080101463.0A
Authority: CN
Inventors: 张乾龙
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-07-30
Filing date: 2020-07-30
Publication date: 2023-01-31
Also published as: WO2022021178A1

Abstract

The embodiment of the application provides a cache system, a cache method and a chip, wherein the cache method comprises the following steps: receiving a data reading request, and determining data needing to be written into a cache from a memory based on the data reading request; acquiring the number of times of data access requests received in unit time; selecting a first page from the cache based on the number of data access requests; the data which needs to be written into the cache from the memory is stored in the first page, and the caching method disclosed by the embodiment of the application can improve the data caching efficiency.

Description

Caching method, system and chip

Technical Field

The embodiment of the application relates to the technical field of caching, in particular to a caching method, a caching system and a caching chip.

Background

With the development of chip technology, the realization media of the memory are more and more diversified. A new technology for solving the problem of memory access bandwidth is provided in a Die-stacked DRAM (Die-stacked DRAM). The large-capacity memory chip and the processor can be packaged on the same system-on-chip Soc by a Through Silicon Via (TSV) technology, so as to realize the on-chip large-capacity memory. Taking 2.5D or 3D packaged DRAM as an example, data show that the bandwidth of the on-chip memory can reach 4-8 times of that of an off-chip double data rate DRAM (DDR DRAM).

In the prior art, an on-chip memory may be used as a normal memory, and may also be used as a cache of an off-chip memory (DDR). When the on-chip memory is used as a cache, the cache space in the cache is allocated with the granularity of the page. The cache space of the cache can be divided into a plurality of pages, and similarly, the memory space can also be divided into a plurality of pages. When the data in the off-chip memory is stored in the cache page, one cache page can be selected from the cache for storage based on the mapping relationship between the memory page and the cache page established in advance. When all cache pages in the cache store data and the data in the memory needs to be stored in the cache, a page is selected from the cache by adopting a replacement mode of the least recently used data or a first-in first-out data replacement mode, so as to replace the data stored before the selected page with the latest acquired data. The page selected by the traditional method may store more dirty data, which is data stored in the cache and overwritten by the processor. When a page is replaced, it needs to be written back to the memory. When dirty data needing to be written back to the memory is more, the cache bandwidth is seriously occupied, data congestion is caused, the data transmission efficiency is reduced, and data access delay is caused.

Therefore, how to improve the data caching efficiency in the large-capacity caching scenario becomes a problem to be solved.

Disclosure of Invention

The cache method, the cache system and the cache chip can improve the data cache efficiency.

In order to achieve the purpose, the following technical scheme is adopted in the application:

in a first aspect, an embodiment of the present application provides a caching method, where the caching method includes: receiving a data reading request, and determining data needing to be written into a cache from a memory based on the data reading request; acquiring the number of times of data access requests received in unit time; selecting a first page from the cache based on the number of data access requests; and storing the data needing to be written into the cache from the memory in the first page.

According to the caching method provided by the application, data are stored in the cache pages, when the data to be cached need to cover the original data stored in the cache, the use condition of the cache bandwidth can be determined by counting the times of the access requests sent by the processor in unit time, and then the cache pages are selected based on the use condition of the cache bandwidth, so that the data to be cached are stored in the selected cache pages. In specific implementation, the cache page with lower dirty data in the stored data can be selected in a time period with higher data transmission quantity, so that the occupancy rate of the access bandwidth can be reduced, and the data cache efficiency and the data access efficiency of the processor can be improved.

Based on the first aspect, in a possible implementation manner, selecting a first page from the cache based on the number of data access requests includes: and responding to the data access request times larger than or equal to a first threshold value, and selecting a page with least dirty data stored in the cache as the first page.

Based on the first aspect, in a possible implementation manner, selecting a first page from the cache based on the number of data access requests includes: responding to the data access request, wherein the number of times of the data access request is smaller than a first threshold, and selecting the first page from the cache based on priority information of data stored in each page in the cache; the priority level comprises one of: least recently used information, first-in-first-out information, or access frequency information.

Based on the first aspect, in a possible implementation manner, the selecting a first page from the cache based on the number of data access requests includes: and responding to the data access request, wherein the number of times is larger than or equal to a first threshold, and the first page is selected based on the cache access amount in unit time and the memory access amount in unit time.

The first page is selected to store data by further introducing the ratio between the cache access amount and the memory access amount, so that the cache hit rate and the bandwidth occupancy rate can be further considered, and the cache efficiency is further improved.

Based on the first aspect, in a possible implementation manner, the cache access amount includes one of: the number of cache hits or the amount of data transfer between the cache and the processor; the memory access amount includes one of: the number of memory accesses or the amount of data transferred between the memory and the processor.

Based on the first aspect, in a possible implementation manner, the selecting the first page based on the cache access amount in unit time and the memory access amount in unit time includes: determining a ratio between the cache access amount and the memory access amount; and selecting the first page from the cache based on the ratio of the cache access amount to the memory access amount.

Based on the first aspect, in a possible implementation manner, the selecting the first page from the cache based on a ratio between the cache access amount and the memory access amount includes: and in response to the fact that the ratio of the cache access amount to the memory access amount is larger than or equal to a second threshold value, selecting the first page from the cache based on the position information of the page in the cache occupied by the data needing to be written into the cache from the memory and the position information of the dirty data stored in each page in the cache.

Based on the first aspect, in a possible implementation manner, the selecting the first page from the cache based on a ratio between the cache access amount and the memory access amount includes: in response to that the ratio of the cache access amount to the memory access amount is smaller than the second threshold, selecting the first page from the cache based on priority information of data stored in each page in the cache; the priority level comprises one of: least recently used information, first-in-first-out information, or access frequency information.

Based on the first aspect, in a possible implementation manner, the method further includes: and updating first index information stored in the cache, wherein the first index information is used for indexing the data which is stored in the first page and needs to be written into the cache from the memory.

Based on the first aspect, in a possible implementation manner, the method further includes: and obtaining the position information of the idle data unit in the first page, and updating second index information stored in the cache according to the position information of the idle data unit, wherein the second index information is used for indexing original data in a data unit corresponding to the position information in the first page.

In a second aspect, an embodiment of the present application provides a cache system, where the cache system includes a cache, and is configured to store data from a memory and index information used to index the data stored in the cache; the storage controller is used for receiving a data reading request and determining data needing to be written into the cache from the memory based on the data reading request; acquiring the number of times of data access requests received in unit time; selecting a first page from the cache based on the number of data access requests; and storing the data needing to be written into the cache from the memory in the first page.

Based on the second aspect, in a possible implementation manner, the storage controller is further configured to: in response to the number of data access requests being greater than or equal to a first threshold, selecting the first page from the cache based on dirty data stored in pages in the cache.

Based on the second aspect, in a possible implementation manner, the storage controller is further configured to: responding to the data access request, wherein the number of times of the data access request is smaller than a first threshold, and selecting the first page from the cache based on priority information of data stored in each page in the cache; the priority level comprises one of: least recently used information, first-in-first-out information, or access frequency information.

Based on the second aspect, in a possible implementation manner, the storage controller is further configured to: and responding to the data access request, wherein the number of times is larger than or equal to a first threshold, and the first page is selected based on the cache access amount in unit time and the memory access amount in unit time.

Based on the second aspect, in a possible implementation manner, the cache access amount includes one of: the number of cache hits or the amount of data transfer between the cache and the processor; the memory access amount includes one of: the number of memory accesses or the amount of data transferred between the memory and the processor.

Based on the second aspect, in a possible implementation manner, the storage controller is further configured to: determining a ratio between the cache access amount and the memory access amount; and selecting the first page from the cache based on the ratio of the cache access amount to the memory access amount.

Based on the second aspect, in a possible implementation manner, the storage controller is further configured to: and in response to the fact that the ratio of the cache access amount to the memory access amount is larger than or equal to a second threshold value, selecting the first page from the cache based on the position information of the page in the cache occupied by the data needing to be written into the cache from the memory and the position information of the dirty data stored in each page in the cache.

Based on the second aspect, in a possible implementation manner, the storage controller is further configured to: in response to that the ratio of the cache access amount to the memory access amount is smaller than the second threshold, selecting the first page from the cache based on priority information of data stored in each page in the cache; the priority level comprises one of: least recently used information, first-in-first-out information, or access frequency information.

Based on the second aspect, in a possible implementation manner, the cache system further includes a first counter, and the first counter is used for counting the number of data access requests received by the storage controller in a unit time.

Based on the second aspect, in a possible implementation manner, the cache system further includes a second counter; the second counter is used for counting the cache access amount of the storage controller in unit time; wherein the cache access amount comprises one of: the number of cache hits or the amount of data transferred between the cache and the processor.

In a possible implementation manner, based on the second aspect, the cache system further includes a third counter; the third counter is used for counting the memory access amount of the memory controller in unit time; wherein the memory access amount comprises one of: the number of memory accesses or the amount of data transferred between the memory and the processor.

In a third aspect, an embodiment of the present application provides a chip, where the chip includes the cache system according to the second aspect.

Based on the third aspect, in a possible implementation manner, the chip further includes a processor, configured to access the data stored in the cache system, and store the processed data to the cache system.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a cache system according to an embodiment of the present application;

fig. 2 is a schematic diagram illustrating a mapping relationship between a memory page and a cache page according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a cache according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a cache according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a cache according to an embodiment of the present application;

fig. 6 is a schematic diagram of a data unit occupied by dirty data stored in the cache page B shown in fig. 3 according to an embodiment of the present application;

fig. 7 is a schematic diagram of a data unit occupied by dirty data stored in the cache page a shown in fig. 3 according to an embodiment of the present application;

fig. 8 is a schematic diagram of a data unit in a cache page occupied by data in a memory page to be stored according to an embodiment of the present application;

fig. 9 is a flowchart of a caching method according to an embodiment of the present application;

fig. 10 is a further flowchart of a caching method according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a cache apparatus according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

Reference herein to "modules" generally refers to a logically partitioned functional structure, and the "modules" may be implemented by pure hardware or a combination of hardware and software.

In the embodiments of the present application, the words "exemplary" or "such as" are used to indicate examples, illustrations or descriptions. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion. In the description of the embodiments of the present application, the meaning of "a plurality" means two or more unless otherwise specified. For example, a plurality of pages refers to two or more pages; the plurality of index information means two or more data information.

Referring to fig. 1, a schematic diagram of a cache system applied to the present application is shown.

In fig. 1, a cache system 100 includes a processor, a storage controller, a cache, and a memory. The memory stores data required by the processor to operate. The cache stores part of data stored in the memory. The processor may initiate data access requests and perform data processing. The storage controller controls data interaction between the processor and the cache and between the cache and the memory based on a data access request initiated by the processor. Under the control of the storage controller, data in the memory may be written to the cache, provided to the processor, or written to the memory.

After the processor initiates a data access request, the memory controller may detect whether data is present in the cache based on the data access request. If the data accessed by the processor is stored in the cache, the storage controller controls the cache to provide the data to the processor through the bus; if the data accessed by the processor is not stored in the cache, the storage controller may control the data to be fetched from the memory and provided to the processor. In addition, the data can be written into the cache after being taken out of the memory, so that the processor can directly acquire the data from the cache next time.

The cache, as shown in FIG. 1, may include a multi-level cache structure, such as L1, L2, and L3 levels. When the processor accesses data, the processor can firstly access the L1 level cache, when the L1 level cache is not hit, the processor can continue to access the L2 level cache, when the L2 level cache is not hit, the processor can continue to access the L3 level cache, and when the L3 level cache is not hit, the processor can obtain the data from the memory. That is, for the L1 level cache, the L2 level cache and the L3 level cache are the next level caches; for an L2 level cache, the L3 level cache is the next level cache. When data write-back is needed, for example, when data stored in the L1 level needs to be written back, the data can be written back to the L2 level cache, the L1 level cache or the memory; when the data stored in the L3 level needs to be written back, the data can only be written back to the memory. The L1 level cache, the L2 level cache, and the L3 level cache may be caches having the same cache structure but different data capacities. The cache shown in FIG. 1 does not distinguish between L1 level, L2 level, and L3 level caches.

In the cache shown in fig. 1, the cache space in each level of cache is allocated at a granularity of a page. In particular, the cache space of each level of cache may be divided into a plurality of pages. Pages in the cache are collectively referred to as cache pages in the following description. In some implementations, a cache page may also be understood as a cache line. The memory space of the memory may also be divided into a plurality of pages based on a similar logical structure as the cache space. In the following description, the same page in the memory is referred to as a memory page. The storage capacity of one memory page may be the same as the storage capacity of one cache page. The data stored in the same cache page may be from the same memory page or from different memory pages. In addition, there is a mapping relationship between the memory pages and the cache pages, which is associated by the Set. That is to say, data stored in a plurality of memory pages may be simultaneously stored in cache pages corresponding to the same Set in the cache, and the pages cached in the same Set have a competitive relationship. In order to alleviate the contention relationship, each Set may Set a plurality of ways Way, and when none of the cache pages corresponding to the plurality of ways Way have data to be stored, the data stored in the memory page mapped to the same Set may be stored in the cache page corresponding to any Way in the Set. How many ways Way ways in the cache indicate how many ways are set associative. Examples may include, but are not limited to: two groups are connected, four groups are connected, or eight groups are connected.

Specifically, as shown in fig. 2, a schematic diagram of a correspondence relationship between a cache space in the cache and a storage space in the memory is schematically shown. FIG. 2 illustrates a cache as a 2-way set associative. In fig. 2, the cache includes two ways Way0 and Way1, each of which can store two sets of page data. The memory space of the memory may be divided into eight memory pages based on a similar logical structure as the cache space. The data in the memory page 01, the memory page 11, the memory page 21, and the memory page 31 may be respectively and correspondingly stored in the cache page corresponding to the Set0 of the cache, and the data in the memory page 02, the memory page 12, the memory page 22, and the memory page 32 may be respectively and correspondingly stored in the cache page corresponding to the Set1 of the cache.

Furthermore, a page may be divided into a plurality of data units. When Data stored in the memory is stored in the cache, data access is generally performed in units of Data blocks (Data blocks). In the cache, one cache page may store data of all data units in a certain memory page, or may store data of a part of data units in a certain memory page. That is, when data in a certain memory page is written into the cache, only data of a part of data units in the memory page may be cached. For example, when the data that can be stored in one page of the cache or the memory may be 4KB, if one page of the cache or the memory is divided into 32 data units, each data unit may store 128B data. The cache page may only store data stored in a certain memory page partial data unit (e.g., 5 data units).

As shown in fig. 3-5, which respectively show three buffer structures of the buffer shown in fig. 1.

In FIG. 3, the cache may include a Tag Array and a Data Array.

The Data acquired from the memory is stored in the cache page of the Data Array, and the index information for indexing the Data stored in the cache page is stored in the Tag Array. Wherein, the label array and the data array are both an m x n array. The cache position in the Tag Array and the page in the Data Array have a mapping relationship established in advance, that is, after the storage position of the Data in the Data Array is fixed, the position of the corresponding index information in the Tag Array is fixed. In the Tag Array and Data Array, each row represents a Set and each column represents a Way. Each element in the Tag Array is index information, and each element in the Data Array is a cache page. As can be seen from fig. 3, the elements in the Tag Array correspond to the elements in the Data Array one by one, and the index information in the Tag Array is the index information of the Data stored in the corresponding cache page in the Data Array. In the cache shown in fig. 3, the Data stored in each cache page in the Data Array comes from the same memory page.

The following describes the index information stored in the Tag Array. Each index information may include Tag (Tag) information, valid Bits (Valid Bits) information, dirty Bits (Dirty Bits) information, and priority level information. Specifically, the Tag information is used to indicate physical address information of a memory page from which data stored in the cache page is stored in the memory and set information corresponding to the cache page to which the data is stored. And the data from the same memory page has the same Tag information. Dirty bit (Dirty Bits) information, which is used to indicate whether data in a data unit stored in a cache page is Dirty data, if some Bits of the Dirty Bits are set to 0, the data stored in the corresponding data unit is indicated to be clean data, when replacement occurs, the data may not be written back to the off-chip memory for direct invalidation, otherwise if some Bits of the Dirty Bits are set to 1, when replacement occurs, all data in the data unit where the corresponding Dirty data is located need to be written back to the off-chip memory. The dirty data is specifically data stored in the cache and rewritten by the processor. The data is not stored in the memory, and if the dirty data in the cache is overwritten by other data, the data is lost if the dirty data is not written back to the memory. Therefore, when dirty data is overwritten, a write back is required. Valid Bits (Valid Bits) information, which indicates whether each data unit in the cache page stores Valid data, typically, several data units are included in the cache page, and the Valid bit information is represented by several Bits. For example, a cache page includes 32 data elements, which are represented by 32 bits. Further, each bit may include a "0" state and a "1" state. When a bit is "1", it indicates that the data stored in the corresponding data unit is valid; when a bit is "0", it indicates that the data stored in the corresponding data unit is invalid. The priority level information is used to indicate whether or not page replacement is to be preferentially replaced when it occurs. The priority level information PRI includes one of: least Recently Used (LRU) information indicating a least recently used page among the pages currently stored in the cache, the least recently used page being preferentially replaced when the priority level is used; based on Frequency Based Replacement (FBR) information, the Frequency information which is used for indicating and caching accessed in the currently stored page, and when the priority level is used, the page with the lowest use Frequency is replaced preferentially; first In First Out (FIFO) information, which is priority information for storing the page In the cache, and when the priority is used, the page stored In the cache First is replaced preferentially. The method for replacing the page can be selected according to the requirements of the application scene.

Continuing to refer to FIG. 4, a further architectural diagram of the cache shown in FIG. 1 is shown.

In FIG. 4, the cache may include a Tag Array and a Data Array. The Tag Array and the Data Array may be both m × n arrays, a pre-established position mapping relationship exists between the cache position in the Tag Array and the page in the Data Array, and after the storage position of the Data in the Data Array is fixed, the position of the corresponding index information in the Tag Array is fixed. Unlike the cache shown in fig. 3, in the cache shown in fig. 4, the Data stored in each cache page in the Data Array may come from different memory pages. Correspondingly, a plurality of index information are stored at the Tag Array position having a mapping relation with each cache page. Taking fig. 4 as an example, assuming that the data stored in the cache page a is from the memory page 01 and the memory page 11 shown in fig. 2, the Index information Index01 and the Index information Index11 are stored in the storage location having a mapping relationship with the cache page a in the Tag Array. The Index information Index01 is used for indexing data stored in the cache page A and coming from the memory page 01; the Index information Index11 is used to Index the data stored in the cache page a from the memory page 11.

Continuing to refer to FIG. 5, a further architectural diagram of the cache shown in FIG. 1 is shown.

In FIG. 5, the cache may include a Tag Array and a Data Array. Unlike the cache structure shown in fig. 3 and 4, in the cache shown in fig. 4, the tag array is an m × n array, and the data array may be an m × s array, where s is less than or equal to n. That is, the sets (Set) of the Tag Array and the Data Array have the same number, and the number of ways (Way) in the Tag Array is not less than the number of ways (Way) in the Data Array. In FIG. 4, the Tag Array is an Array 2*4, and the Data Array is an Array 2*3. In the cache shown in fig. 5, the data stored in one cache page may be from the same memory page or may be from different memory pages. The index information stored in the Tag Array shown in fig. 5 includes, in addition to the information included in the index information stored in the cache shown in fig. 2, position information indicating a position of a cache page in which Data that can be indexed by the index information is located in the Data Array. The position information may be road (Way) information or (Set, way) information. Which kind of location information is used is selected according to the needs of the application scenario. When the position information may be Way (Way) information, the set in the Tag Array and the set in the Data Array have a predetermined mapping relationship. For example, the index information stored in the Set0 in the Tag Array is used to index the data stored in each cache page in the Set0 in the data Array. When the above-mentioned position information is (Set, way) information, the index information of the data held by each cache page in the data Array may be stored at any position in the Tag Array. When performing Tag information retrieval, tag information of data to be accessed needs to be compared with Tag information in all index information in the Tag Array one by one.

Based on the cache structures shown in fig. 3 to 5, assuming that the cache is in a full storage state, if the Data stored in the memory page is stored in the cache, and the Data to be cached and the Data currently stored in each cache page are from different memory pages, at this time, a cache page needs to be selected from the Data Array to store the Data to be cached in the cache page, and when the Data to be cached is stored in the selected cache page, the original Data stored before the cache page is usually covered. In the conventional caching technology, cache pages for storing data to be overwritten are generally selected based on priority information, such as LRU information or FIFO information, of data stored in each cache page. Before storing the data to be cached in the cache, dirty data in the overwritten data needs to be written back (for example, to the memory or to the next-level cache). As the cache capacity increases, the amount of valid data and the amount of dirty data stored in a cache page may be larger. The selection of the data to be overwritten using LRU information or FIFO information or the like does not take into consideration the amount of dirty data. When the amount of dirty data in the covered data is large, a large amount of dirty data needs to be written back to the memory or the next-level cache, so that the cache bandwidth is seriously occupied, and the data caching efficiency is reduced. However, some non-selected cache pages may store data that includes less dirty data, and if the page is selected, less dirty data may be written back. Taking the cache shown in fig. 3 as an example, it is assumed that the original data currently stored in the cache page a includes a large amount of dirty data, and the original data currently stored in the remaining cache pages includes less dirty data. Assuming that it is determined that the data stored in the cache page a is the least recently used data based on the LRU information of the data stored in each cache page, a large amount of dirty data in the cache page a needs to be written back. The access bandwidth is seriously occupied. If the data to be cached is stored in the cache page B, less dirty data may need to be written back, so that the occupation of the memory access bandwidth can be reduced, and the data caching efficiency can be improved.

Based on this, in the cache system shown in the embodiment of the present application, when data is stored in all cache pages and the data to be cached needs to be overwritten on the original data stored in the cache, the use condition of the cache bandwidth may be determined by counting the number of times of the access request sent by the processor in a unit time, and then the cache page is selected based on the use condition of the cache bandwidth, so that the data to be cached is stored in the selected cache page. In specific implementation, the cache page with lower dirty data in the stored data can be selected in a time period with higher data transmission quantity, so that the occupancy rate of the access bandwidth can be reduced, and the data cache efficiency and the data access efficiency of the processor can be improved.

In the cache system as shown in fig. 1, a first counter is further included. The first counter is used for counting the number of times of the access requests sent by the processor in unit time. The unit time here may be, for example, 1s, or may be one clock cycle in the cache system.

The following takes the cache structure shown in fig. 3 as an example, and a cache method of the cache system 100 shown in this embodiment of the present application is described in detail.

When the Data stored in the memory page 21 shown in fig. 2 needs to be stored in the cache page, it is assumed that the Data stored in the memory page 21 needs to be stored in the cache page corresponding to the Set0 in the Data Array based on the mapping relationship between the memory page and the cache page shown in fig. 2. At this time, the storage controller may query whether the cache page corresponding to the Set0 in the Data Array is in a full storage state.

In a specific implementation, the storage controller may query whether each storage location in the Tag Array stores index information, so as to determine whether the cache is in a full storage state. In some other implementations, the storage controller may also query whether each cache page in the Data Array stores Data to determine whether the cache is in a full storage state. Assume that each storage location in the Tag Array currently holds index information, as shown in FIG. 3. I.e. the buffer is in a full storage state at this time.

Then, the memory controller may acquire the number of access requests sent by the processor per unit time from the first counter. Here, the access request sent by the processor may include reading data from a cache or a memory, or may include writing data to a cache or a memory. The memory controller may select a cache page from the cache shown in fig. 2 to hold data to be cached based on the number of access requests sent by the processor per unit time.

When the number of the access requests sent by the processor in the unit time is smaller than the first threshold, it indicates that the frequency of the processor accessing the memory or the cache is low, at this time, the occupancy rate of the cache bandwidth used for data transmission with the processor in the cache is low, and the data volume transmitted by the cache bandwidth is within an affordable range. At this time, in order to improve the access hit rate of the processor, the memory controller may select a cache page for storing data to be cached based on the priority information.

Specifically, the storage controller may query the priority information of each Index information Index stored at the storage location corresponding to the Set0 in the Tag Array to determine the priority of the data that can be indexed by each Index information Index. Wherein the priority information may include one of: LRU information, FIFO information, or FBR information. Specifically, the LRU information in each index information is pre-calculated by the memory controller through the LRU algorithm. For example, the data usage within a preset time period from the current time period may be sorted (the data usage is usually reflected by the number of times that the processor accesses the cache page for storing the data), and corresponding LRU information may be set for the data stored in each cache page based on the sorting. In addition, the FIFO information and the FBR information may also be determined in advance by using their respective algorithms, and are not described herein again. It is assumed that the priority level of the data stored in the cache page B shown in fig. 3 is determined to be the lowest by querying the Index information Index of each page. At this time, the storage controller may store the Data stored in the memory page 21 to be cached in the cache page B of the Data Array, and then update the index information used for indexing the Data stored in the cache page B in the Tag Array. That is, the Index information Index11 stored before is updated to the Index information Index21.

It should be noted that before the data stored in the memory page 21 is stored in the cache page B, dirty data in the data stored in the cache page B needs to be written back to the memory or written back to the next-level cache.

When the number of the access requests sent by the processor in the unit time is greater than or equal to the first threshold, it indicates that the frequency of the processor accessing the memory or the cache is high, and the cache bandwidth and the occupancy rate of the interface for data transmission with the processor in the cache are high. And if the priority information selection mode is adopted, the selected covered data is the data in the cache page B. Assume that cache page B includes 32 data units, of which 25 currently stored data are valid data, and of the 25 data units, 20 currently stored data are dirty data, as shown in fig. 6. Before storing the data stored in the memory page 21 to be cached into the cache, all dirty data stored in the 20 data units need to be written back. In this case, too much bandwidth resources are occupied by writing back dirty data, and since the buffer bandwidth and the amount of data that can be transmitted by the interface are limited in a unit time, data congestion may be caused, and the data access efficiency of the processor and the storage efficiency of the buffer memory are reduced, thereby reducing the operating rate of the device or the system. Assuming that data stored in 20 data units in the current cache page a is valid data, and data stored in 5 data units in the 20 data units is dirty data, the data storage condition of each data unit in the cache page a is as shown in fig. 7. If the data to be cached is stored in the cache page A, only the smudges stored in 5 data units need to be written back, and the bandwidth pressure can be greatly relieved at the moment.

It should be noted that the data unit occupied by the data stored in the page is represented by the valid bit information in the index information. Wherein, each bit in the valid bit information represents a data unit, 0 represents that the data stored in the data unit is valid, and 1 represents that the data stored in the data unit is invalid. For example, when a cache page includes 32 data units, both the valid bit information and dirty bit information in the index information may be represented by 32 bits. When data stored in a certain data unit is valid, a bit indicating the data unit in the valid bit information may be set to be valid (e.g., set to "1"); when a data unit is invalid, the corresponding valid bit of the data unit may be set to invalid (e.g., to "0"). In addition, only when the data stored in a certain data unit is valid and has dirty data, the data stored in the data unit needs to be written back.

Therefore, when the frequency of accessing the memory or the cache by the processor is high, the storage controller can select the page with the least dirty data for data storage in order to avoid data congestion caused by excessive dirty data write-back. Specifically, dirty bit information in each index information stored in the Tag Array may be queried, and a cache page with the least dirty data may be selected.

It is assumed that dirty bit information in Index information Index01 for indexing data in cache page a shown in fig. 3 is: 00000000000000001100110000000000, the dirty bit information in Index information Index11 for indexing the data in cache page B shown in fig. 3 is: 00000001111110001100110000000000. in the dirty bit information, each bit represents a data unit, "0" represents that dirty data is not stored in the data unit, and "1" represents that dirty data is stored in the data unit. By comparing the dirty bit information in the Index information Index01 with the dirty bit information in the Index information Index11, it can be determined that the cache page a indexed by the Index information Index01 stores the least dirty data. At this time, the memory controller may store the data stored in the memory page 21 to be cached into the cache page a, and then update the index information used for indexing the data stored in the cache page a in the Tag Array. That is, the Index information Index01 stored before is updated to the Index information Index21. It should be noted that before the data stored in the memory page 21 is stored in the cache page a, the dirty data previously stored in the cache page a needs to be written back to the memory or written back to the next-level cache.

It should be noted that the first threshold of the number of access requests sent by the processor in a unit time shown in the embodiment of the present application may be determined based on the maximum number of accesses that can be received by the cache in the unit time. When the maximum access times that can be carried out by the cache are higher, the first threshold value can be increased; the first threshold may be lowered when the maximum number of accesses that the cache can accommodate is low.

In another possible implementation manner, when the number of times of the access requests sent by the processor in the unit time is greater than or equal to the first threshold, the storage controller may further select a cache page to store the data based on the cache access amount in the unit time and the memory access amount in the unit time.

The cache system 100 may further include a second counter and a third counter, where the second counter is used to count the cache access amount in a unit time; the third counter is used for counting the memory access amount in unit time. The cache access amount can be cache hit times or data transmission amount between the cache and the processor; the memory access amount may be the number of times the processor accesses the memory or the amount of data transfer between the memory and the processor. In addition, when the cache access amount and the memory access amount are the number of cache hits and the number of times that the processor accesses the memory, respectively, the above may be only provided with a second counter for counting the number of cache hits, and the number of times that the processor accesses the memory may be determined by subtracting the number of cache hits from the number of times of access requests sent by the processor.

In a specific implementation, when the cache access amount is the number of cache hits and the memory access amount is the number of times that the processor accesses the memory, the second threshold may be a ratio of the maximum number of accesses that the cache can carry in a unit time to the maximum number of accesses that the memory can carry in the unit time; when the cache access amount is a data transmission amount between the cache and the processor, and the memory access amount is a data transmission amount between the memory and the processor, the second threshold may be a ratio between a maximum data transmission rate of the cache and a maximum data transmission rate of the memory per unit time.

The memory controller may obtain the cache access amount per unit time from the second counter and obtain the memory access amount per unit time from the third counter. The ratio of the cache access amount to the memory access amount is then determined. When the ratio is smaller than or equal to the second threshold, the hit rate of the processor accessing the cache is low at this time, a large amount of data needs to be obtained from the memory, and the cache page can be selected based on the priority information at this time, so that the cache hit rate is improved; when the ratio is greater than the second threshold, it indicates that the cache bandwidth is overloaded, and a cache page with the least dirty data may be selected for data storage.

In this embodiment, the memory controller may obtain the number of access requests sent by the processor per unit time from the first counter. When the number of the access requests sent by the processor in the unit time is smaller than the first threshold, the cache page can be selected to store the data to be stored by inquiring the priority information in the index information stored in the cache. When the number of times of the access request sent by the processor in the unit time is greater than or equal to the first threshold, the storage controller may obtain the cache access amount in the unit time from the second counter, obtain the memory access amount in the unit time from the third counter, and determine a ratio between the cache access amount and the memory access amount. When the ratio of the cache access amount to the memory access amount is smaller than a second threshold, a cache page can be selected to store the data to be stored by inquiring the priority information in the index information stored in the cache; when the ratio of the cache access amount to the memory access amount is greater than or equal to a second threshold, the page with the least dirty data can be selected for data storage. Therefore, the cache hit rate and the bandwidth occupancy rate can be further considered, and the cache efficiency is further improved.

The above describes how the cache system according to the embodiment of the present application selects a cache page when each cache page in the cache stores data, so as to store the data in the to-be-stored memory into the selected cache page. The above implementation may be applied to any cache structure shown in fig. 3 to 5.

In the cache structure shown in fig. 5, since the memory pages in the Data Array and the storage locations in the Tag Array are unbound, they may have different Array numbers, and there is a case where each cache page in the Data Array stores Data, and there may be a free storage location in the Tag Array where no Tag information is stored, as shown in fig. 5. At this time, data stored in different memory pages needs to be stored in the same cache page. For a data unit in a cache page, if the data unit is used to store data stored in a first memory page, the data unit may not be used to store data stored in a second memory page. If there is data to be stored in the data unit in the first memory page, the data stored in other memory pages previously stored in the data unit needs to be overwritten.

Based on the above scenario, in this embodiment of the application, when the number of access requests sent by the processor in a unit time is greater than or equal to the first threshold, the cache page may be selected to store the data to be cached based on the valid bit information of the data to be cached, the valid bit information of the data stored in the cache page, and the dirty bit information.

Specifically, when data stored in the memory page 01 needs to be stored in a cache page, it is assumed that the memory page 01 and the cache page corresponding to the Set0 in the cache have a mapping relationship. At this time, the Data stored in the memory page 01 needs to be stored in the cache page corresponding to the Set0 in the Data Array. The storage controller can inquire the cache page corresponding to the group Set0 in the Data Array and the storage position corresponding to the group Set0 in the Tag Array, and inquire that the cache page corresponding to the group Set0 in the Data Array stores Data and the storage position corresponding to the group Set0 in the Tag Array also has an idle position. At this time, the memory controller may determine valid dirty bit information in the data stored in each cache page based on the valid bit information and the dirty bit information of the data stored in each corresponding cache page in the Set0 (only valid dirty data needs to be written back, and when dirty data is invalid, write back may not be needed). Then, the memory controller may select the page with the least conflict with the memory page 01 based on the valid bit information of the data stored in the memory page 01 to be cached and the valid dirty bit information of the data stored in the cache page corresponding to the Set 0. The conflict here means that when the data stored in the memory page 01 to be cached is stored in the cache page a, the data unit occupied by the occupied cache page a conflicts with the data unit occupied by the currently stored effective dirty data in the cache page. For example, a data unit occupied by data stored in the memory page 01 to be cached is as shown in fig. 8, and correspondingly, the valid bit information is: 0xFF0E410. In fig. 5, it is assumed that valid bit information of the data stored in the cache page B is 0xC975a450, dirty bit information is 0x00700060, and valid dirty bit information is 0x00700040; the valid bit information of the data stored in the cache page C is 0xFF8DAC20, the dirty bit information is 0x06980020, and the valid dirty bit information is 0x06880020. Therefore, it can be determined that the data unit occupied by the data stored in the cache page B and the data unit occupied by the data stored in the memory page 01 to be cached have the least conflict, and thus the data stored in the memory page 01 to be cached can be stored in the cache page B. It should be noted that before the data stored in the memory page 01 to be cached is stored in the cache page B, the valid dirty data covered in the cache page B needs to be written back to the memory or written back to the next-level cache. In addition, the index information Inedx02 stored in the cache needs to be updated. Specifically, the valid bit information and dirty bit information in the index information Inedx02 are updated.

In an example of an embodiment of the present application, the cache, the memory controller, and the processor may be integrated on the same chip, forming a System On Chip (SOC). In addition, the processor and the cache may be integrated on the same chip, and the memory controller may be integrated on another chip. In practical applications, the cache may also be integrated in a different chip from the processor, the off-chip cache adopts the same storage structure design as the on-chip cache provided in the embodiment of the present application and achieves the same function as the on-chip cache provided in the embodiment of the present application, and the off-chip cache should also be considered to fall within the protection scope of the embodiment of the present application.

Based on the cache system shown in fig. 1, the mapping relationship between the memory page and the cache page shown in fig. 2, and the cache structures shown in fig. 3 to fig. 5, an embodiment of the present application further provides a cache method, where the cache method is applied to the storage controller shown in fig. 1. Continuing to refer to fig. 9, a flow 900 of a caching method provided by an embodiment of the present application is shown, where the flow 900 of the caching method includes the following steps:

step 901, receiving a data read request, and determining data to be written into the cache from the memory based on the data read request.

In this embodiment, the data read request usually carries address information of the data to be read, where the address information includes Tag information Tag, group information Set, and the like. The cache controller searches the Tag Array by using the Set information Set based on the instruction sent by the processor, and finds a plurality of index information in the Set group. Then, the cache controller may continue to search whether one of the index information includes Tag information carried in the data read request. If the Tag information carried in the data reading request is not included in any index information, a Tag miss is indicated. I.e. the cache does not hold the data to be read by the processor. At this time, the storage controller needs to obtain the data to be read by the processor from the memory.

Then, the storage controller may further determine that the data needs to be written into the cache from the memory based on Tag information carried in the data read request. That is, the location information of the memory page for storing the data to be written in the memory is determined. Then, based on the mapping relationship between the memory page and the cache page as shown in fig. 2, a plurality of cache pages for storing data to be written are determined.

And then, detecting whether the data are stored in the plurality of cache pages. When it is detected that data is stored in all of the plurality of cache pages, in order to avoid that a large amount of dirty data is stored in the selected cache page for storing the data to be written, when the data to be read covers the original data stored in the selected cache page, a large amount of dirty data needs to be written back to the memory or the next-level cache, so that the cache bandwidth is seriously occupied, and the data caching efficiency is reduced. At this point, step 902 may be performed.

Step 902, obtaining the number of times of data access requests received in a unit time.

The memory controller may determine the number of data access requests received per unit of time. Specifically, a first counter as shown in fig. 1 may be provided in the memory controller. The first counter is used for counting the number of times of data access requests received in unit time. The unit time may also be referred to herein as a clock cycle. The unit time may be, for example, 1s or 30ms, and is not particularly limited.

The memory controller may acquire the number of data access requests received per unit time from the first counter. Typically, the data access request is processor initiated. It may be a data read request and may be a data write request. When the processor sends a data access request to the memory controller, the counter may be incremented by 1.

Step 903, selecting a first page from the cache based on the number of data access requests received in unit time.

In the embodiment of the present application, a first threshold may be preset in the storage controller, and the first threshold may also be referred to as a maximum access count value in a unit time. The maximum number of accesses per unit time may be set based on a buffer bandwidth, a buffer capacity, or the like.

When the number of data access requests received in unit time is smaller than a first threshold, the frequency of accessing the memory or the cache by the processor is low, the occupancy rate of the cache bandwidth for data transmission with the processor in the cache is low, and the data volume transmitted by the cache bandwidth is enough to be in an affordable range. At this time, in order to improve the access hit rate of the processor, the memory controller may select a cache page for storing data to be read, based on the determined priority information of the data stored in each cache page. The priority level information may include one of: LRU information, FIFO information, or FBR information.

When the number of data access requests received in unit time is greater than or equal to a first threshold, it indicates that the frequency of accessing the memory or the cache by the processor is high, and the cache bandwidth and the interface occupancy rate for data transmission with the processor in the cache are high. If the priority information selection method is adopted, a large amount of valid data may exist in the selected overlaid data, and the large amount of valid data includes a large amount of dirty data. The writing back of dirty data also occupies too much bandwidth resources, and since the buffer bandwidth and the data volume which can be transmitted by the interface in unit time are limited, data congestion may be caused, the data access efficiency of the processor and the storage efficiency of the buffer memory are reduced, and further the running speed of the device or the system is reduced. At this time, in order to avoid data congestion caused by writing back excessive dirty data, the memory controller may select a page with the least dirty data for data saving. Specifically, the cache page for storing the data to be read may be selected based on the determined data dirty bit information stored in each cache page.

At step 904, the data to be written from the memory into the cache is stored in the selected first page.

According to the caching method disclosed by the embodiment of the application, when data are stored in the cache pages and the data to be cached needs to cover the original data stored in the cache, the use condition of the cache bandwidth can be determined by counting the number of times of access requests sent by the processor in unit time, and then the cache pages are selected based on the use condition of the cache bandwidth so as to store the data to be cached into the selected cache pages. In specific implementation, the cache page with lower dirty data in the stored data can be selected in a time period with higher data transmission quantity, so that the occupancy rate of the access bandwidth can be reduced, and the data cache efficiency and the data access efficiency of the processor can be improved.

Continuing to refer to fig. 10, a flow chart of yet another embodiment of the caching method provided by the present application is shown. The process 1000 of the caching method includes:

step 1001, receiving a data read request, and determining data to be written into a cache from a memory based on the data read request.

Step 1002, obtaining the number of times of data access requests received in unit time.

The specific implementation of step 1001 and step 1002 may refer to the related description of step 901 and step 902 shown in fig. 9, and is not described herein again.

Step 1003 determines whether the number of data access requests is greater than or equal to a first threshold. When it is determined that the number of data access requests is less than the first threshold, performing step 1004; when it is determined that the number of data access requests is equal to or greater than the first threshold, step 1005 is performed.

Step 1004, selecting a first page for storing the data to be written based on the determined priority information of the data stored in each cache page.

In step 1005, it is determined whether the ratio between the cache access amount in unit time and the memory access amount in unit time is greater than or equal to a second threshold.

When the number of times of the received data access requests in the unit time is larger than or equal to the first threshold, the memory controller selects a cache page for storing the data to be read based on the cache access amount in the unit time and the memory access amount in the unit time. The cache access amount includes one of: the number of cache hits or the amount of data transfer between the cache and the processor; the memory access amount includes one of: the number of memory accesses or the amount of data transferred between the memory and the processor.

Specifically, the cache system 100 shown in fig. 1 further includes a second counter and a third counter, where the second counter is used to count the cache access amount in a unit time; the third counter is used for counting the memory access amount in unit time. In addition, when the cache access amount and the memory access amount are the number of cache hits and the number of times that the processor accesses the memory, respectively, the above may be only provided with one second counter, and the third counter is not provided, where the second counter is used to count the number of cache hits, and the number of times that the processor accesses the memory may be determined by subtracting the number of cache hits from the number of times of access requests sent by the processor.

The memory controller may obtain the cache access amount per unit time from the second counter and obtain the memory access amount per unit time from the third counter. The ratio of the cache access amount to the memory access amount is then determined.

When the cache access amount is the number of cache hits and the memory access amount is the number of times that the processor accesses the memory, the second threshold may be a ratio of the maximum number of accesses that the cache can carry in the unit time to the maximum number of accesses that the memory can carry in the unit time; when the cache access amount is a data transmission amount between the cache and the processor, and the memory access amount is a data transmission amount between the memory and the processor, the second threshold may be a ratio between a maximum data transmission rate of the cache and a maximum data transmission rate of the memory per unit time.

When the ratio between the cache access amount and the memory access amount is smaller than the second threshold, step 1004 is executed; when the ratio between the cache access amount and the memory access amount is greater than or equal to the second threshold, step 1006 is executed.

When the ratio between the cache access amount and the memory access amount is smaller than the second threshold, it indicates that the hit rate of the processor accessing the cache is low at this time, and a large amount of data needs to be acquired from the memory, and at this time, the replaced page may be determined from the cache based on the priority information, so as to improve the cache hit rate.

Step 1006, based on the position information of the page in the cache occupied by the data that needs to be written into the cache from the memory and the position information of the dirty data stored in each page in the cache, selecting a first page for storing the data to be written.

When the ratio is larger than or equal to the first threshold value, the cache bandwidth is overloaded. At this time, one of the cache pages is selected from the determined cache pages according to the valid bit information and dirty bit information of the data stored in the determined cache pages and the position information of the data unit in the cache page occupied by the data to be read, and then the data to be read is stored in the selected cache page.

As can be seen from the embodiment shown in fig. 10, by further introducing the ratio between the cache access amount and the memory access amount to select the first page to store data, the cache hit rate and the bandwidth occupancy rate can be further considered, so as to further improve the cache efficiency.

In addition, in a possible implementation manner of this embodiment, for example, in the cache structure shown in fig. 5, when all cache pages store data, and the Tag Array shown in fig. 5 stores index information. When the data to be read is stored in one of the cache pages, the original data stored before the cache page is covered by the data to be read. And the label Array Tag Array still stores the index information of the original data stored in the cache page. At this time, the index information of the original data stored before needs to be updated to the index information of the data to be read.

Further, in a possible implementation manner of this embodiment, for example, in the cache structure shown in fig. 5, when all cache pages store data, and there is a free position in the Tag Array shown in fig. 5 where no index information is stored. At this time, after the data to be read is stored in one of the cache pages and the index information of the data to be read is stored in the free position in the Tag Array, the position information of the free data unit in the cache page for storing the data to be read can also be obtained. And then updating the second index information stored in the cache according to the position information of the free data unit. The second index information is used for indexing the original data in the free data unit.

It will be appreciated that the storage controller, in order to implement the above-described functionality, may include corresponding hardware and/or software modules that perform the respective functions. The present application can be realized in hardware or a combination of hardware and computer software in connection with the exemplary algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, with the embodiment described in connection with the particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In this embodiment, the memory controller may be divided into functional modules according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one cache control module. The integrated module may be implemented in the form of hardware. It should be noted that the division of the modules in this embodiment is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

In the case of dividing each functional module by corresponding functions, fig. 11 shows a schematic diagram of a possible composition of the memory controller 1100 involved in the above embodiments, and as shown in fig. 11, the memory controller 1100 may include: the device comprises a receiving module 1101, an obtaining module 1102, a selecting module 1103 and a saving module 1104.

The receiving module 1101 is configured to receive a data reading request, and determine, based on the data reading request, data that needs to be written into a cache from a memory; an obtaining module 1102, configured to obtain the number of times of data access requests received in unit time; a selecting module 1103, configured to select a first page from the cache based on the number of times of the data access request; a saving module 1104, configured to save the data that needs to be written from the memory into the cache in the first page.

In one possible implementation, the selecting module 1103 is further configured to: in response to the number of data access requests being greater than or equal to a first threshold, selecting the first page from the cache based on dirty data stored in pages in the cache.

In one possible implementation, the selecting module 1103 is further configured to: and responding to the data access request, wherein the number of times is larger than or equal to a first threshold, and the first page is selected based on the cache access amount in unit time and the memory access amount in unit time.

In one possible implementation, the cache access amount includes one of: the number of cache hits or the amount of data transfer between the cache and the processor; the memory access amount includes one of: the number of memory accesses or the amount of data transferred between the memory and the processor.

In one possible implementation, the selecting module 1103 is further configured to: determining a ratio between the cache access amount and the memory access amount; and selecting the first page from the cache based on the ratio of the cache access amount to the memory access amount.

In one possible implementation, the selecting module 1103 is further configured to: and in response to the fact that the ratio of the cache access amount to the memory access amount is larger than or equal to a second threshold value, selecting the first page from the cache based on the position information of the page in the cache occupied by the data needing to be written into the cache from the memory and the position information of the dirty data stored in each page in the cache.

In one possible implementation, the selecting module 1103 is further configured to: in response to the fact that the ratio of the cache access amount to the memory access amount is smaller than the second threshold value, selecting the first page from the cache based on priority information of data stored in each page in the cache; the priority level comprises one of: least recently used information, first-in-first-out information, or access frequency information.

In a possible implementation manner, the storage controller 1100 further includes a first updating module (not shown in the figure), configured to update the first index information stored in the cache, where the first index information is used to index the data to be read stored in the first page.

In one possible implementation, the storage controller 1100 further includes a second update module (not shown in the figure): the second updating module is configured to obtain location information of an idle data unit in the first page, and update second index information stored in the cache according to the location information, where the second index information is used to index original data in a data unit corresponding to the location information in the first page.

The storage controller 1100 provided in this embodiment is configured to execute the caching method executed by the storage controller shown in the caching system 10, and may achieve the same effect as the above implementation method.

Among other things, the storage controller may implement or execute the various exemplary logic modules described in connection with the present disclosure. The memory controller may also be a combination of components that perform computing functions, including, for example, an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, or discrete hardware components.

Through the description of the above embodiments, those skilled in the art will understand that, for convenience and simplicity of description, only the division of the above functional modules is used as an example, and in practical applications, the above function distribution may be completed by different functional modules as needed, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions.

In several embodiments provided in the present application, it should be understood that the disclosed caching apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, and the indirect coupling or communication connection of the devices may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed to a plurality of different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partially contributed to by the prior art, or all or part of the technical solutions may be embodied in the form of a software product, where the software product is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned readable storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A caching method, comprising:

receiving a data reading request, and determining data needing to be written into a cache from a memory based on the data reading request;

acquiring the number of times of data access requests received in unit time;

selecting a first page from the cache based on the number of data access requests;

and storing the data needing to be written into the cache from the memory in the first page.
The caching method of claim 1, wherein the selecting the first page from the cache based on the number of data access requests comprises:

in response to the number of data access requests being greater than or equal to a first threshold, selecting the first page from the cache based on dirty data stored by pages in the cache.
The caching method of claim 1, wherein the selecting the first page from the cache based on the number of data access requests comprises:

and responding to the data access request, wherein the number of times of the data access request is greater than or equal to a first threshold, and the first page is selected based on the cache access amount in unit time and the memory access amount in unit time.
The caching method of claim 3,

the cache access amount comprises one of: the number of cache hits or the amount of data transferred between the cache and the processor;

the memory access amount includes one of: the number of memory accesses or the amount of data transferred between the memory and the processor.
The caching method according to claim 3 or 4, wherein the selecting the first page based on the cache access amount per unit time and the memory access amount per unit time comprises:

determining a ratio between the cache access amount and the memory access amount;

and selecting the first page from the cache based on the ratio of the cache access amount to the memory access amount.
The caching method according to claim 5, wherein the selecting the first page from the cache based on a ratio between the cache access amount and the memory access amount comprises:

and in response to the fact that the ratio of the cache access amount to the memory access amount is larger than or equal to a second threshold value, selecting the first page from the cache based on the position information of the page in the cache occupied by the data needing to be written into the cache from the memory and the position information of the dirty data stored in each page in the cache.
The caching method according to claim 6, wherein the selecting the first page from the cache based on a ratio between the cache access amount and the memory access amount comprises:

in response to that the ratio of the cache access amount to the memory access amount is smaller than the second threshold, selecting the first page from the cache based on priority information of data stored in each page in the cache;

the priority level comprises one of: least recently used information, first-in-first-out information, or access frequency information.
A cache system, comprising:

the cache is used for storing data from the memory and index information used for indexing the data stored in the cache;

a storage controller to: receiving a data reading request, and determining data needing to be written into a cache from a memory based on the data reading request; acquiring the number of times of data access requests received in unit time; selecting a first page from the cache based on the number of data access requests; and storing the data needing to be written into the cache from the memory in the first page.
The cache system of claim 8, further comprising a first counter;

the first counter is used for counting the number of data access requests received by the storage controller in unit time.
The cache system of claim 9, further comprising a second counter;

the second counter is used for counting the cache access amount of the storage controller in unit time;

wherein the cache access amount comprises one of: the number of cache hits or the amount of data transferred between the cache and the processor.
The cache system of claim 10, further comprising a third counter;

the third counter is used for counting the memory access amount of the memory controller in unit time;

wherein the memory access amount comprises one of: the number of memory accesses or the amount of data transferred between the memory and the processor.
A chip, characterized in that it comprises a cache system according to any of claims 8-11.
The chip of claim 12, further comprising:

and the processor is used for accessing the data stored in the cache system and storing the processed data to the cache system.