CN115668153A - 闪存控制方法和装置 - Google Patents
闪存控制方法和装置 Download PDFInfo
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- CN115668153A CN115668153A CN202080101642.4A CN202080101642A CN115668153A CN 115668153 A CN115668153 A CN 115668153A CN 202080101642 A CN202080101642 A CN 202080101642A CN 115668153 A CN115668153 A CN 115668153A
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- ftl
- ppn
- lba
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Memory System (AREA)
Abstract
本申请提供了一种闪存控制方法和装置,该装置包括随机存储器,用于存储闪存转换层FTL二级表;控制器,用于接收主机发送的数据访问指令,所述数据访问指令包括目标数据的目标逻辑块地址LBA;在所述FTL二级表的第一条目指示的LBA地址段对应的物理页号PPN连续,并且所述第一条目对应有效数据空间的情况下,根据所述目标LBA和所述第一条目中的起始PPN访问所述目标数据,所述起始PPN是所述第一条目指示的LBA地址段中第一个LBA对应的PPN。该闪存控制装置可以通过FTL二级表的信息直接访问目标数据,无需加载和替换FTL一级表,提高了数据访问的效率。
Description
PCT国内申请,说明书已公开。
Claims (15)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2020/106229 WO2022021337A1 (zh) | 2020-07-31 | 2020-07-31 | 闪存控制方法和装置 |
Publications (1)
Publication Number | Publication Date |
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CN115668153A true CN115668153A (zh) | 2023-01-31 |
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ID=80037325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN202080101642.4A Pending CN115668153A (zh) | 2020-07-31 | 2020-07-31 | 闪存控制方法和装置 |
Country Status (2)
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CN (1) | CN115668153A (zh) |
WO (1) | WO2022021337A1 (zh) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8364931B2 (en) * | 2009-06-29 | 2013-01-29 | Mediatek Inc. | Memory system and mapping methods using a random write page mapping table |
CN102521160B (zh) * | 2011-12-22 | 2015-04-01 | 上海交通大学 | 写缓冲检测器、并行通道写入方法 |
KR20130084846A (ko) * | 2012-01-18 | 2013-07-26 | 삼성전자주식회사 | 플래시 메모리를 기반으로 하는 저장 장치, 그것을 포함한 사용자 장치, 그리고 그것의 데이터 읽기 방법 |
-
2020
- 2020-07-31 WO PCT/CN2020/106229 patent/WO2022021337A1/zh active Application Filing
- 2020-07-31 CN CN202080101642.4A patent/CN115668153A/zh active Pending
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WO2022021337A1 (zh) | 2022-02-03 |
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