CN115666209B - A packaging method and packaging structure for improving the stability of graphene carrier concentration - Google Patents
A packaging method and packaging structure for improving the stability of graphene carrier concentration Download PDFInfo
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Abstract
Description
技术领域technical field
本发明属于石墨烯器件封装技术领域,特别涉及一种提高石墨烯载流子浓度稳定性的封装方法及封装结构。The invention belongs to the technical field of graphene device packaging, in particular to a packaging method and a packaging structure for improving the stability of graphene carrier concentration.
背景技术Background technique
在低温强磁场环境中,由于钉扎效应,SiC(0001)面外延生长的单层石墨烯呈现出非常宽磁场范围内的量子霍尔平台,其对应的填充因子为2。然而石墨烯为重n掺杂,其载流子浓度通常为1012~1013 cm-2,因此无法在较低的磁场下达到填充因子为2对应的量子霍尔平台。目前已研究出多种调控石墨烯载流子浓度的方法,其中较为常见的方法:使用F4TCNQ(2,3,5,6-四氟-7,7',8,8'-四氰二甲基对苯醌),例如文献1(Form doping of grapheneclose to the Dirac point by polymer-assisted assembly of molecular dopants.Nat. Commun. 9, 3956 (2018))中记载了使用F4TCNQ作为电子受体,将芯片在160 ℃下加热,其载流子浓度的随着加热时间的增加而发生变化,可以将载流子浓度从在1×1013 cm-2降至狄拉克点附近(0 cm-2)。但对于初始载流子浓度偏低的芯片,调控速率过快,无法实现载流子的稳定调控。当采用五层结构时,载流子的稳定性较好,但每层胶均需要加热,匀五层胶大大增加了调控的难度;以及ZEP520A(主要成分是ZEP胶,ZEP胶是一种苯乙烯甲基丙烯酸酯基的电子束正胶),例如文献2(Lara-Avila, S.et al.Non-volatilephotochemical gating of an epitaxial graphene/polymer heterostructure. Adv.Mater. 23, 878-882 (2011)中记载了通过紫外光照可使得ZEP 520A产生大量氯自由基,通过控制紫外光照的计量实现氯自由基形成的数量,从而实现载流子浓度的控制。虽然上述调控方法可以有效降低其载流子浓度,但是调控后的石墨烯在大气环境中均存在载流子浓度不稳定的问题。需将其放置氮气、氩气或真空中才可以有效提高石墨烯芯片载流子浓度的稳定性,进而大大限制了其实际应用。In a low temperature and strong magnetic field environment, due to the pinning effect, the single-layer graphene grown on the SiC (0001) surface exhibits a quantum Hall platform in a very wide magnetic field range, and the corresponding fill factor is 2. However, graphene is heavily n-doped, and its carrier concentration is usually 10 12 ~10 13 cm -2 , so the quantum Hall platform corresponding to the fill factor of 2 cannot be achieved at a relatively low magnetic field. A variety of methods for regulating the carrier concentration of graphene have been studied, among which the more common method is to use F4TCNQ (2,3,5,6-tetrafluoro-7,7',8,8'-tetracyanodimethyl-p-benzoquinone), such as Document 1 (Form doping of grapheneclose to the Dirac point by polymer-assisted assembly of molecular dopants. Nat. Commun. 9, 3956 (2 018)) records that using F4TCNQ as an electron acceptor, heating the chip at 160 °C, the carrier concentration changes with the increase of heating time, and the carrier concentration can be reduced from 1×10 13 cm -2 to near the Dirac point (0 cm -2 ). However, for chips with low initial carrier concentration, the control rate is too fast to achieve stable control of carriers. When the five-layer structure is adopted, the stability of the carriers is better, but each layer of glue needs to be heated, and the uniform five-layer glue greatly increases the difficulty of regulation; and ZEP520A (the main component is ZEP glue, ZEP glue is a styrene methacrylate-based electron beam positive glue), such as literature 2 (Lara-Avila, S.et al.Non-volatile photochemical gating of an epitaxial graphene/polymer heterostructure. Ad It is recorded in v.Mater. 23, 878-882 (2011) that ZEP 520A can produce a large amount of chlorine free radicals by ultraviolet light irradiation, realize the quantity that chlorine free radicals form by controlling the metering of ultraviolet light irradiation, thereby realize the control of carrier concentration.Although the above-mentioned control method can effectively reduce its carrier concentration, the graphene after the regulation all has the unstable problem of carrier concentration in atmospheric environment.Need to place it in nitrogen, argon gas or vacuum and just can effectively improve graphene chip carrying current The stability of sub-concentration greatly limits its practical application.
发明内容Contents of the invention
针对上述现有技术存在的问题,本发明提供了一种提高石墨烯载流子浓度稳定性的封装方法及封装结构。In view of the above-mentioned problems in the prior art, the present invention provides a packaging method and a packaging structure for improving the stability of graphene carrier concentration.
本发明的第一方面提供了一种提高石墨烯载流子浓度稳定性的封装方法,包括以下步骤:First aspect of the present invention provides a kind of encapsulation method that improves graphene carrier concentration stability, comprises the following steps:
S1、制作石墨烯芯片;S1, making graphene chips;
S2、对石墨烯芯片基底进行二次匀胶:首先采用PMMA溶液对石墨烯芯片基底进行第一次匀胶并烘烤;然后采用混合掺杂剂对第一次匀胶后的石墨烯芯片进行第二次匀胶,其中,所述混合掺杂剂为掺有F4TCNQ(2,3,5,6-四氟-7,7',8,8'-四氰二甲基对苯醌)的PMMA;S2, performing secondary leveling on the graphene chip substrate: firstly, using PMMA solution to perform the first leveling and baking on the graphene chip base; then using a mixed dopant to perform a second leveling on the graphene chip after the first leveling, wherein the mixed dopant is PMMA doped with F4TCNQ (2,3,5,6-tetrafluoro-7,7',8,8'-tetracyanodimethyl-p-benzoquinone);
S3、于手套箱中,对二次匀胶后的石墨烯芯片进行封装;S3. In the glove box, the graphene chip after the second glue leveling is packaged;
S4、对完成封装的石墨烯芯片进行调控,以减少石墨烯载流子浓度。S4. Regulating the packaged graphene chip to reduce the graphene carrier concentration.
优选地,步骤S2中,所述烘烤温度为160~180 ℃,烘烤时间为3~6 min。Preferably, in step S2, the baking temperature is 160-180°C, and the baking time is 3-6 min.
优选地,步骤S2中,所述PMMA溶液所用溶剂为苯甲醚,所述PMMA的分子量为920000~980000;所述混合掺杂剂中的F4TCNQ的质量百分比含量为4~7wt%。Preferably, in step S2, the solvent used in the PMMA solution is anisole, the molecular weight of the PMMA is 920000-980000; the mass percentage of F4TCNQ in the mixed dopant is 4-7wt%.
优选地,步骤S3中,对二次匀胶后的石墨烯芯片可采用以下三种方式进行封装:Preferably, in step S3, the following three ways can be used to package the graphene chip after the secondary glue leveling:
(1)采用热熔胶方式进行封装,具体步骤为:于手套箱中,用热熔胶包裹二次匀胶后的石墨烯芯片,然后加热热熔胶使之熔化,再将载玻片盖住热熔胶,整体取下封装后的石墨烯芯片;其中,所述加热温度为90~100 ℃,加热时间为1~5 min;所述封装过程在手套箱内保护性气体或者真空条件下进行,所述保护性气体为氩气或者氮气。(1) Encapsulation with hot-melt adhesive, the specific steps are: in the glove box, use hot-melt adhesive to wrap the graphene chip after secondary uniform glue, then heat the hot-melt adhesive to melt it, then cover the glass slide with the hot-melt adhesive, and remove the encapsulated graphene chip as a whole; wherein, the heating temperature is 90-100°C, and the heating time is 1-5 min; the packaging process is carried out under protective gas or vacuum conditions in the glove box, and the protective gas is argon or nitrogen.
(2)当测试台尺寸明显大于二次匀胶后的石墨烯芯片尺寸时,采用以下方式进行封装,具体步骤为:将印制电路板用低温胶粘在测试台上,并将二次匀胶后的石墨烯芯片用低温胶粘在印制电路板的上方,并用引线将二次匀胶后的石墨烯芯片与印制电路板连接,随后将已放置二次匀胶后的石墨烯芯片和印制电路板的测试台、低温胶以及玻璃罩放入手套箱,并用低温胶以及玻璃罩将二次匀胶后的石墨烯芯片以及引线封装,用引线将印制电路板与测试台连接,从而实现二次匀胶后的石墨烯芯片与测试台之间的连接。(2) When the size of the test bench is significantly larger than the size of the graphene chip after the second glue leveling, the following method is used for packaging. The specific steps are: glue the printed circuit board on the test bench with low-temperature glue, and glue the graphene chip after the second glue leveling on the top of the printed circuit board with low-temperature glue, and connect the graphene chip after the second glue leveling with the printed circuit board. The cover encapsulates the graphene chip after the second glue leveling and the lead, and connects the printed circuit board to the test bench with the lead wire, so as to realize the connection between the graphene chip after the second glue leveling and the test bench.
(3)当测试台的密闭性较高时,采用以下方式进行封装,具体步骤为:于手套箱中,将测试台和二次匀胶后的石墨烯芯片之间用低温胶实现固定,玻璃罩的底部用低温胶实现和测试台之间的固定以及玻璃罩内部的密封,玻璃罩和二次匀胶后的石墨烯芯片之间填充有保护性气体或为真空环境,二次匀胶后的石墨烯芯片和测试台通过引线连接。(3) When the airtightness of the test bench is high, use the following method for packaging. The specific steps are: in the glove box, use low-temperature glue to fix the test bench and the graphene chip after the second glue leveling.
优选地,步骤S4中,所述调控方式为:对完成封装的石墨烯芯片进行加热,加热温度为90~95 ℃,加热时间为2~5 min。由于加热操作可使PMMA发生变形,让电子受体F4TCNQ达到石墨烯表面进而减少石墨烯的载流子浓度。Preferably, in step S4, the control method is: heating the packaged graphene chip, the heating temperature is 90-95 °C, and the heating time is 2-5 min. Since the heating operation can deform PMMA, the electron acceptor F4TCNQ can reach the surface of graphene to reduce the carrier concentration of graphene.
优选地,所述二次匀胶可采用以下方式代替实现;采用PMMA/MMA对石墨烯芯片基底进行第一次匀胶和第一次烘烤, 然后采用ZEP520A对第一次匀胶后的石墨烯芯片进行第二次匀胶和第二次烘烤。Preferably, the second glue leveling can be realized in the following manner instead: use PMMA/MMA to carry out the first glue leveling and the first baking on the graphene chip substrate, and then use ZEP520A to carry out the second glue leveling and the second baking on the graphene chip after the first leveling.
优选地,所述第一次烘烤温度为160~180 ℃,烘烤时间为3~6 min;所述第二次烘烤温度为160~180 ℃,烘烤时间为3~6 min。Preferably, the first baking temperature is 160-180°C, and the baking time is 3-6 minutes; the second baking temperature is 160-180°C, and the baking time is 3-6 minutes.
优选地,步骤S4中,所述调控方式为对完成封装的石墨烯芯片使用紫外灯进行照射,所述紫外灯光的波长为248~260 nm,照射时间为2~5 min。由于紫外光照射可诱导大量氯自由基的形成,氯自由基作为电子受体,能够有效降低石墨烯的载流子浓度。Preferably, in step S4, the control method is to irradiate the packaged graphene chip with an ultraviolet lamp, the wavelength of the ultraviolet light is 248-260 nm, and the irradiation time is 2-5 min. Since ultraviolet light irradiation can induce the formation of a large number of chlorine free radicals, chlorine free radicals, as electron acceptors, can effectively reduce the carrier concentration of graphene.
本发明的第二方面提供了上述封装方法得到的石墨烯芯片封装结构。The second aspect of the present invention provides the graphene chip packaging structure obtained by the above packaging method.
优选地,所述石墨烯芯片封装结构包括:依次层叠的测试台、印制电路板、二次匀胶后的石墨烯芯片、玻璃罩;其中,所述玻璃罩和二次匀胶后的石墨烯芯片之间填充有保护性气体或为真空环境,所述二次匀胶后的石墨烯芯片和印制电路板之间通过引线连接,所述印制电路板和测试台之间通过引线连接。Preferably, the graphene chip packaging structure includes: a test platform stacked in sequence, a printed circuit board, a graphene chip after secondary gluing, and a glass cover; wherein, a protective gas or a vacuum environment is filled between the glass cover and the graphene chip after the secondary gluing, and the graphene chip after the secondary gluing is connected to the printed circuit board by a lead, and the printed circuit board and the test bench are connected by a lead.
优选地,所述测试台和印制电路板之间、以及印制电路板和二次匀胶后的石墨烯芯片之间均通过低温胶实现固定,所述玻璃罩的底部通过低温胶实现和印制电路板之间的固定以及玻璃罩内部的密封。Preferably, between the test bench and the printed circuit board, as well as between the printed circuit board and the graphene chip after secondary glue leveling, the fixation is realized by low-temperature glue, and the bottom of the glass cover is fixed with the printed circuit board and sealed inside the glass cover by low-temperature glue.
优选地,所述石墨烯芯片封装结构包括:依次层叠的测试台、二次匀胶后的石墨烯芯片、玻璃罩;其中,所述玻璃罩和二次匀胶后的石墨烯芯片之间填充有保护性气体或为真空环境,所述二次匀胶后的石墨烯芯片和测试台之间通过引线连接。Preferably, the graphene chip packaging structure comprises: a test bench stacked in sequence, a graphene chip after the secondary glue leveling, and a glass cover; wherein, a protective gas or a vacuum environment is filled between the glass cover and the graphene chip after the second glue leveling, and the graphene chip after the second glue leveling and the test bench are connected by wires.
优选地,所述测试台和二次匀胶后的石墨烯芯片之间通过低温胶实现固定,所述玻璃罩的底部用低温胶实现和测试台之间的固定以及玻璃罩内部的密封。Preferably, the low-temperature glue is used to fix the test platform and the graphene chip after the second glue leveling, and the bottom of the glass cover is fixed to the test platform and sealed inside the glass cover with low-temperature glue.
本发明具备如下有益效果:The present invention has following beneficial effects:
(1)本发明提供了一种提高石墨烯载流子浓度稳定性的封装方法及封装结构,该封装方法不仅可以有效地将调控后的石墨烯芯片表面隔绝空气,降低空气中的水、氧对石墨烯载流子浓度稳定性的影响,同时降低了石墨烯的载流子浓度(可降至1×1010~1011 cm-2)。(1) The present invention provides a packaging method and packaging structure for improving the stability of graphene carrier concentration. The packaging method can not only effectively isolate the surface of the regulated graphene chip from the air, reduce the influence of water and oxygen in the air on the stability of graphene carrier concentration, but also reduce the graphene carrier concentration (it can be reduced to 1×10 10 ~10 11 cm -2 ).
(2)本发明所得的石墨烯芯片封装结构较小,基本不会影响芯片的运输和测量,且能够针对不同的情况给出相应较为方便的封装方式,为芯片封装提供了多个思路。封装后的石墨烯芯片无需放置于手套箱里保存,大大便利了芯片的储存,同时避免了手套箱内外环境的差异给芯片带来的影响,让芯片的运输更加地便捷。(2) The packaging structure of the graphene chip obtained in the present invention is small, basically does not affect the transportation and measurement of the chip, and can provide corresponding and relatively convenient packaging methods for different situations, providing multiple ideas for chip packaging. The encapsulated graphene chip does not need to be stored in a glove box, which greatly facilitates the storage of the chip, and at the same time avoids the impact of the difference between the internal and external environments of the glove box on the chip, making the transportation of the chip more convenient.
(3)本发明中,采用的两种调控技术能够实现对石墨烯进行均匀掺杂,操作也较为简单,且去除掺杂剂后可恢复到调控前的状态,即具有可逆性。(3) In the present invention, the two control technologies adopted can achieve uniform doping of graphene, and the operation is relatively simple, and the state before the control can be restored after removing the dopant, that is, it is reversible.
(4)本发明封装方法操作过程简单、用时少、原料便宜,能够较大程度地提高石墨烯(芯片)载流子浓度的稳定性和使用便捷性,因此适合推广。(4) The packaging method of the present invention has simple operation process, less time consumption, and cheap raw materials, and can greatly improve the stability of the graphene (chip) carrier concentration and the convenience of use, so it is suitable for promotion.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings without creative work.
图1为本发明提供的一种提高石墨烯载流子浓度稳定性的封装方法的流程图;Fig. 1 is a flow chart of a packaging method that improves the stability of graphene carrier concentration provided by the present invention;
图2为实施例1中的石墨烯芯片的光镜图片;Fig. 2 is the optical microscope picture of the graphene chip in embodiment 1;
图3为实施例1中二次匀胶后的石墨烯芯片切面的示意图;Fig. 3 is the schematic diagram of the cut surface of the graphene chip after secondary homogenization in embodiment 1;
图4为实施例1中测试台尺寸明显大于二次匀胶后的石墨烯芯片尺寸时得到的石墨烯芯片封装结构的示意图;Fig. 4 is the schematic diagram of the graphene chip encapsulation structure that obtains when test bench size is obviously greater than the graphene chip size after secondary even glue in embodiment 1;
图5为实施例2中测试台密闭性较高时得到的石墨烯芯片封装结构的示意图;Fig. 5 is the schematic diagram of the graphene chip encapsulation structure that obtains when test platform airtightness is higher in embodiment 2;
图6为实施例3中热熔胶封装得到的石墨烯芯片封装结构的剖面示意图;Fig. 6 is the schematic cross-sectional view of the graphene chip encapsulation structure that hot-melt adhesive encapsulation obtains in embodiment 3;
图7为检测载流子浓度中石墨烯芯片的霍尔电阻随磁场的变化图;Fig. 7 is the change diagram of the Hall resistance of the graphene chip with the magnetic field in detecting the carrier concentration;
图8为检测载流子浓度中石墨烯芯片的霍尔电阻在低场进行反对称处理后的随磁场的变化图;Fig. 8 is the graph of the change with the magnetic field after the Hall resistance of the graphene chip in the detection carrier concentration is antisymmetrically processed in a low field;
其中,1、测试台;2、印制电路板;3、二次匀胶后的石墨烯芯片;4、玻璃罩。Among them, 1. Test bench; 2. Printed circuit board; 3. Graphene chip after secondary uniform glue; 4. Glass cover.
具体实施方式Detailed ways
以下描述中,为了说明而不是为了限定,提出了诸如特定系统结构、技术之类的具体细节,以便透彻理解本发明实施例。然而,本领域的技术人员应当清楚,在没有这些具体细节的其它实施例中也可以实现本发明。In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced in other embodiments without these specific details.
实施例1Example 1
参照图1,一种提高石墨烯载流子浓度稳定性的封装方法,包括以下步骤:With reference to Fig. 1, a kind of packaging method that improves the stability of graphene carrier concentration comprises the following steps:
S1、制作石墨烯芯片;这里采用本领域常规方法制作,如图2所示为制备的石墨烯芯片光镜图,白色虚线为石墨烯边界:(1)碳化硅外沿石墨烯的生长:在一个大气压的氩气环境下,将温度快速升至2000 ℃退火5 min,由于高温下硅具有较高的蒸汽压,升华速率比碳快,从而让部分碳留在SiC表面而形成石墨烯,即得到碳化硅外沿石墨烯;(2)采用电子束光刻法制作石墨烯霍尔条形,再通过电子束曝光以及电子束蒸发金属电极,获得石墨烯芯片;S1. Making a graphene chip; here it is made by a conventional method in this field, as shown in Fig. 2 is the optical microscope image of the prepared graphene chip, and the white dotted line is the graphene boundary: (1) Growth of graphene on the outer edge of silicon carbide: in an atmosphere of argon gas at an atmospheric pressure, the temperature is rapidly raised to 2000 ° C for 5 minutes for annealing. Since silicon has a higher vapor pressure at high temperature, the sublimation rate is faster than that of carbon, so that part of the carbon remains on the surface of SiC to form graphene, that is, graphene on the outer edge of silicon carbide is obtained; Graphene Hall strips are made by beam lithography, and then graphene chips are obtained by electron beam exposure and electron beam evaporation of metal electrodes;
S2、对得到的石墨烯芯片基底进行二次匀胶:(1)采用PMMA对石墨烯芯片基底进行第一次匀胶,匀胶时的转速6000 rpm,厚度约为240 nm,并于160 ℃下烘烤5 min;(2)采用混合掺杂剂对第一次匀胶后的石墨烯芯片进行第二次匀胶,匀胶时的转速6000 rpm,厚度约为235 nm;得到二次匀胶后的石墨烯芯片,结构示意图见图3;S2. Perform secondary homogenization on the obtained graphene chip substrate: (1) use PMMA to perform the first homogenization on the graphene chip substrate, the speed of homogenization is 6000 rpm, the thickness is about 240 nm, and bake at 160 °C for 5 min; (2) The graphene chip after the first homogenization is performed with a mixed dopant, the speed of homogenization is 6000 rpm, and the thickness is about 235 nm; the graphene chip after the second homogenization is obtained. Figure 3;
其中,混合掺杂剂是将质量为5 mg 的F4TCNQ和体积为1.8 ml的PMMA A4(质量分数为4%)混合得到,且混合掺杂剂中的F4TCNQ的质量分数为7%。Among them, the mixed dopant is obtained by mixing 5 mg of F4TCNQ with a volume of 1.8 ml of PMMA A4 (4% mass fraction), and the mass fraction of F4TCNQ in the mixed dopant is 7%.
S3、当测试台1尺寸明显大于二次匀胶后的石墨烯芯片3尺寸时,采用以下方式对二次匀胶后的石墨烯芯片3进行封装,具体步骤为:将印制电路板2用低温胶粘在测试台1上,并将二次匀胶后的石墨烯芯片3用低温胶(VGE-7031 varnish,varnish为清漆)粘在印制电路板2的上方,并用引线将二次匀胶后的石墨烯芯片3与印制电路板2连接,随后将已放置二次匀胶后的石墨烯芯片3和印制电路板2的测试台1、低温胶以及玻璃罩4放入手套箱,并用低温胶以及玻璃罩4将二次匀胶后的石墨烯芯片3以及引线封装,用引线将印制电路板2与测试台1连接,从而实现二次匀胶后的石墨烯芯片3与测试台1之间的连接。得到图4所示的封装结构(A为俯视图,B为侧视图),由图4B所示,从下往上依次层叠为:测试台1、印制电路板2、二次匀胶后的石墨烯芯片3、玻璃罩4。测试台1和印制电路板2之间以及印制电路板2和二次匀胶后的石墨烯芯片3之间用低温胶实现固定,玻璃罩4的底部用低温胶实现和印制电路板2之间的固定以及玻璃罩4内部的密封,玻璃罩4和二次匀胶后的石墨烯芯片3之间填充有保护性气体或为真空环境,二次匀胶后的石墨烯芯片3通过引线实现和印制电路板2的连接,印制电路板2和测试台1同样通过引线连接,进而实现二次匀胶后的石墨烯芯片3和测试台1的连接。此方法较热熔胶封装操作难度更小,而且能够实现更大的封装面积,减少了封装难度。S3. When the size of the test bench 1 is significantly larger than the size of the graphene chip 3 after the second gluing, the graphene chip 3 after the second gluing is packaged in the following manner. The specific steps are: the printed circuit board 2 is glued on the test bench 1, and the graphene chip 3 after the second gluing is glued on the top of the printed circuit board 2 with a low-temperature glue (VGE-7031 varnish, varnish is varnish), and the graphene chip 3 after the second gluing is connected to the printed circuit board 2 with a lead wire Then put the graphene chip 3 and the test bench 1 of the graphene chip 3 and the printed circuit board 2 after the second glue leveling, the low-temperature glue and the glass cover 4 into the glove box, and use the low-temperature glue and the glass cover 4 to package the graphene chip 3 and the lead after the second glue leveling, and connect the printed circuit board 2 to the test bench 1 with the lead wires, so as to realize the connection between the graphene chip 3 and the test bench 1 after the second glue leveling. Obtain the packaging structure shown in Figure 4 (A is a top view, B is a side view), as shown in Figure 4B, stacked sequentially from bottom to top: test bench 1, printed circuit board 2, graphene chip 3 after secondary glue leveling, glass cover 4. Between the test bench 1 and the printed circuit board 2 and between the printed circuit board 2 and the graphene chip 3 after the secondary glue leveling, realize fixing with low-temperature glue; the bottom of the glass cover 4 realizes the fixing between the printed circuit board 2 and the sealing inside the glass cover 4 with low-temperature glue; Realize the connection between the graphene chip 3 and the test bench 1 after the second glue leveling. This method is less difficult than hot melt adhesive packaging, and can achieve a larger packaging area, reducing the difficulty of packaging.
S4、通过在90 ℃下加热方式(加热3 min)调控完成封装的石墨烯芯片的载流子浓度。S4. Regulate the carrier concentration of the packaged graphene chip by heating at 90°C (heating for 3 min).
实施例2Example 2
S1、制备石墨烯芯片;这里采用本领域常规方法制作:(1)碳化硅外沿石墨烯的生长:在一个大气压的氩气环境下,将温度快速升至2000 ℃退火5 min,由于高温下硅具有较高的蒸汽压,升华速率比碳快,从而让部分碳留在SiC表面而形成石墨烯,即得到碳化硅外沿石墨烯芯片;(2)采用电子束光刻法制作石墨烯霍尔条形,再通过电子束曝光以及电子束蒸发镀金属电极,获得石墨烯芯片;S1. Preparation of graphene chip; Here, the conventional method in this field is used to make: (1) Growth of graphene on the outer edge of silicon carbide: in an atmosphere of argon gas at atmospheric pressure, the temperature is rapidly raised to 2000 ° C for 5 minutes, and silicon has a higher vapor pressure at high temperature, and the sublimation rate is faster than that of carbon, so that part of the carbon remains on the surface of SiC to form graphene, that is, a graphene chip on the outer edge of silicon carbide is obtained; Plating metal electrodes to obtain graphene chips;
S2、对得到的石墨烯芯片基底进行二次匀胶:(1)采用PMMA/MMA(MMA质量占比8.5%,MAA)对石墨烯芯片进行第一次匀胶,匀胶时的转速5000 rpm,厚度为320 nm,并于160℃下烘烤5 min;(2)采用ZEP520A对第一次匀胶后的石墨烯芯片进行第二次匀胶,匀胶时的转速6000 rpm,厚度为300 nm,并于170 ℃下烘烤5 min。S2. Perform secondary coating on the obtained graphene chip substrate: (1) use PMMA/MMA (8.5% by mass of MMA, MAA) to perform the first coating on the graphene chip, the speed of coating is 5000 rpm, the thickness is 320 nm, and bake at 160 °C for 5 minutes; (2) Use ZEP520A to perform the second coating on the graphene chip after the first coating, the speed of coating is 6000 rpm, and the thickness is 30 0 nm and baked at 170 °C for 5 min.
S3、当测试台1的密闭性较高时,采用以下方式对二次匀胶后的石墨烯芯片3进行封装,此方法较热熔胶封装操作难度更小,具体步骤为:将测试台1和二次匀胶后的石墨烯芯片3之间用低温胶实现固定,玻璃罩4的底部用低温胶实现和测试台1之间的固定以及玻璃罩4内部的密封,玻璃罩4和二次匀胶后的石墨烯芯片3之间填充有保护性气体或为真空环境,二次匀胶后的石墨烯芯片3和测试台1通过引线连接。得到图5所示的封装结构(A为俯视图,B为侧视图),由图5B所示,从下往上依次层叠为:测试台1、二次匀胶后的石墨烯芯片3、玻璃罩4;测试台1和二次匀胶后的石墨烯芯片3之间用低温胶实现固定,玻璃罩4的底部用低温胶实现和测试台1之间的固定以及玻璃罩4内部的密封,玻璃罩4和二次匀胶后的石墨烯芯片3之间填充有保护性气体或为真空环境,二次匀胶后的石墨烯芯片3通过引线实现和测试台1的连接。此方法较热熔胶封装操作难度更小;S3, when the airtightness of the test bench 1 is high, adopt the following method to package the graphene chip 3 after the second glue leveling. This method is less difficult than the hot melt adhesive packaging operation. The specific steps are: use low-temperature glue to fix the test bench 1 and the graphene chip 3 after the second glue leveling. The chip 3 and the test bench 1 are connected by wires. Obtain the encapsulation structure shown in Figure 5 (A is a top view, B is a side view), as shown in Figure 5B, stacked successively from bottom to top: test bench 1, graphene chip 3 and glass cover 4 after the second glue leveling; low-temperature glue is used to fix between the test bench 1 and the graphene chip 3 after the second glue leveling; The graphene chips 3 after uniform glue are connected to the test bench 1 through wires. This method is less difficult than hot melt adhesive packaging operation;
S4、通过紫外灯照射(248 nm)的方式,调控完成封装的石墨烯芯片的载流子浓度。S4. Control the carrier concentration of the packaged graphene chip by means of ultraviolet light irradiation (248 nm).
实施例3Example 3
S1、制备石墨烯芯片;这里采用本领域常规方法制作:(1)碳化硅外沿石墨烯的生长:在一个大气压的氩气环境下,将温度快速升至2000 ℃退火5 min,由于高温下硅具有较高的蒸汽压,升华速率比碳快,从而让部分碳留在SiC表面而形成石墨烯,即得到碳化硅外沿石墨烯芯片;(2)采用电子束光刻法制作石墨烯霍尔条形,再通过电子束曝光以及电子束蒸发镀金属电极,获得石墨烯芯片;S1. Preparation of graphene chip; Here, the conventional method in this field is used to make: (1) Growth of graphene on the outer edge of silicon carbide: in an atmosphere of argon gas at atmospheric pressure, the temperature is rapidly raised to 2000 ° C for 5 minutes, and silicon has a higher vapor pressure at high temperature, and the sublimation rate is faster than that of carbon, so that part of the carbon remains on the surface of SiC to form graphene, that is, a graphene chip on the outer edge of silicon carbide is obtained; Plating metal electrodes to obtain graphene chips;
S2、对得到的石墨烯芯片基底进行二次匀胶:(1)采用PMMA/MMA(MMA质量占比8.5%,MAA)对石墨烯芯片基底进行第一次匀胶,匀胶时的转速5000 rpm,厚度为320 nm,并于160 ℃下烘烤5 min;(2)采用ZEP520A对第一次匀胶后的石墨烯芯片进行第二次匀胶,匀胶时的转速6000 rpm,厚度为300 nm,并于170 ℃下烘烤5 min。S2. Perform secondary coating on the obtained graphene chip substrate: (1) use PMMA/MMA (8.5% by mass of MMA, MAA) to perform the first coating on the graphene chip substrate, the speed of coating is 5000 rpm, the thickness is 320 nm, and bake at 160 ℃ for 5 min; 300 nm and baked at 170 °C for 5 min.
S3、于手套箱中,采用热熔胶对二次匀胶后的石墨烯芯片进行封装,具体步骤为:将二次匀胶后的石墨烯芯片、热熔胶、以及切割成合适大小的载玻片放入手套箱,用热熔胶包裹二次匀胶后的石墨烯芯片,然后加热热熔胶使之熔化,再将载玻片盖住热熔胶,整体取下封装后的石墨烯芯片。得到的石墨烯芯片封装结构如图6所示(这里未展示引线和测试台),从下往上依次层叠为:二次匀胶后的石墨烯芯片、保护性气体或真空、载玻片;载玻片边缘用热熔胶胶密封,载玻片和二次匀胶后的石墨烯芯片之间填充有保护性气体或为真空环境。S3. In the glove box, use hot-melt adhesive to package the graphene chip after the secondary leveling. The specific steps are: put the graphene chip after the second leveling, hot-melt adhesive, and a glass slide cut into a suitable size into the glove box, wrap the graphene chip after the second leveling with hot-melt adhesive, then heat the hot-melt adhesive to melt it, cover the glass slide with the hot-melt adhesive, and remove the packaged graphene chip as a whole. The resulting graphene chip packaging structure is shown in Figure 6 (leads and test benches are not shown here), which are stacked sequentially from bottom to top: the graphene chip after the second glue leveling, protective gas or vacuum, and the glass slide; the edge of the glass slide is sealed with hot melt adhesive, and the gap between the glass slide and the graphene chip after the second glue leveling is filled with protective gas or in a vacuum environment.
S4、通过紫外灯照射(248 nm)的方式,调控完成封装的石墨烯芯片的载流子浓度。S4. Control the carrier concentration of the packaged graphene chip by means of ultraviolet light irradiation (248 nm).
检测载流子浓度Detection of carrier concentration
测试室温下实施例1制备的一个石墨烯芯片的纵向电阻率,得到纵向电阻率为5.47 kΩ,由于当芯片纵向电阻率处于5~6 kΩ范围时,其5K时对应的载流子浓度大致在1~2×1011 cm-2,此时芯片的霍尔电阻可以在较低的磁场:小于4 T进入平台,然后将芯片放入低温腔中,降至5 K且保持稳定,给样品通入电流(这里依次通入了1 μA、20 μA、30 μA、40 μA、50 μA),然后给芯片施加连续变化的磁场,磁场范围为-9 T到9 T,测试芯片霍尔电压随磁场的变化,结果如图7所示。由图7结果可知,芯片在2.5 T时已进入平台,用霍尔电压除以通入的电流得到霍尔电阻(率),然后取-0.5 T到0.5 T时霍尔电阻随磁场的变化,此时霍尔电阻随磁场成线性变化,将数据进行反对称化处理(见图8),通过线性拟合,获得磁场和霍尔电阻的比值,再除以一个电子的电荷量(1.6×10-19 C),得到实施例1制备的封装后的某一个石墨烯芯片的载流子浓度为1.95×1011~1.98×1011 cm-2(石墨烯芯片的载流子浓度随电流的增加会略有增加)。完成全部测试后,得到实施例1制备的封装后的石墨烯芯片的载流子浓度为1×1010~2×1011 cm-2,实施例2制备的封装后的石墨烯芯片的载流子浓度为1×1011~3×1011 cm-2。由上述试验结果可知,此封装方法不仅能提高芯片的稳定性,还能有效降低芯片载流子浓度。测试室温下实施例1制备的一个石墨烯芯片的纵向电阻率,得到纵向电阻率为5.47 kΩ,由于当芯片纵向电阻率处于5~6 kΩ范围时,其5K时对应的载流子浓度大致在1~2×10 11 cm -2 ,此时芯片的霍尔电阻可以在较低的磁场:小于4 T进入平台,然后将芯片放入低温腔中,降至5 K且保持稳定,给样品通入电流(这里依次通入了1 μA、20 μA、30 μA、40 μA、50 μA),然后给芯片施加连续变化的磁场,磁场范围为-9 T到9 T,测试芯片霍尔电压随磁场的变化,结果如图7所示。 It can be seen from the results in Figure 7 that the chip has entered the platform at 2.5 T, and the Hall resistance (ratio) is obtained by dividing the Hall voltage by the input current, and then taking the change of the Hall resistance with the magnetic field from -0.5 T to 0.5 T. At this time, the Hall resistance changes linearly with the magnetic field, and the data is desymmetricalized (see Figure 8). The carrier concentration of a graphene chip is 1.95×10 11 ~1.98× 10 11 cm -2 (the carrier concentration of the graphene chip will increase slightly with the increase of the current). After completing all the tests, the carrier concentration of the packaged graphene chip prepared in Example 1 was 1×10 10 ~2×10 11 cm -2 , and the carrier concentration of the packaged graphene chip prepared in Example 2 was 1×10 11 ~3×10 11 cm -2 . From the above test results, it can be seen that this packaging method can not only improve the stability of the chip, but also effectively reduce the carrier concentration of the chip.
本发明不局限于上述具体的实施方式,本领域的普通技术人员从上述构思出发,不经过创造性的劳动,所做出的种种变换,均落在本发明的保护范围之内。The present invention is not limited to the above-mentioned specific implementation manners, and various transformations made by those skilled in the art starting from the above-mentioned ideas without creative work all fall within the scope of protection of the present invention.
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