CN115666209B - Packaging method and packaging structure for improving concentration stability of graphene carriers - Google Patents
Packaging method and packaging structure for improving concentration stability of graphene carriers Download PDFInfo
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Abstract
The invention discloses a packaging method and a packaging structure for improving the concentration stability of graphene carriers, comprising the following steps: manufacturing a graphene chip; carrying out secondary spin coating on the graphene chip substrate by adopting PMMA solution and mixed doping agent, and baking; wherein the mixed dopant is PMMA doped with F4 TCNQ; packaging the graphene chip subjected to secondary spin in a glove box; and regulating and controlling the packaged graphene chip. The packaging method disclosed by the invention not only effectively isolates the surface of the regulated graphene chip from air and reduces the influence of water and oxygen in the air on the carrier concentration stability of the graphene chip, but also reduces the carrier concentration of the graphene. And the obtained graphene chip packaging structure is smaller, the transportation and measurement of the graphene chip packaging structure are not affected basically, the graphene chip packaging structure is not required to be placed in a glove box for storage, and the storage of the chip is greatly facilitated. In addition, the packaging method has the advantages of simple operation process, less time consumption and cheap raw materials, so that the packaging method is suitable for popularization.
Description
Technical Field
The invention belongs to the technical field of graphene device packaging, and particularly relates to a packaging method and a packaging structure for improving graphene carrier concentration stability.
Background
In a low-temperature strong magnetic field environment, single-layer graphene epitaxially grown on a SiC (0001) surface presents a quantum Hall platform within a very wide magnetic field range due to a pinning effect, and the corresponding filling factor is 2. However, graphene is heavily n-doped and its carrier concentration is typically 10 12 ~10 13 cm -2 Therefore, a quantum hall platform corresponding to a filling factor of 2 cannot be achieved under a lower magnetic field. A variety of methods for regulating and controlling graphene carrier concentration have been studied at present, among which more common methods are: the use of F4TCNQ (2, 3,5, 6-tetrafluoro-7, 7', 8' -tetracyanodimethyl-p-benzoquinone), for example, is described in document 1 (Form doping of graphene close to the Dirac point by polymer-assisted assembly of molecular dopans. Nat. Commun. 9, 3956 (2018)), in which F4TCNQ is used as an electron acceptor, a chip is heated at 160℃with the carrier concentration as a function of heating timeCan change the carrier concentration from 1×10 13 cm -2 Down to around the dirac point (0 cm) -2 ). However, for a chip with a low initial carrier concentration, the regulation and control rate is too fast to realize stable regulation and control of carriers. When a five-layer structure is adopted, the stability of carriers is better, but each layer of glue needs to be heated, and the difficulty of regulation and control is greatly increased by evenly mixing the five layers of glue; the method for controlling carrier concentration by controlling the amount of chlorine radicals formed by controlling the measurement of ultraviolet light is described in, for example, document 2 (Lara-Avila, S.et al, non-volatile photochemical gating of an epitaxial graphene/Polymer healthcare, adv. Mater, 23, 878-882 (2011), in which ZEP520A generates a large amount of chlorine radicals by ultraviolet light, and the carrier concentration of graphene is effectively reduced by controlling the amount of chlorine radicals formed by ultraviolet light.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a packaging method and a packaging structure for improving the concentration stability of graphene carriers.
The first aspect of the invention provides a packaging method for improving the concentration stability of graphene carriers, which comprises the following steps:
s1, manufacturing a graphene chip;
s2, carrying out secondary spin coating on the graphene chip substrate: firstly, carrying out first glue homogenizing and baking on a graphene chip substrate by adopting PMMA solution; then, carrying out second spin on the graphene chip subjected to the first spin by adopting a mixed dopant, wherein the mixed dopant is PMMA doped with F4TCNQ (2, 3,5, 6-tetrafluoro-7, 7', 8' -tetracyanoquinodimeth-p-benzoquinone);
s3, packaging the graphene chip subjected to the secondary spin coating in a glove box;
s4, regulating and controlling the packaged graphene chip to reduce the concentration of graphene carriers.
Preferably, in step S2, the baking temperature is 160-180 ℃ and the baking time is 3-6 min.
Preferably, in the step S2, the solvent used in the PMMA solution is anisole, and the molecular weight of the PMMA is 920000 to 980000; the mass percentage content of F4TCNQ in the mixed doping agent is 4-7wt%.
Preferably, in step S3, the graphene chip after the secondary spin may be packaged in the following three ways:
(1) The method adopts a hot melt adhesive mode to package, and comprises the following specific steps: wrapping the graphene chip subjected to secondary glue homogenization by using a hot melt adhesive in a glove box, heating the hot melt adhesive to melt the graphene chip, covering the hot melt adhesive by using a glass slide, and integrally taking down the packaged graphene chip; wherein the heating temperature is 90-100 ℃ and the heating time is 1-5 min; the packaging process is carried out under the condition of protective gas or vacuum in a glove box, wherein the protective gas is argon or nitrogen.
(2) When the size of the test bench is obviously larger than that of the graphene chip subjected to secondary spin coating, the following modes are adopted for packaging, and the specific steps are as follows: and (3) gluing the printed circuit board on the test bench by using low-temperature glue, gluing the secondarily glued graphene chip above the printed circuit board by using low-temperature glue, connecting the secondarily glued graphene chip with the printed circuit board by using a lead wire, then placing the secondarily glued graphene chip and the test bench of the printed circuit board, the low-temperature glue and a glass cover into a glove box, packaging the secondarily glued graphene chip and the lead wire by using the low-temperature glue and the glass cover, and connecting the printed circuit board with the test bench by using the lead wire, thereby realizing connection between the secondarily glued graphene chip and the test bench.
(3) When the tightness of the test bench is higher, the following modes are adopted for packaging, and the specific steps are as follows: in a glove box, fixing the test bench and the graphene chips subjected to secondary spin coating by using low-temperature glue, fixing the test bench and the bottom of the glass cover by using low-temperature glue, and sealing the inside of the glass cover, wherein protective gas or a vacuum environment is filled between the glass cover and the graphene chips subjected to secondary spin coating, and the graphene chips subjected to secondary spin coating are connected with the test bench through leads.
Preferably, in step S4, the regulation manner is: and heating the packaged graphene chip at the temperature of 90-95 ℃ for 2-5 min. Due to the fact that PMMA can be deformed through heating operation, the electron acceptor F4TCNQ reaches the surface of graphene, and then the carrier concentration of the graphene is reduced.
Preferably, the secondary spin can be realized by the following way instead; and (3) carrying out first spin coating and first baking on the graphene chip substrate by adopting PMMA/MMA, and then carrying out second spin coating and second baking on the graphene chip subjected to the first spin coating by adopting ZEP 520A.
Preferably, the first baking temperature is 160-180 ℃ and the baking time is 3-6 min; the second baking temperature is 160-180 ℃ and the baking time is 3-6 min.
Preferably, in step S4, the adjustment and control manner is to irradiate the encapsulated graphene chip with an ultraviolet lamp, where the wavelength of the ultraviolet lamp is 248-260 nm, and the irradiation time is 2-5 min. The ultraviolet irradiation can induce the formation of a large amount of chlorine free radicals, and the chlorine free radicals serve as electron acceptors, so that the carrier concentration of graphene can be effectively reduced.
The second aspect of the invention provides a graphene chip packaging structure obtained by the packaging method.
Preferably, the graphene chip packaging structure includes: a test bench, a printed circuit board, a graphene chip subjected to secondary spin coating and a glass cover which are sequentially laminated; the glass cover and the graphene chip subjected to secondary spin coating are filled with protective gas or are in a vacuum environment, the graphene chip subjected to secondary spin coating is connected with the printed circuit board through a lead, and the printed circuit board is connected with the test bench through a lead.
Preferably, the test bench and the printed circuit board and the graphene chip after secondary spin coating are fixed through low-temperature glue, and the bottom of the glass cover is fixed with the printed circuit board and sealed inside the glass cover through the low-temperature glue.
Preferably, the graphene chip packaging structure includes: a test bench, a graphene chip subjected to secondary spin coating and a glass cover which are sequentially laminated; the glass cover and the graphene chip subjected to secondary spin coating are filled with protective gas or are in a vacuum environment, and the graphene chip subjected to secondary spin coating is connected with the test bench through a lead.
Preferably, the test bench and the graphene chip subjected to secondary spin coating are fixed through low-temperature glue, and the bottom of the glass cover is fixed with the test bench and sealed inside the glass cover through the low-temperature glue.
The invention has the following beneficial effects:
(1) The invention provides a packaging method and a packaging structure for improving the concentration stability of graphene carriers, which not only can effectively isolate the surface of a regulated graphene chip from air and reduce the influence of water and oxygen in the air on the concentration stability of graphene carriers, but also can reduce the concentration of graphene carriers (which can be reduced to 1 multiplied by 10) 10 ~10 11 cm -2 ）。
(2) The graphene chip packaging structure obtained by the method is smaller, the transportation and measurement of the chip are not affected basically, a corresponding and more convenient packaging mode can be provided for different conditions, and a plurality of ideas are provided for chip packaging. The packaged graphene chip is not required to be placed in a glove box for storage, so that the storage of the chip is greatly facilitated, meanwhile, the influence of the difference between the internal environment and the external environment of the glove box on the chip is avoided, and the transportation of the chip is more convenient.
(3) According to the invention, the graphene can be uniformly doped by adopting two regulation and control technologies, the operation is simpler, and the graphene can be recovered to a state before regulation and control after the dopant is removed, so that the graphene has reversibility.
(4) The packaging method has the advantages of simple operation process, less time consumption and cheap raw materials, and can greatly improve the stability and the use convenience of the carrier concentration of the graphene (chip), so that the packaging method is suitable for popularization.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a packaging method for improving the concentration stability of graphene carriers;
fig. 2 is a mirror image of the graphene chip in example 1;
fig. 3 is a schematic diagram of a section of a graphene chip after the secondary spin in example 1;
fig. 4 is a schematic diagram of a graphene chip package structure obtained when the size of the test bench in example 1 is significantly larger than the size of the graphene chip after the secondary spin;
fig. 5 is a schematic diagram of a graphene chip package structure obtained when the test bench in embodiment 2 has high tightness;
fig. 6 is a schematic cross-sectional view of a graphene chip package structure obtained by hot melt adhesive encapsulation in example 3;
FIG. 7 is a graph showing the change of Hall resistance of a graphene chip with magnetic field in detecting carrier concentration;
FIG. 8 is a graph showing the change of Hall resistance of a graphene chip with magnetic field after antisymmetric treatment in a low field for detecting carrier concentration;
1, a test bench; 2. a printed circuit board; 3. graphene chips after secondary spin coating; 4. a glass cover.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details.
Example 1
Referring to fig. 1, a packaging method for improving the stability of graphene carrier concentration includes the following steps:
s1, manufacturing a graphene chip; the graphene chip is manufactured by a conventional method in the art, and as shown in fig. 2, a prepared graphene chip is subjected to optical mapping, and white dotted lines are graphene boundaries: (1) growth of silicon carbide outer edge graphene: in an atmosphere of argon, the temperature is quickly raised to 2000 ℃ for annealing for 5min, and silicon has higher vapor pressure at high temperature, so that sublimation rate is faster than carbon, and part of carbon is left on the surface of SiC to form graphene, namely the silicon carbide outer edge graphene is obtained; (2) Manufacturing a graphene Hall strip by adopting an electron beam lithography method, and then obtaining a graphene chip through electron beam exposure and electron beam evaporation of a metal electrode;
s2, carrying out secondary spin coating on the obtained graphene chip substrate: (1) Carrying out first spin coating on the graphene chip substrate by adopting PMMA, wherein the rotating speed is 6000 rpm during spin coating, the thickness is about 240 nm, and the graphene chip substrate is baked for 5min at 160 ℃; (2) Carrying out second spin coating on the graphene chip subjected to the first spin coating by adopting a mixed doping agent, wherein the rotating speed is 6000 rpm during the spin coating, and the thickness is about 235 nm; obtaining a graphene chip subjected to secondary spin coating, wherein the structural schematic diagram is shown in fig. 3;
the mixed dopant was obtained by mixing 5. 5 mg of F4TCNQ and 1.8 ml of PMMA A4 (mass fraction of 4%) by volume, and the mass fraction of F4TCNQ in the mixed dopant was 7%.
S3, when the size of the test bench 1 is obviously larger than the size of the graphene chip 3 subjected to secondary spin coating, the graphene chip 3 subjected to secondary spin coating is packaged in the following manner, and the specific steps are as follows: the method comprises the steps of adhering a printed circuit board 2 to a test bench 1 by using low-temperature glue, adhering a secondarily homogenized graphene chip 3 above the printed circuit board 2 by using low-temperature glue (VGE-7031 varnish,varnish is varnish), connecting the secondarily homogenized graphene chip 3 with the printed circuit board 2 by using leads, then placing the secondarily homogenized graphene chip 3 and the test bench 1, the low-temperature glue and a glass cover 4 of the printed circuit board 2 into a glove box, packaging the secondarily homogenized graphene chip 3 and leads by using the low-temperature glue and the glass cover 4, and connecting the printed circuit board 2 with the test bench 1 by using the leads, thereby realizing connection between the secondarily homogenized graphene chip 3 and the test bench 1. The package structure shown in fig. 4 (a is a top view, and B is a side view) is obtained, and as shown in fig. 4B, the package structure is laminated in order from bottom to top: test bench 1, printed circuit board 2, graphene chip 3 after the secondary spin, glass cover 4. The test bench 1 and the printed circuit board 2 and the graphene chips 3 after secondary spin coating are fixed by using low-temperature glue, the bottom of the glass cover 4 is fixed with the printed circuit board 2 by using low-temperature glue and the inside of the glass cover 4 is sealed, protective gas or vacuum environment is filled between the glass cover 4 and the graphene chips 3 after secondary spin coating, the graphene chips 3 after secondary spin coating are connected with the printed circuit board 2 through leads, the printed circuit board 2 and the test bench 1 are connected through leads, and then the connection between the graphene chips 3 after secondary spin coating and the test bench 1 is realized. Compared with the hot melt adhesive, the method has lower packaging operation difficulty, can realize larger packaging area and reduces the packaging difficulty.
S4, regulating and controlling the carrier concentration of the packaged graphene chip by a heating mode (heating for 3 min) at 90 ℃.
Example 2
S1, preparing a graphene chip; the preparation is carried out by the conventional method in the field: (1) growth of silicon carbide outer edge graphene: in an atmosphere of argon, the temperature is quickly raised to 2000 ℃ for annealing for 5min, and silicon has higher vapor pressure at high temperature, so that sublimation rate is faster than carbon, and part of carbon is left on the surface of SiC to form graphene, and a silicon carbide outer edge graphene chip is obtained; (2) Manufacturing a graphene Hall strip by adopting an electron beam lithography method, and then obtaining a graphene chip through electron beam exposure and electron beam evaporation of a metal-plated electrode;
s2, carrying out secondary spin coating on the obtained graphene chip substrate: (1) Carrying out first spin coating on a graphene chip by adopting PMMA/MMA (the mass ratio of MMA is 8.5%, MAA), wherein the spin speed is 5000 rpm during spin coating, the thickness is 320 nm, and the graphene chip is baked for 5min at 160 ℃; (2) And (3) performing secondary spin coating on the graphene chip subjected to the primary spin coating by adopting ZEP520A, wherein the spin speed is 6000 rpm during spin coating, the thickness is 300 nm, and the graphene chip is baked for 5min at 170 ℃.
S3, when the tightness of the test bench 1 is high, packaging the graphene chip 3 subjected to secondary spin coating in the following manner, wherein the method is less in difficulty than hot melt adhesive packaging operation, and comprises the following specific steps: the graphene chips 3 after the secondary glue homogenizing are fixed by using low-temperature glue, the bottom of the glass cover 4 is fixed with the test bench 1 by using low-temperature glue, and the inside of the glass cover 4 is sealed, protective gas or a vacuum environment is filled between the glass cover 4 and the graphene chips 3 after the secondary glue homogenizing, and the graphene chips 3 after the secondary glue homogenizing are connected with the test bench 1 through leads. The package structure shown in fig. 5 (a is a top view, and B is a side view) is obtained, and as shown in fig. 5B, the package structure is laminated in order from bottom to top: the device comprises a test bench 1, a graphene chip 3 subjected to secondary spin coating and a glass cover 4; the test bench 1 and the graphene chip 3 after secondary spin coating are fixed by using low-temperature glue, the bottom of the glass cover 4 is fixed with the test bench 1 by using low-temperature glue, and the inside of the glass cover 4 is sealed, protective gas or a vacuum environment is filled between the glass cover 4 and the graphene chip 3 after secondary spin coating, and the graphene chip 3 after secondary spin coating is connected with the test bench 1 through a lead. The method has lower difficulty than the hot melt adhesive packaging operation;
s4, regulating and controlling the carrier concentration of the packaged graphene chip in a mode of ultraviolet lamp irradiation (248 nm).
Example 3
S1, preparing a graphene chip; the preparation is carried out by the conventional method in the field: (1) growth of silicon carbide outer edge graphene: in an atmosphere of argon, the temperature is quickly raised to 2000 ℃ for annealing for 5min, and silicon has higher vapor pressure at high temperature, so that sublimation rate is faster than carbon, and part of carbon is left on the surface of SiC to form graphene, and a silicon carbide outer edge graphene chip is obtained; (2) Manufacturing a graphene Hall strip by adopting an electron beam lithography method, and then obtaining a graphene chip through electron beam exposure and electron beam evaporation of a metal-plated electrode;
s2, carrying out secondary spin coating on the obtained graphene chip substrate: (1) Carrying out first spin coating on a graphene chip substrate by adopting PMMA/MMA (the mass ratio of MMA is 8.5%, MAA), wherein the spin speed is 5000 rpm during spin coating, the thickness is 320 nm, and the graphene chip substrate is baked for 5min at 160 ℃; (2) And (3) performing secondary spin coating on the graphene chip subjected to the primary spin coating by adopting ZEP520A, wherein the spin speed is 6000 rpm during spin coating, the thickness is 300 nm, and the graphene chip is baked for 5min at 170 ℃.
S3, in a glove box, packaging the graphene chip subjected to secondary spin coating by adopting hot melt adhesive, wherein the method comprises the following specific steps of: and (3) placing the graphene chip subjected to secondary glue homogenization, the hot melt adhesive and the glass slide cut into a proper size into a glove box, wrapping the graphene chip subjected to secondary glue homogenization by the hot melt adhesive, heating the hot melt adhesive to melt, covering the hot melt adhesive by the glass slide, and integrally taking down the packaged graphene chip. The resulting graphene chip package structure is shown in fig. 6 (here, the leads and the test bench are not shown), and is laminated in order from bottom to top: graphene chips, protective gas or vacuum and glass slides after secondary spin; the edge of the glass slide is sealed by hot melt adhesive, and protective gas or vacuum environment is filled between the glass slide and the graphene chip after secondary spin coating.
S4, regulating and controlling the carrier concentration of the packaged graphene chip in a mode of ultraviolet lamp irradiation (248 nm).
Detecting carrier concentration
The longitudinal resistivity of the graphene chip prepared in example 1 at room temperature was tested to obtain a longitudinal resistivity of 5.47K Ω, and the carrier concentration at 5K was approximately 1-2×10 when the chip longitudinal resistivity was in the range of 5-6 kΩ 11 cm -2 At this time, the hall resistance of the chip can be set at a lower magnetic field: less than 4T, then placing the chip in a low-temperature cavity, reducing to 5K and keeping stable, introducing current (1 μA, 20 μA, 30 μA, 40 μA and 50 μA are sequentially introduced into the sample), applying a continuously variable magnetic field to the chip, wherein the magnetic field is in the range of-9T to 9T, and testing the Hall voltage of the chip along with the magnetic fieldThe results are shown in FIG. 7. As can be seen from the results of FIG. 7, the chip has entered the platform at 2.5 and T, the Hall resistance (rate) is obtained by dividing the Hall voltage by the current supplied, then the Hall resistance (rate) varies with the magnetic field at-0.5 and T to 0.5 and T, at this time the Hall resistance varies linearly with the magnetic field, the data is subjected to antisymmetric processing (see FIG. 8), the ratio of the magnetic field to the Hall resistance is obtained by linear fitting, and then the ratio is divided by the charge amount of one electron (1.6X10) -19 C) The carrier concentration of one of the graphene chips after encapsulation prepared in example 1 was 1.95X10 11 ~1.98×10 11 cm -2 (the carrier concentration of the graphene chip increases slightly with increasing current). After all the tests were completed, the carrier concentration of the packaged graphene chip prepared in example 1 was 1×10 10 ~2×10 11 cm -2 The carrier concentration of the encapsulated graphene chip prepared in example 2 was 1×10 11 ~3×10 11 cm -2 . The test results show that the packaging method not only can improve the stability of the chip, but also can effectively reduce the carrier concentration of the chip.
The present invention is not limited to the above-described specific embodiments, and various modifications may be made by those skilled in the art without inventive effort from the above-described concepts, and are within the scope of the present invention.
Claims (8)
1. The encapsulation method for improving the concentration stability of the graphene carrier is characterized by comprising the following steps of:
s1, manufacturing a graphene chip;
s2, carrying out secondary spin coating on the graphene chip substrate: carrying out first glue homogenizing and baking on the graphene chip substrate by adopting PMMA solution; then, carrying out second spin coating on the graphene chip subjected to the first spin coating by adopting a mixed dopant, wherein the mixed dopant is PMMA doped with F4 TCNQ;
s3, packaging the graphene chip subjected to the secondary spin coating in a glove box;
s4, regulating and controlling the packaged graphene chip to reduce the carrier concentration of graphene;
in step S3, packaging the graphene chip after the secondary spin coating by adopting a hot melt adhesive mode, which specifically comprises the following steps: wrapping the graphene chip subjected to secondary glue homogenization by using a hot melt adhesive in a glove box, heating the hot melt adhesive to melt the graphene chip, covering the hot melt adhesive by using a glass slide, and integrally taking down the packaged graphene chip; the packaging process is carried out under the condition of protective gas or vacuum in a glove box, the edges of the glass slide are sealed by hot melt adhesive, and the protective gas or vacuum environment is filled between the glass slide and the graphene chip after secondary spin coating.
2. The packaging method for improving the concentration stability of graphene carriers according to claim 1, wherein in the step S2, the baking temperature is 160-180 ℃ and the baking time is 3-6 min; the solvent used by the PMMA solution is anisole, and the molecular weight of the PMMA is 920000-980000; the mass percentage content of F4TCNQ in the mixed doping agent is 4-7wt%.
3. The packaging method for improving the concentration stability of graphene carriers according to claim 1, wherein the heating temperature is 90-100 ℃ and the heating time is 1-5 min; the protective gas is argon or nitrogen.
4. The packaging method for improving the stability of the concentration of the graphene carrier according to claim 1, wherein in the step S4, the regulation and control manner is as follows: and heating the packaged graphene chip at a temperature of 90-95 ℃ for 2-5 min.
5. The packaging method for improving the concentration stability of graphene carriers according to claim 1, wherein the secondary spin is realized by replacing the following method; and (3) carrying out first spin coating and first baking on the graphene chip substrate by adopting PMMA/MMA, and then carrying out second spin coating and second baking on the graphene chip subjected to the first spin coating by adopting ZEP 520A.
6. The packaging method for improving the concentration stability of graphene carriers according to claim 5, wherein the first baking temperature is 160-180 ℃ and the baking time is 3-6 min; the second baking temperature is 160-180 ℃ and the baking time is 3-6 min.
7. The packaging method for improving the stability of the carrier concentration of graphene according to claim 1, wherein in the step S4, the control mode is to irradiate the packaged graphene chip by using an ultraviolet lamp, the wavelength of the ultraviolet lamp is 248-260 nm, and the irradiation time is 2-5 min.
8. A graphene chip package structure produced by the packaging method for improving the stability of the concentration of a graphene carrier according to any one of claims 1 to 7.
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