CN115666134A - Method for manufacturing flash memory device - Google Patents
Method for manufacturing flash memory device Download PDFInfo
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- CN115666134A CN115666134A CN202211259848.7A CN202211259848A CN115666134A CN 115666134 A CN115666134 A CN 115666134A CN 202211259848 A CN202211259848 A CN 202211259848A CN 115666134 A CN115666134 A CN 115666134A
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Abstract
The application discloses a manufacturing method of a flash memory device, which comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is used for integrating a flash memory device, the second area is used for integrating a logic device, a gate dielectric layer is formed on the substrate, a word line is formed on the gate dielectric layer of the first area, first polycrystalline silicon layers are formed on the gate dielectric layers on two sides of the word line, a second polycrystalline silicon layer is formed above the first polycrystalline silicon layer, a first isolation layer is formed between the first polycrystalline silicon layer and the second polycrystalline silicon layer, a word line oxide layer is formed on the top of the word line, and floating gate nitride layers are formed on the second polycrystalline silicon layers on two sides of the word line; forming an APF layer on the floating gate nitride layer and the word line oxide layer; forming an anti-reflection layer on the APF layer; etching to remove the anti-reflection layer and the APF layer in other areas except the area above the word line; and forming a protective nitride layer on the floating gate nitride layer and the APF layer. The top pair of the word lines is protected by forming the APF layer above the word lines, and the reliability of a product is improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a flash memory device.
Background
A flash memory (hereinafter referred to as "flash memory") is a memory using a non-volatile memory (NVM) technology, and is widely applied to electronic products with a storage function, such as smart phones, tablet computers, digital cameras, universal serial bus flash disks (USB flash disks, or "USB flash disks"). The flash memory is mainly characterized in that: the capacity is relatively large, the rewriting speed is high, the method is suitable for storing a large amount of data, and the data can be still stored after power failure, so that the method is widely applied.
Generally, a flash memory device includes Word Lines (WL), floating Gates (FG) on both sides of the word lines, and Control Gates (CG) also on both sides of the word lines and above the floating gates, and during a manufacturing process of the flash memory device, a problem of poor appearance of the formed word lines often occurs, thereby reducing reliability and lifespan of the product.
Disclosure of Invention
The application provides a manufacturing method of a flash memory device, which can solve the problems that the reliability of a product is poor and the service life is short due to poor appearance of a word line in the manufacturing process of the flash memory device provided by the related technology, and comprises the following steps:
providing a substrate, wherein the substrate comprises a first area and a second area when viewed from a top view, the first area is used for integrating a flash memory device, the second area is used for integrating a logic device, a gate dielectric layer is formed on the substrate, a word line is formed on the gate dielectric layer of the first area, first polycrystalline silicon layers are formed on the gate dielectric layers on two sides of the word line, a second polycrystalline silicon layer is formed above the first polycrystalline silicon layers, a first isolation layer is formed between the first polycrystalline silicon layers and the second polycrystalline silicon layers, a word line oxide layer is formed on the top of the word line, and floating gate nitride layers are formed on the second polycrystalline silicon layers on two sides of the word line;
forming an APF layer on the floating gate nitride layer and the word line oxide layer;
forming an anti-reflection layer on the APF layer;
etching to remove the anti-reflection layer and the APF layer in other areas except the area above the word line;
and forming a protective nitride layer on the floating gate nitride layer and the APF layer.
In some embodiments, the first isolation layer is an ONO layer.
In some embodiments, the etching to remove the anti-reflection layer and the APF layer in the other region except above the word line includes:
covering a photoresist on the anti-reflection layer through a photoetching process, wherein the photoresist covers the area where the top of the word line is located, and exposing other areas;
etching is carried out, and the APF layer and the anti-reflection layer in other areas except the area where the top of the word line is located are removed;
removing the photoresist;
the anti-reflection layer on top of the word line is removed.
In some embodiments, the cross section of the word line is T-shaped with a wide top and a narrow bottom, and a second isolation layer and a third isolation layer are further formed between the word line and the first polysilicon layer and between the word line and the first polysilicon layer.
In some embodiments, the second isolation layer comprises a nitride layer and the third isolation layer comprises an oxide layer.
In some embodiments, an STI structure is formed in the substrate of the first and second regions, and a first isolation layer and a second polysilicon layer are sequentially formed on the STI structure.
In some embodiments, the first polysilicon layer is used to fabricate a floating gate of the flash memory device, and the second polysilicon layer is used to fabricate a control gate of the flash memory device.
The technical scheme at least comprises the following advantages:
in the manufacturing process of the flash memory device, after the word line is formed, the APF layer is formed above the word line to protect the top of the word line, so that the subsequent process cannot damage the top of the word line, the appearance of the word line is damaged, and the reliability and the service life of a product are improved to a certain extent.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for fabricating a flash memory device according to an exemplary embodiment of the present application;
fig. 2 to fig. 6 are schematic diagrams illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, which shows a flowchart of a method for manufacturing a flash memory device according to an exemplary embodiment of the present application, as shown in fig. 1, the method includes:
step S1, providing a substrate, wherein the substrate comprises a first area and a second area when viewed from a top view, the first area is used for integrating a flash memory device, the second area is used for integrating a logic device, a gate dielectric layer is formed on the substrate, a word line is formed on the gate dielectric layer of the first area, first polycrystalline silicon layers are formed on the gate dielectric layers on two sides of the word line, a second polycrystalline silicon layer is formed above the first polycrystalline silicon layers, a first isolation layer is formed between the first polycrystalline silicon layers and the second polycrystalline silicon layers, a word line oxide layer is formed on the top of the word line, and floating gate nitride layers are formed on the second polycrystalline silicon layers on two sides of the word line.
And S2, forming an APF layer on the floating gate nitride layer and the word line oxide layer.
Referring to fig. 2, a cross-sectional view of an Advanced Patterning Film (APF) layer formed on a floating gate nitride layer and a word line oxide layer is shown. Illustratively, as shown in fig. 2, from a top view, the substrate 210 includes a first region 201 and a second region 202, the first region 201 is used for integrating a flash memory device, the second region 202 is used for integrating a logic (logic) device, a gate dielectric layer 220 is formed on the substrate 210, a word line 243 is formed on the gate dielectric layer 220 of the first region 201, a first polysilicon layer 241 is formed on the gate dielectric layer 220 on both sides of the word line 243, a second polysilicon layer 242 is formed above the first polysilicon layer 241, a first isolation layer is formed between the first polysilicon layer 241 and the second polysilicon layer 242, a word line oxide layer 260 is formed on the top of the word line 243, and a floating gate nitride layer 260 is formed on the second polysilicon layer 242 on both sides of the word line 243.
The first isolation layer may be an oxide-nitride-oxide (ONO) layer, which includes a first oxide layer 231, a nitride layer 232, and a second oxide layer 233 in sequence from bottom to top. The cross section of the word line 243 is a T-shape with a wide top and a narrow bottom, the width of the top is larger than that of the bottom, the first polysilicon layer 241 is used for manufacturing a floating gate of the flash memory device, the second polysilicon layer 242 is used for manufacturing a control gate of the flash memory device, a second isolation layer 252 and a third isolation layer 253 are further formed between the word line 243 and the first and second polysilicon layers 241, 243, the second isolation layer 252 may comprise a nitride layer, and the third isolation layer 253 may comprise an oxide layer; the STI structures 211 are formed in the substrate 210 of the first and second regions 201 and 202, and a first isolation layer (a first oxide layer 231, a nitride layer 232, and a second oxide layer 233) and a second polysilicon layer 242 are sequentially formed on the STI structures 211.
Illustratively, the APF layer 270 may be formed on the floating gate nitride layer 260 and the word line oxide layer 260 by a Chemical Vapor Deposition (CVD) process, such as a plasma enhanced chemical vapor deposition (PE CVD) process.
And S3, forming an anti-reflection layer on the APF layer.
And S4, etching to remove the anti-reflection layer and the APF layer in other areas except the area above the word line.
Illustratively, step S4 includes, but is not limited to: s4.1, covering a photoresist on the anti-reflection layer through a photoetching process, wherein the photoresist covers the area where the top of the word line is located, and exposing other areas; step S4.2, etching is carried out, and the APF layer 270 and the anti-reflection layer 280 in other areas except the area where the top of the word line is located are removed; and step S4.3, removing the light resistance. Wherein, step 4.1 includes: coating a photoresist on the anti-reflection layer; and sequentially exposing and developing to remove the photoresist in other areas except the area where the top of the word line is located.
Referring to FIG. 3, a cross-sectional view of the anti-reflective layer coated with photoresist is shown; referring to fig. 4, there is shown a schematic cross-sectional view of sequentially exposing and developing to remove the photoresist in the regions other than the region where the top of the word line is located. Illustratively, as shown in fig. 3 and 4, the anti-reflection layer 280 may include a bottom anti-reflective coating (BARC), the anti-reflection layer 280 may be formed on the APF layer 270 by coating, the photoresist 300 may be formed on the anti-reflection layer 280 by coating, and after sequentially exposing and developing, the photoresist 300 may be removed in other regions except the region where the top of the word line 243 is located.
Referring to fig. 5, a schematic cross-sectional view after etching to remove the anti-reflection layer on top of the word line is shown. The APF layer 270 and the anti-reflection layer 280 may be removed by dry etching in the regions except the region where the top of the word line 243 is located, and after the remaining photoresist 300 is removed, the anti-reflection layer at the top of the word line 243 is removed.
And S5, forming a protective nitride layer on the floating gate nitride layer and the APF layer.
Referring to fig. 6, a schematic cross-sectional view of the formation of a protective nitride layer over the floating gate nitride layer and the APF layer is shown. Illustratively, as shown in fig. 6, a protective nitride layer 290 may be formed by depositing a nitride layer on the floating gate nitride layer 260 and the APF layer 270 by a CVD process.
In summary, in the embodiment of the present application, in the manufacturing process of the flash memory device, after the word line is formed, the top of the word line is protected by forming the APF layer above the word line, so that the top of the word line is not damaged by the subsequent process, the appearance of the word line is damaged, and the reliability and the service life of the product are improved to a certain extent.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A method for manufacturing a flash memory device, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area when viewed from a top view, the first area is used for integrating a flash memory device, the second area is used for integrating a logic device, a gate dielectric layer is formed on the substrate, a word line is formed on the gate dielectric layer of the first area, first polycrystalline silicon layers are formed on the gate dielectric layers on two sides of the word line, a second polycrystalline silicon layer is formed above the first polycrystalline silicon layers, a first isolation layer is formed between the first polycrystalline silicon layers and the second polycrystalline silicon layers, a word line oxide layer is formed on the top of the word line, and floating gate nitride layers are formed on the second polycrystalline silicon layers on two sides of the word line;
forming an APF layer on the floating gate nitride layer and the word line oxide layer;
forming an anti-reflection layer on the APF layer;
etching to remove the anti-reflection layer and the APF layer in other areas except the area above the word line;
and forming a protective nitride layer on the floating gate nitride layer and the APF layer.
2. The method of claim 1, wherein the first isolation layer is an ONO layer.
3. The method of claim 2, wherein the etching to remove the anti-reflection layer and the APF layer in the other regions except above the word lines comprises:
covering a photoresist on the anti-reflection layer through a photoetching process, wherein the photoresist covers the area where the top of the word line is located and exposes other areas;
etching to remove the APF layer and the anti-reflection layer in other areas except the area where the top of the word line is located;
removing the light resistance;
the anti-reflection layer on top of the word line is removed.
4. The method as claimed in claim 3, wherein the cross-section of the word line is T-shaped with a wide top and a narrow bottom, and a second isolation layer and a third isolation layer are further formed between the word line and the first polysilicon layer and between the word line and the first polysilicon layer.
5. The method of claim 4, wherein the second isolation layer comprises a nitride layer and the third isolation layer comprises an oxide layer.
6. A method according to any one of claims 1 to 5, wherein STI structures are formed in the substrate of the first and second regions, the STI structures having sequentially formed thereon a first isolation layer and a second polysilicon layer.
7. The method of claim 6, wherein the first polysilicon layer is used to fabricate a floating gate of the flash memory device, and wherein the second polysilicon layer is used to fabricate a control gate of the flash memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211259848.7A CN115666134A (en) | 2022-10-14 | 2022-10-14 | Method for manufacturing flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211259848.7A CN115666134A (en) | 2022-10-14 | 2022-10-14 | Method for manufacturing flash memory device |
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| Publication Number | Publication Date |
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| CN115666134A true CN115666134A (en) | 2023-01-31 |
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| CN202211259848.7A Pending CN115666134A (en) | 2022-10-14 | 2022-10-14 | Method for manufacturing flash memory device |
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