CN115665567A - Real-time offset correction method, system, medium and device applied to detector - Google Patents
Real-time offset correction method, system, medium and device applied to detector Download PDFInfo
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Abstract
The invention belongs to the field of flat panel detectors and linear array detectors, and particularly relates to a real-time offset correction method, a real-time offset correction system, a real-time offset correction medium and real-time offset correction equipment applied to a detector. The method comprises the following steps: step 1, controlling a detector analog switch to be turned off and resetting a rear-stage circuit input end; step 2, collecting a first digital output value of the column analog-to-digital conversion circuit as a bias coefficient of a corresponding column; step 3, controlling the analog switch to be turned on and controlling the input end of the post-stage circuit to work; step 4, collecting a second digital output value of the column analog-to-digital conversion circuit, and subtracting the second digital output value from the bias coefficient of the corresponding column to obtain a correction output value of the pixels in multiple columns of the current row; and 5, scanning line by line and repeating the steps 3 to 4 until the corrected output values of all the pixels are obtained. The invention achieves the aim of real-time offset correction by disconnecting the pixel array from the post-stage circuit, acquiring the output of the post-stage circuit to obtain the column offset coefficient and subtracting the normal output of the pixel array from the corresponding column offset coefficient.
Description
Technical Field
The invention belongs to the field of flat panel detectors and linear array detectors, and particularly relates to a real-time offset correction method, a real-time offset correction system, a real-time offset correction medium and real-time offset correction equipment applied to a detector.
Background
A flat panel detector and a linear array detector are apparatuses for converting X-ray energy into electrical signals, and generally include a passive pixel array with multiple rows and columns and an active signal readout array, where the active signal readout array may include a row gating circuit, a multiple-to-one circuit, an integrating circuit, a PGA circuit, an analog-to-digital conversion circuit, a data processing circuit, and the like according to different architectures. In a typical APS pixel framework flat panel detector, a plurality of rows of pixels on the same column usually share a set of column signal reading circuits, and the circuits usually have some low-frequency interference due to the problems of power supply fluctuation, external power frequency interference and the like, so that real-time bias correction is usually required to be added in the use of the flat panel detector and the linear array detector to eliminate the low-frequency interference.
Conventional real-time bias correction methods typically involve the use of detectors with dual sampling functionality (DDS) or dark field line pixel sampling functionality (DRS). The DDS function is realized by resetting the pixel after each pixel signal is normally read out, acquiring the output under reset again, and subtracting the 2-time output through hardware or a program to achieve the aim of eliminating low-frequency interference. The realization idea of the DRS function is to add pixels for physical shading before the starting row or after the ending row of the normal photosensitive pixel array, and subtract the dark pixel output of the corresponding column when the normal photosensitive pixels are read out, so as to achieve the purpose of eliminating the low-frequency interference.
According to the principle, the DDS function obtains the offset signal output of the post-stage signal reading circuit through pixel resetting after the pixel signal is read out, and eliminates the interference of a higher frequency taking a single-pixel acquisition frequency as an upper limit by utilizing the characteristic that the pixel reading time is close to the offset reading time of the post-stage signal reading circuit in time. However, it can also be seen that the DDS function is complex, and each pixel needs to acquire 2 outputs, so that it includes several significant disadvantages: DDS function usually needs more complicated functional circuit support, greatly reduce the chip yield; each pixel needs to be acquired for 2 times under the DDS function, the data volume is increased to 2 times of the original data volume, and the limit frame rate is greatly influenced; subtraction of 3.2 data increases the noise by a factor of 1.41 for a single data acquisition.
The DRS function can subtract slightly lower frequency interference, which is capped at the image acquisition frequency of one frame, but it also has several significant drawbacks: 1, the DRS function needs to add extra pixel rows physically, so that the chip area is greatly increased; the DRS function usually performs plane-level physical shading on the surface of a chip, but because of the light diffusion characteristic, shading pixels close to normal pixels usually have a light leakage phenomenon and cannot be used, and the number of required pixel rows is further increased; 3. due to the existence of input end parasitic capacitance and subtraction introduced by the mounted pixels, the noise increase amplitude under the DRS function is large, and is related to the number of rows of the dark pixels, the more the number of rows is, the more the dark pixels in a single-column pixel can be used for averaging is, the smaller the noise increase amplitude is, but the corresponding chip area is obviously increased.
Summarizing, the problems introduced by the DDS functionality mainly include: (1) Complex hardware functional circuit support is required, and the yield of chips is reduced; (2) significantly reducing the limit frame rate of the detector; and (3) the corrected dark field image noise is obviously increased. The problems of DRS function introduction mainly include: (1) Extra pixel circuit support is needed, and the chip area is increased; (2) effective shading of the pixels is not easily performed; (3) There is some increase in the corrected dark field image noise.
Disclosure of Invention
The invention aims to provide a real-time offset correction method, a real-time offset correction system, a real-time offset correction medium and real-time offset correction equipment applied to a detector.
The technical scheme for solving the technical problems is as follows: a real-time offset correction method applied to a detector, comprising:
step 1, controlling an analog switch between a pixel array and a rear-stage column signal reading circuit in a detector to be turned off, and simultaneously controlling an input end of the rear-stage column signal reading circuit to be in a reset state;
step 2, in the reset state, acquiring a first digital output value of a column analog-to-digital conversion circuit in the detector, and taking the first digital output value as a bias coefficient corresponding to each column in the pixel array;
step 3, controlling the analog switch to be turned on, and simultaneously controlling the input end of the post-stage column signal reading circuit to be in a working state;
step 4, collecting a second digital output value of a column analog-to-digital conversion circuit in the detector in the working state, and subtracting the second digital output value from the offset coefficient of each column to obtain a corrected output value after the real-time offset correction of a plurality of columns of pixels in the current row is finished;
and 5, scanning line by line and repeating the steps 3 to 4 until the corrected output values of all the pixels of the pixel array are obtained.
The invention has the beneficial effects that: the invention obtains the real-time column offset coefficient by disconnecting the passive pixel array and the rear-stage active circuit and directly collecting the output of the rear-stage circuit, and achieves the purpose of real-time offset correction by directly subtracting the output of the rear-stage circuit and the corresponding column offset coefficient when the normal pixel is read out. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area completely; compared with the DRS function, because the noise of a post-stage circuit is smaller when the pixel array is not mounted, the influence of the invention on the limit frame rate and the noise is smaller under the same condition; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the step 1 specifically comprises:
when the detector is in exposure time, the analog switch between the register configuration pixel array and the rear-stage column signal reading circuit is turned off, and meanwhile, the input end of the rear-stage column signal reading circuit is controlled to be in a reset state through register configuration.
Further, the step 2 is followed by:
and correspondingly forming pixel pairs by the offset coefficient of each column and the pixel array one by one, and storing the pixel pairs into a storage device of the detector.
Further, the process of acquiring the first digital output value of the column analog-to-digital conversion circuit in the detector is as follows:
taking the single-acquisition digital output value of the analog-to-digital conversion circuit subjected to linear conversion as a first digital output value;
or taking the average value of the digital output values acquired for multiple times by the analog-to-digital conversion circuit after linear conversion as the first digital output value.
Another technical solution of the present invention for solving the above technical problems is as follows: a real-time offset correction system for use with a detector, comprising:
the first control module is used for controlling the turn-off of an analog switch between a pixel array and a rear-stage column signal reading circuit in the detector and simultaneously controlling the input end of the rear-stage column signal reading circuit to be in a reset state;
the first acquisition module is used for acquiring a first digital output value of each path of analog-to-digital conversion circuit in the detector in the reset state, and taking the first digital output value of each path as a bias coefficient corresponding to each column in the pixel array;
the second control module is used for controlling the analog switch to be turned on and controlling the input end of the post-stage column signal reading circuit to be in a working state;
the correction module is used for acquiring a second digital output value of a column analog-to-digital conversion circuit in the detector in the working state, and subtracting the offset coefficient of each column from the second digital output value to obtain a correction output value of the current row of the plurality of columns of pixels for completing real-time offset correction;
and the result module is used for scanning line by line and repeating the second control module and the correction module until the corrected output values of all pixels of the pixel array are obtained.
The beneficial effects of the invention are: the invention obtains the real-time column offset coefficient by disconnecting the passive pixel array and the rear-stage active circuit and directly collecting the output of the rear-stage circuit, and achieves the purpose of real-time offset correction by directly subtracting the output of the rear-stage circuit and the corresponding column offset coefficient when the normal pixel is read out. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area completely; compared with the DRS function, the invention has smaller influence on the limit frame rate and noise under the same condition because the noise of a post-stage circuit is smaller when the pixel array is not mounted; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements.
Further, the first control module is specifically configured to:
when the detector is in exposure time, the analog switch between the register configuration pixel array and the rear-stage column signal reading circuit is turned off, and meanwhile, the input end of the rear-stage column signal reading circuit is controlled to be in a reset state through register configuration.
Further, still include:
and the storage module is used for correspondingly forming pixel pairs by the offset coefficient of each column and the pixel array one by one and storing the pixel pairs into a storage device of the detector.
Further, the first acquisition module is specifically configured to:
the process of acquiring the first digital output value of each analog-to-digital conversion circuit in the detector is as follows:
taking the single-acquisition digital output value of the analog-to-digital conversion circuit subjected to linear conversion as a first digital output value;
or taking the average value of the digital output values acquired for multiple times by the analog-to-digital conversion circuit after linear conversion as a first digital output value.
Another technical solution of the present invention for solving the above technical problems is as follows: a storage medium having stored therein instructions which, when read by a computer, cause the computer to carry out a real-time offset correction method as claimed in any one of the preceding claims applied to a detector.
The invention has the beneficial effects that: the invention obtains the real-time column offset coefficient by disconnecting the passive pixel array and the rear-stage active circuit and directly collecting the output of the rear-stage circuit, and achieves the purpose of real-time offset correction by directly subtracting the output of the rear-stage circuit and the corresponding column offset coefficient when the normal pixel is read out. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area completely; compared with the DRS function, the invention has smaller influence on the limit frame rate and noise under the same condition because the noise of a post-stage circuit is smaller when the pixel array is not mounted; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements.
Another technical solution of the present invention for solving the above technical problems is as follows: an electronic device includes the storage medium and a processor executing instructions in the storage medium.
The invention has the beneficial effects that: the invention obtains the real-time column bias coefficient by disconnecting the passive pixel array from the rear-stage active circuit and directly collecting the output of the rear-stage circuit, and achieves the purpose of real-time correction by directly subtracting the output of the rear-stage circuit from the corresponding column bias coefficient when the normal pixel is read out. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area completely; compared with the DRS function, the invention has smaller influence on the limit frame rate and noise under the same condition because the noise of a post-stage circuit is smaller when the pixel array is not mounted; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements.
Drawings
FIG. 1 is a schematic flow chart diagram of a real-time offset calibration method applied to a detector according to an embodiment of the present invention;
FIG. 2 is a block diagram of a real-time offset calibration system for a detector according to an embodiment of the present invention;
fig. 3 is a circuit structure diagram provided by an embodiment of a real-time offset calibration method applied to a detector according to the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with examples which are set forth to illustrate, but are not to be construed to limit the scope of the invention.
As shown in fig. 1, a real-time offset correction method applied to a detector includes:
step 1, controlling an analog switch between a pixel array and a rear-stage column signal reading circuit in a detector to be turned off, and simultaneously controlling an input end of the rear-stage column signal reading circuit to be in a reset state;
step 2, in the reset state, acquiring a first digital output value of a column analog-to-digital conversion circuit in the detector, and taking the first digital output value as a bias coefficient corresponding to each column in the pixel array;
step 3, controlling the analog switch to be turned on, and simultaneously controlling the input end of the post-stage column signal reading circuit to be in a working state;
step 4, collecting a second digital output value of a column analog-to-digital conversion circuit in the detector under the working state, and subtracting the second digital output value from the offset coefficient of the corresponding column to obtain a corrected output value of completing real-time offset correction of a plurality of columns of pixels of the current row;
and 5, scanning line by line and repeating the steps 3 to 4 until the corrected output values of all the pixels of the pixel array are obtained.
In some possible embodiments, the present invention obtains a real-time column offset coefficient by disconnecting the passive pixel array from the post-stage active circuit and directly collecting the output of the post-stage circuit, and achieves the purpose of real-time correction by directly subtracting the output of the post-stage circuit from the corresponding column offset coefficient during normal pixel readout. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area at all; compared with the DRS function, the invention has smaller influence on the limit frame rate and noise under the same condition because the noise of a post-stage circuit is smaller when the pixel array is not mounted; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements. It should be noted that, in step 1, the specific process of controlling the analog switch between the pixel array and the rear-stage column signal readout circuit in the detector to be turned off and controlling the input terminal of the rear-stage column signal readout circuit to be in the reset state includes:
the connection between the input of a post-stage circuit in a flat detector or linear array detector analog link and the corresponding pixel charge output is disconnected by certain measures; determining the input end state of the post-stage circuit according to specific application; note that measures include, but are not limited to, (1) turning off a switch (2) between the preceding stage circuit and the subsequent stage circuit by the register configuration or the IO input specific waveform, (3) turning off an output of the preceding stage circuit by the register configuration or the IO input specific waveform, (4) turning off an output of the preceding stage circuit by cutting off part of the power supply, and (4) setting the output of the preceding stage circuit to a fixed voltage by the register configuration or the IO input specific waveform. The latter stage circuit may be all analog circuits located after the pixel array with respect to the whole analog circuit, or may be a part of the analog circuits after the pixel array. Disconnected means that there is no direct or indirect physical connection between the input of the subsequent stage circuit and the charge output of the pixel of the preceding stage corresponding to the subsequent stage circuit. The input state of the subsequent stage circuit includes but is not limited to floating, high impedance or being placed at a fixed voltage. The key point of the method for determining the state of the input end of the later stage is to approach the working state of the pixel when the charge output connection is not disconnected as much as possible.
Step 2, in the reset state, acquiring a first digital output value of a column analog-to-digital conversion circuit in the detector, and using the first digital output value as a bias coefficient corresponding to each column in the pixel array comprises:
collecting the output of the post-stage circuit and generating multi-column corresponding bias coefficients; the output of the post-stage circuit refers to the digital output of the post-stage circuit after the analog-to-digital conversion circuit. The output acquisition of the post-stage circuit can realize the optimal limit frame rate by single acquisition or set the times of multiple acquisition according to actual needs to realize the optimal balance between the limit frame rate and noise. The offset coefficient generating method can be obtained by certain linear conversion of single digital output of the analog-to-digital conversion circuit, and can also be obtained by certain linear conversion of multiple digital outputs after averaging. Step 3 also includes before:
integrating the bias coefficients into a correction template and storing the correction template; the method of integrating the offset coefficients into the template usually establishes a calibration coefficient-physical column number mapping table according to the column signal processing circuit position where the column offset coefficients are located.
Step 4, in the working state, collecting a second digital output value of the column analog-to-digital conversion circuit in the detector, subtracting the second digital output value from the offset coefficient of the corresponding column, and obtaining a corrected output value of the real-time offset correction of the multiple columns of pixels in the current row, wherein the specific process is as follows:
when the image is normally acquired, subtracting the corresponding column offset coefficient from the output corresponding to each pixel;
in embodiment 1, a 16-bit APS flat panel detector with a pixel matrix of 1024 × 1024 is taken as an example, and a typical analog circuit portion of the flat panel detector is shown in fig. 3, where the pixel matrix has 1024 rows of pixels, each row of pixels shares one path of integrating circuit + PGA circuit + analog-to-digital conversion circuit as a column signal readout circuit, and analog switches that can be turned off/on through a register configuration are provided between the pixels and each stage of circuits. When the real-time offset correction described in the present invention is implemented using the flat panel, a typical method and steps are as follows:
1. when the flat panel detector is in the exposure time, an analog switch between the pixel array and the rear-stage column signal reading circuit is switched off through register configuration;
2. the input end of the post-stage column signal reading circuit is placed in a reset state through register configuration;
3. acquiring digital output of the analog-to-digital conversion circuits of 1024 rows acquired at one time as a bias coefficient of each row;
4. 1024 offset coefficients are in one-to-one correspondence with 1024 rows of pixels, recorded as b 1-b 1024 and stored in an on-chip memory of a main processor;
5. an analog switch between the pixel array and the rear-stage column signal reading circuit is opened through register configuration, and the input end of the rear-stage column signal reading circuit is placed in a normal working state;
6. when the flat panel detector is positioned in a certain row for image acquisition, the output of an nth column analog-to-digital conversion circuit corresponding to an nth column of pixels subtracts a bias coefficient bn to obtain the corrected output after the real-time bias correction of the column is finished, and the corrected output of the 1 st to 1024 th columns of the current row can be obtained by the method;
7. and (6) completing image acquisition from the first row to the last row through a row scanning circuit, and repeating the step 6 to complete real-time offset correction of the whole pixel array.
It can be seen that in the present embodiment, the extra functional circuit used only includes a switch, and the switch is usually already present in the conventional flat panel detector and linear array detector due to the existence of the line scanning concept. Meanwhile, because the rear-stage active circuit does not mount pixels when the switch is switched off, the method has lower functional noise relative to the DRS under the same condition. Compared with the use of multiple dark pixels with the DRS function, the method needs the support of chip hardware, and can continuously acquire the offset value when the connection between the front-stage passive pixel and any rear-stage circuit is disconnected, so that the method has better flexibility and applicability.
Preferably, in any of the above embodiments, step 1 specifically is:
when the detector is in exposure time, the analog switch between the register configuration pixel array and the rear-stage column signal reading circuit is turned off, and meanwhile, the input end of the rear-stage column signal reading circuit is controlled to be in a reset state through register configuration.
Preferably, in any of the above embodiments, step 2 is further followed by:
and correspondingly forming pixel pairs by the offset coefficient of each column and the pixel array one by one, and storing the pixel pairs into a storage device of the detector.
Preferably, in any of the above embodiments, the acquiring the first digital output value of the column analog-to-digital conversion circuit in the detector is:
taking the single-acquisition digital output value of the analog-to-digital conversion circuit subjected to linear conversion as a first digital output value;
or taking the average value of the digital output values acquired for multiple times by the analog-to-digital conversion circuit after linear conversion as the first digital output value.
As shown in fig. 2, a real-time offset correction system applied to a detector includes:
the first control module 100 is configured to control an analog switch between a pixel array and a post-stage column signal readout circuit in a detector to be turned off, and control an input end of the post-stage column signal readout circuit to be in a reset state;
a first collecting module 200, configured to collect a first digital output value of a column analog-to-digital conversion circuit in the detector in the reset state, and use the first digital output value as a bias coefficient corresponding to each column in the pixel array;
the second control module 300 is configured to control the analog switch to be turned on, and control the input end of the post-stage column signal readout circuit to be in a working state;
the correction module 400 is configured to, in the operating state, acquire a second digital output value of the column analog-to-digital conversion circuit in the detector, and subtract the second digital output value from the offset coefficient of the corresponding column to obtain a correction output value of the current row of the plurality of columns of pixels for completing real-time offset correction;
and a result module 500, configured to scan line by line and repeat the second control module and the correction module until obtaining corrected output values of all pixels of the pixel array.
In some possible embodiments, the present invention obtains a real-time column offset coefficient by disconnecting the passive pixel array from the post-stage active circuit and directly collecting the output of the post-stage circuit, and achieves the purpose of real-time correction by directly subtracting the output of the post-stage circuit from the corresponding column offset coefficient during normal pixel readout. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area completely; compared with the DRS function, because the noise of a post-stage circuit is smaller when the pixel array is not mounted, the influence of the invention on the limit frame rate and the noise is smaller under the same condition; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements.
Preferably, in any of the above embodiments, the first control module 100 is specifically configured to:
when the detector is in the exposure time, the analog switch between the register configuration pixel array and the rear-stage column signal reading circuit is turned off, and meanwhile, the input end of the rear-stage column signal reading circuit is controlled to be in a reset state through the register configuration.
Preferably, in any of the above embodiments, further comprising:
and the storage module is used for correspondingly forming pixel pairs by the bias coefficients of each column and the pixel array one by one and storing the pixel pairs into a storage device of the detector.
Preferably, in any of the above embodiments, the first building block is specifically configured to:
the process of acquiring the first digital output value of each analog-to-digital conversion circuit in the detector is as follows:
taking the single-time acquisition digital output value of the analog-to-digital conversion circuit after linear conversion as a first digital output value;
or taking the average value of the digital output values acquired for multiple times by the analog-to-digital conversion circuit after linear conversion as the first digital output value.
Another technical solution of the present invention for solving the above technical problems is as follows: a storage medium having stored therein instructions which, when read by a computer, cause the computer to carry out a method of real-time offset correction applied to a detector as claimed in any preceding claim.
In some possible embodiments, the invention obtains the real-time column offset coefficient by disconnecting the passive pixel array from the post-stage active circuit and directly collecting the output of the post-stage circuit, and achieves the purpose of real-time correction by directly subtracting the output of the post-stage circuit from the corresponding column offset coefficient during normal pixel reading. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area completely; compared with the DRS function, the invention has smaller influence on the limit frame rate and noise under the same condition because the noise of a post-stage circuit is smaller when the pixel array is not mounted; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements.
Another technical solution of the present invention for solving the above technical problems is as follows: an electronic device includes the storage medium and a processor executing instructions in the storage medium.
In some possible embodiments, the invention obtains the real-time column offset coefficient by disconnecting the passive pixel array from the post-stage active circuit and directly collecting the output of the post-stage circuit, and achieves the purpose of real-time correction by directly subtracting the output of the post-stage circuit from the corresponding column offset coefficient during normal pixel reading. Compared with the DDS function, the invention does not need to add a complex hardware circuit, hardly influences the yield and does not increase the area completely; compared with the DRS function, the invention has smaller influence on the limit frame rate and noise under the same condition because the noise of a post-stage circuit is smaller when the pixel array is not mounted; meanwhile, the invention has very good flexibility because of no limitation of the number of physical dark pixels, and can select the most appropriate balance between noise and limit frame rate according to requirements.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described method embodiments are merely illustrative, and for example, the division of steps into only one type of logical functional division may be implemented in practice in other ways, for example, multiple steps may be combined or integrated into another step, or some features may be omitted, or not implemented.
The above method, if implemented in the form of software functional units and sold or used as a stand-alone product, can be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for real-time offset correction for a detector, comprising:
step 1, controlling an analog switch between a pixel array and a rear-stage column signal reading circuit in a detector to be turned off, and simultaneously controlling an input end of the rear-stage column signal reading circuit to be in a reset state;
step 2, in the reset state, collecting a first digital output value of a digital conversion circuit in the detector, and taking the first digital output value of each path as a bias coefficient corresponding to a current column of pixels in the pixel array;
step 3, controlling the analog switch to be turned on, and simultaneously controlling the input end of the post-stage column signal reading circuit to be in a working state;
step 4, collecting a second digital output value of the analog-digital conversion circuit in the detector under the working state, and determining the difference between the second digital output value and the offset coefficient of the corresponding column in the pixel array as a corrected output value after the real-time offset correction of the current row at a plurality of columns of pixels is completed;
and 5, scanning line by line and repeating the steps 3 to 4 until the corrected output values of all the pixels of the pixel array are obtained.
2. The real-time offset correction method applied to the detector according to claim 1, wherein the step 1 specifically comprises:
when the detector is in exposure time, the analog switch between the pixel array and the rear-stage column signal reading circuit is turned off through the register configuration, and meanwhile, the input end of the rear-stage column signal reading circuit is controlled to be in a reset state through the register configuration.
3. The method for real-time offset correction applied to a detector according to claim 1, wherein the step 2 is followed by further comprising:
and correspondingly forming pixel pairs by the offset coefficient of each column and the pixel array one by one, and storing the pixel pairs into a storage device of the detector.
4. The method according to claim 2, wherein the step of acquiring the first digital output value of each analog-to-digital conversion circuit in the detector comprises:
taking the single-acquisition digital output value of the analog-to-digital conversion circuit subjected to linear conversion as a first digital output value;
or taking the average value of the digital output values acquired for multiple times by the analog-to-digital conversion circuit after linear conversion as the first digital output value.
5. A real-time offset correction system for a detector, comprising:
the first control module is used for controlling the analog switch between the pixel array in the detector and the rear-stage column signal reading circuit to be turned off and controlling the input end of the rear-stage column signal reading circuit to be in a reset state;
the first acquisition module is used for acquiring a first digital output value of the analog-to-digital conversion circuit in the detector in the reset state, and taking the first digital output value of each path as a bias coefficient corresponding to a current column of pixels in the pixel array;
the second control module is used for controlling the analog switch to be turned on and controlling the input end of the rear-stage column signal reading circuit to be in a working state;
the correction module is used for acquiring a second digital output value of the analog-digital conversion circuit in the detector under the working state, and determining the difference between the second digital output value and the offset coefficient of the corresponding column in the pixel array as a correction output value after the real-time offset correction of the pixels in multiple columns in the current row is completed;
and the result module is used for scanning line by line and repeating the second control module and the correction module until the correction output values of all pixels of the pixel array are obtained.
6. The system of claim 5, wherein the first control module is specifically configured to:
when the detector is in exposure time, the analog switch between the register configuration pixel array and the rear-stage column signal reading circuit is turned off, and meanwhile, the input end of the rear-stage column signal reading circuit is controlled to be in a reset state through register configuration.
7. The system of claim 5, further comprising:
and the storage module is used for correspondingly forming pixel pairs by the bias coefficients of each column and the pixel array one by one and storing the pixel pairs into a storage device of the detector.
8. The system of claim 5, wherein the first building block is specifically configured to:
the process of collecting the first digital output value of the column analog-to-digital conversion circuit in the detector is as follows:
taking the single-acquisition digital output value of the analog-to-digital conversion circuit subjected to linear conversion as a first digital output value;
or taking the average value of the digital output values acquired for multiple times by the analog-to-digital conversion circuit after linear conversion as the first digital output value.
9. A storage medium having stored therein instructions which, when read by a computer, cause the computer to carry out a real-time offset correction method as claimed in any one of claims 1 to 4 applied to a detector.
10. An electronic device comprising the storage medium of claim 9, a processor executing instructions within the storage medium.
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| US20090033779A1 (en) * | 2007-07-31 | 2009-02-05 | Micron Technology, Inc. | Method, apparatus, and system providing multi-column shared readout for imagers |
| CN101415072A (en) * | 2004-07-02 | 2009-04-22 | 富士通株式会社 | Imaging device, control method thereof and CMOS image sensor |
| CN111447382A (en) * | 2020-04-08 | 2020-07-24 | 电子科技大学 | Focal plane array non-uniformity correction method and correction circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101415072A (en) * | 2004-07-02 | 2009-04-22 | 富士通株式会社 | Imaging device, control method thereof and CMOS image sensor |
| US20090033779A1 (en) * | 2007-07-31 | 2009-02-05 | Micron Technology, Inc. | Method, apparatus, and system providing multi-column shared readout for imagers |
| CN111447382A (en) * | 2020-04-08 | 2020-07-24 | 电子科技大学 | Focal plane array non-uniformity correction method and correction circuit |
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