CN115664423A - Sigma-delta modulator and analog signal processing circuit - Google Patents
Sigma-delta modulator and analog signal processing circuit Download PDFInfo
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- CN115664423A CN115664423A CN202211263456.8A CN202211263456A CN115664423A CN 115664423 A CN115664423 A CN 115664423A CN 202211263456 A CN202211263456 A CN 202211263456A CN 115664423 A CN115664423 A CN 115664423A
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Abstract
The invention discloses a sigma-delta modulator and an analog signal processing circuit for sensor detection. The method comprises the following steps: an input node configured to receive an analog input signal; a first feed-forward path for forward amplifying an analog input signal; an adder circuit for obtaining the sum of the forward amplified analog input signal and the feedback signal; a loop filter comprising a plurality of integrator circuits for transmitting an integrated signal in accordance with the summed signal; a plurality of second feed-forward paths, each second feed-forward path for forward amplification of the integrated signal; a summation stage circuit for obtaining a sum between the forward amplified analog input signal and the forward amplified integrated signal; and a quantizer for forming a digital output signal from the output signal of the summing stage circuit. The sigma-delta modulator has the characteristics of gain programmability, high common-mode rejection ratio and the like, and is applicable to an ADC front-end amplifying circuit for high-precision detection.
Description
Technical Field
The present invention relates to the field of high precision sensor detection technology, and more particularly, to a sigma-delta modulator and analog signal processing circuit for sensor detection.
Background
Analog signal processing circuits have found wide application in electronic devices. The analog signal is a signal which is continuous in both the amplitude domain and the time domain, and the analog signal processing includes amplification, filtering, modulation, demodulation, frequency conversion, and the like of the analog signal.
In sensor applications, analog signal processing circuitry determines to a large extent the performance of the sensor. As shown in fig. 1, a signal chain (signal chain) 100 of a sensor includes: an Analog Front End circuit (AFE), an Analog to Digital converter (ADC), and a Digital signal Processing (DP). The analog front end circuit AFE further includes a bias circuit (bias circuit) 101, a sensing or readout circuit (sensing or readout circuit) 102, a tunable gain amplifier (tunable gain amplifier) 103, and an anti-aliasing low pass filter (anti-aliasing low pass filter) 104. The analog front-end circuit AFE is an analog signal processing circuit in the signal chain of the sensor.
In order to adapt to input signals of different amplitude ranges, the AFE analog front end is generally required to be capable of realizing programmable gain, and conventionally, the AFE analog front end is designed into a Programmable Gain Amplifier (PGA), the PGA is realized by a chopper amplifier and a gain resistor, and different gain resistance values are selected through switches, so that the programmable gain function is realized. However, this method has the problem that the gain resistance of the PGA can only be trimmed once in practical application, and when different gains are selected, the offset voltage (offset) equivalent to the input terminal will change, which results in a large change in the Common Mode Rejection Ratio (CMRR) of the circuit at different gains, and poor stability.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a sigma-delta modulator and an analog signal processing circuit for sensor detection, which combine the characteristics of gain programmability and high common-mode rejection ratio.
According to an aspect of an embodiment of the present invention, there is provided a sigma-delta modulator for sensor detection, comprising: an input node configured to receive an analog input signal; a first feed-forward path coupled to the input node for forward amplifying the analog input signal; an adder circuit for obtaining a sum between the analog input signal after forward amplification and a feedback signal; a loop filter coupled to the adder circuit and including a cascaded plurality of integrator circuits for transmitting an integrated signal according to the summed signal obtained by the adder circuit; a plurality of second feed-forward paths, each for forward amplifying an integrated signal output by a respective integrator circuit; a summing stage circuit for obtaining a sum between the forward amplified analog input signal and the forward amplified integrated signal; and a quantizer coupled to the output node and arranged to receive the output signal of the summing stage and to form a digital output signal from the output signal of the summing stage.
Optionally, the sigma-delta modulator further comprises: a feedback path coupling the output node to the adder circuit for providing the feedback signal to the adder circuit in accordance with the digital output signal.
Optionally, the feedback path comprises a digital-to-analog converter.
Optionally, a first forward amplifier having a first feed-forward factor is disposed in the first feed-forward path.
Optionally, a second forward amplifier having a second feedforward factor is disposed in the second feedforward path.
Optionally, the loop filter further includes: a gain amplifier disposed before each of the integrator circuits, respectively, for gain amplifying the signal supplied to the corresponding integrator circuit.
Optionally, the sigma-delta modulator is a2 nd order sigma-delta modulator.
Optionally, the signal transfer function of the sigma-delta modulator is:
H x (z)＝m
wherein m is a first feed forward factor of the first forward amplifier.
Optionally, the programmable gain adjustment of the analog input signal is achieved by adjusting a value of the first feedforward factor.
Optionally, the noise transfer function of the sigma-delta modulator is:
where a1 and a2 are the gain factors of the gain amplifier before each integrator circuit in the loop filter, c1 and c2 are the second feedforward factors of each second forward amplifier, and z is the discrete time domain.
According to another aspect of the embodiments of the present invention, there is provided an analog signal processing circuit including: the pre-stage amplification module is used for carrying out fixed gain amplification on the differential input signal to obtain a processed signal; a programmable gain modulator for converting the processed signal into a modulated signal; and a digital filter for filtering the modulated signal to obtain a digital signal, wherein the programmable gain modulator is implemented by the sigma-delta modulator described above.
Optionally, the pre-stage amplifying module includes: the differential input circuit comprises a switch modulator, a chopper amplifier and first to fifth resistors, wherein first ends of the first resistor and the second resistor are respectively coupled to a positive input voltage signal and a negative input voltage signal of the differential input signal, second ends of the first resistor and the second resistor are coupled to a positive input end and a negative input end of the chopper amplifier through the switch modulator, a positive output end and a negative output end of the chopper amplifier are respectively used for providing a positive output voltage signal and a negative output voltage signal of a processed signal, the third resistor and the fifth resistor are sequentially coupled to an input end of the switch modulator and a negative output end of the chopper amplifier, and the fourth resistor is coupled between the input end of the switch modulator and the positive output end of the chopper amplifier.
Optionally, the first resistor and the second resistor have the same resistance, and the third resistor and the fourth resistor have the same resistance.
Optionally, resistance values of the first resistor, the second resistor, the third resistor, and the fourth resistor are used to set a gain of the pre-stage amplifier module.
Optionally, the fifth resistor is a variable resistor.
In summary, the present invention provides a sigma-delta modulator for use in the field of sensor detection, which employs a feed-forward path to perform forward amplification on an analog input signal, and then adjusts an amplification factor of the input signal to implement a programmable gain characteristic on the input signal. When the sigma-delta modulator is applied to an analog signal processing circuit in a sensor signal chain, a preceding-stage amplification module can be designed to be a fixed gain, and the gain adjustment of an input signal is realized through the sigma-delta modulator, so that after the offset voltage of the preceding-stage amplification module is adjusted, the offset voltage of a signal input end cannot be influenced even if the gain of the circuit is changed, and the circuit has good CMRR characteristics under different gains. In addition, the sigma-delta modulator of the embodiment can push most quantization noise into a high frequency region and filter the quantization noise through oversampling, noise shaping, digital filtering and sampling, and has good noise suppression performance. Therefore, the sigma-delta modulator according to the embodiment of the present invention has the characteristics of programmable gain and high common mode rejection ratio, and can be applied to the field of high-precision sensor detection, especially to the case where the CMRR requirement is relatively high.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic block diagram of a typical signal chain of a sensor;
fig. 2 shows a schematic circuit diagram of a programmable gain amplifier according to the prior art;
FIG. 3 shows a schematic circuit diagram of an analog signal processing circuit according to an embodiment of the invention;
fig. 4 shows a schematic block diagram of a sigma-delta modulator for sensor detection according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are identified with the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "coupled" to another element or element/circuit is referred to as being "coupled" between two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly coupled" to another element, it is intended that there are no intervening elements present.
The invention is further illustrated by the following examples in conjunction with the drawings.
Fig. 2 shows a schematic circuit diagram of a programmable gain amplifier according to the prior art. As shown in fig. 2, the programmable gain amplifier 103 includes a switching modulator 131, a chopper amplifier 132, and resistors R1 to R5. First ends of the resistor R1 and the resistor R2 are electrically connected to a positive input voltage signal VIP and a negative input voltage signal VIN in the differential input signal, respectively. The switch-modulator 131 includes a first input terminal, a second input terminal, a first output terminal and a second output terminal, and the first input terminal and the second input terminal of the switch-modulator 131 are electrically connected to the second terminal of the resistor R1 and the second terminal of the resistor R2, respectively. The chopper amplifier 132 includes a positive input end, a negative input end, a positive output end, and a negative output end, the positive input end and the negative input end of the chopper amplifier 132 are electrically connected to the first output end and the second output end of the switch modulator 131, respectively, and the positive output end and the negative output end of the chopper amplifier 132 are used for outputting a positive output voltage signal VOP and a negative output voltage signal VON in the differential output signal, respectively. Resistors R3 and R5 are, in turn, electrically connected between the first input terminal of switch-modulator 131 and the negative output terminal of chopper amplifier 132, and resistor R4 is electrically connected between the second input terminal of switch-modulator 131 and the positive output terminal of chopper amplifier 132. It should be noted that the chopper amplifier 132 may be implemented by a fully differential chopper-modulated cascode amplifier, and the circuit structure is not limited.
In the embodiment of fig. 2, the resistors R1 and R2 have the same resistance, and the resistors R3 and R4 have the same resistance, which determine the gain of the preamplifier. The chopper amplifier 102 eliminates the influence of the offset voltage and low-frequency noise thereof on the common-mode rejection ratio of the whole architecture by adopting a chopping technology. However, in practical applications, the resistances of the resistors R1 to R4 cannot be perfectly matched, so that the resistor R5 may be a variable resistor, and the resistance of the resistor R5 is adjusted by the trimming signal Trim to compensate for mismatch between the resistors R1 to R4, so that the offset voltage of the front-end analog front-end circuit (AFE) is minimized, and the common-mode rejection ratio CMRR of the system is greatly improved.
However, the problem of the analog front-end circuit AFE in the prior art is that the gain resistance can be modified only once in practical application, and when different gains are selected, the offset voltage equivalent to the input end of the analog front-end circuit AFE also changes, so that the common-mode rejection ratio CMRR of the circuit under different gains changes greatly, and the circuit stability is poor.
Fig. 3 shows a schematic circuit diagram of an analog signal processing circuit according to an embodiment of the invention. As shown in fig. 3, the analog signal processing circuit 200 includes a pre-amplification block 210, a programmable gain modulator 220, and a digital filter 230. In the whole circuit structure, the pre-stage amplification module 210 is configured to perform fixed gain amplification on the differential input signals VIN and VIP to obtain a processed signal, where the processed signal includes differential output signals VON1 and VOP1, the programmable gain modulator 220 is configured to convert the processed signal into a modulation signal S1, and the digital filter 230 is configured to filter the modulation signal S1 to obtain a digital signal Dout.
In this embodiment, the pre-amplification module 210 includes a first input terminal for receiving a positive input voltage signal VIP of the differential input signal and a second input terminal for receiving a negative input voltage signal VIN of the differential input signal, and a first output terminal for providing a negative output voltage signal VON of the differential output signal and a second output terminal for providing a positive output voltage signal VOP of the differential output signal.
In the present embodiment, the pre-amplification module 210 includes a switch modulator 201, a chopper amplifier 202, and resistors R1 to R5. The switch-modulator 201 comprises, for example, a plurality of switches for chopping the input signal to obtain a high frequency square wave signal.
In the present embodiment, first ends of the resistor R1 and the resistor R2 are electrically connected to a positive input voltage signal VIP and a negative input voltage signal VIN of the differential input signal, second ends of the resistor R1 and the resistor R2 are electrically connected to a positive input end and a negative input end of the chopper amplifier 202 via the switch modulator 201, respectively, a positive output end of the chopper amplifier 202 is used for providing a positive output voltage signal VOP of the differential output signal, a negative output end of the chopper amplifier 202 is used for providing a negative output voltage signal VON of the differential output signal, a first end of the resistor R3 is electrically connected to the positive input end of the chopper amplifier 202 via the switch modulator 201, a second end of the resistor R3 is electrically connected to a first end of the resistor R5, a second end of the resistor R5 is electrically connected to the negative output end of the chopper amplifier 202, a first end of the resistor R4 is electrically connected to the negative input end of the chopper amplifier 202 via the switch modulator 201, and a second end of the resistor R4 is electrically connected to the positive output end of the chopper amplifier 202.
In this embodiment, the chopper amplifier 202 may be implemented by a fully-differential chopper-modulated cascode amplifier, and the circuit structure thereof is not limited.
In the present embodiment, the resistances of the resistor R1 and the resistor R2 are equal, and the resistances of the resistor R3 and the resistor R4 are equal, which determine the gain of the preamplifier. The chopper amplifier 202 eliminates the influence of the offset voltage and low-frequency noise thereof on the common-mode rejection ratio of the whole architecture by adopting a chopping technology. However, in practical applications, the resistances of the resistors R1 to R4 cannot be perfectly matched, so that the resistor R5 may be a variable resistor, and the resistance of the resistor R5 is adjusted by the trimming signal Trim to compensate for mismatch between the resistors R1 to R4, so that the offset voltage of the front-end analog front-end circuit (AFE) is minimized, and the common-mode rejection ratio CMRR of the system is greatly improved.
Different from the analog signal processing circuit in the prior art, the pre-amplifier module 210 of the present embodiment is designed to be a fixed gain, and the gain of the circuit is realized by the programmable gain modulator 220, that is, after the offset voltage of the pre-amplifier module is adjusted by trimming (Trim), the offset voltage at the input end of the circuit is not affected by changing the gain of the circuit, so that the circuit has good CMRR characteristics under different gains.
In the present embodiment, the programmable gain modulator 220 is, for example, a sigma-delta modulator. For the purpose of introducing embodiments, the operation of a known sigma-delta modulator (also known as a sigma-delta modulator, such as may be used for an ADC) will be discussed. Sigma-delta modulators may provide better noise performance than conventional ADCs by oversampling, noise shaping, digital filtering, and sampling. ADCs employing sigma-delta modulators (which are typically referred to as sigma-delta ADCs) may provide performance advantages in allowing high dynamic range signals to be received with little power consumption. The power advantage of using a sigma-delta modulator can only be maximized if the digital filter following the sigma-delta modulator can be efficiently implemented. The high oversampling output of the sigma-delta modulator places an additional processing burden on the digital domain, resulting in increased power consumption. The analog side of the ADC (1-bit ADC/DAC and filter) can be relatively simple. The digital side performs filtering and decimation (decimation) and reduces ADC cost to meet practical production.
The operating principle of sigma-delta modulators is well known. In general terms, an input analog signal is fed to a feedback loop that includes an analog filter (such as an integrator that applies noise shaping) followed by a digital converter that samples the signal and a feedback loop that uses a DAC. The output signal of the sigma-delta modulator is a bit stream higher than the sampling rate. Alternatively, the oversampled bit stream may be fed to subsequent digital processing which converts the bit stream into a lower rate representation of the information signal by decimation and digital filtering to provide a stream having more bit values and a lower sampling frequency. The oversampling frequency is set to kfs, where fs is the nyquist sampling frequency and k is the oversampling ratio. Oversampling lowers the noise floor (noise floor) to the same bandwidth. The signal-to-noise ratio (SNR) in the frequency range 0 to fs is the same as before, however the noise energy has been extended to a wider frequency range. The sigma-delta ADC exploits this effect by following a 1-bit ADC with digital filtering. Because the subsequent digital filter removes most of the noise, the RMS noise is reduced. This operation enables the sigma-delta ADC to achieve a wide dynamic range with a low resolution digital converter. A loop filter in the form of an integrator function is used as a low-pass filter for its input signal by adding an error voltage as the difference between the input signal and the feedback signal. Most of the quantization noise is forced into higher frequencies where it is filtered out by a digital filter.
In the present embodiment, oversampling and integration do not change the total noise power, but the distribution of the noise power. The digital filter described above can be represented by the digital filter 230 in fig. 3, and the digital filter 230 can average the 1-bit digital stream, improve the ADC resolution, and remove quantization noise outside the frequency band of interest, thus having a good effect on noise suppression.
Fig. 4 shows a schematic block diagram of a sigma-delta modulator for sensor detection according to an embodiment of the present invention. In fig. 4, a 1-bit quantized sigma-delta modulator with a 2-order full feed-forward structure is shown by way of example. The sigma-delta modulator is illustrated in the present embodiment using a z-domain (discrete time domain) model, which can be realized both due to analog switched capacitor time and digital of the modulator. The z-domain description may be transformed into a continuous time domain description to provide an RC modulator implementation. Where X (z) and Y (z) are z-domain representations of the input signal and the output signal, respectively, having signal values at discrete time instants. The modulator 300 includes: forward amplifiers 301, 307, 308, and 309, adder 302, gain amplifiers 303 and 305, integrators 304 and 306, summing stage circuit 310, and quantizer 311.
For simplicity, the same names (e.g., X and Y) will be used to refer to both a certain signal and a circuit node/element where such a signal may be present. And the name "adder node" will be applied to certain circuit nodes that add two or more signals together: as known to those skilled in the art, such nodes may be "signed", i.e. nodes that add a certain signal to one or more other signals having a negative sign, i.e. subtract the one or more other signals from the combination. In other words, marking a node as an adder node does not mean that the signals added at that node are added with the same sign.
In the modulator 300, a forward amplifier 301 is provided on a feed-forward path 321 between the input node to the adder 302. The adder 302 is connected to the output of the forward amplifier 301 for obtaining a sum between the output of the forward amplifier 301 and the feedback signal.
The gain amplifier 303, the integrator 304, the gain amplifier 305 and the integrator 306 are arranged on a loop filter 320 coupled to the output of the adder 302, the loop filter 320 being arranged to filter the summed signal obtained by the adder 302. Further, the integrated signal is transmitted on the loop filter 320 by the integrators 304 and 306 according to the sum signal obtained by the adder 302. The forward amplifier 307 is arranged in a feed forward path 322 between said input node to a first input of the summing stage 310, the forward amplifier 308 is arranged in a feed forward path 323 between the output of said integrator 304 to a second input of the summing stage 310, the forward amplifier 309 is arranged in a feed forward path 324 between the output of said integrator 306 to a third input of the summing stage 310, and the summing stage 310 is arranged to sum the amplified signals of the forward amplifiers 307 to 309. The quantizer 311 is arranged to receive the output signal of the summing stage circuit 310 and to form a digital output signal Y (z) from the output signal of the summing stage circuit 310.
In this embodiment, the modulator 300 further comprises a DAC 313 located in a feedback path for receiving the output signal Y (z), an output path from the output signal Y (z) is connected to an input port of the DAC 313, and an output of the DAC 313 is connected to one input port of the adder 302 to form a feedback loop.
In this embodiment, the input signal X (z) from the input node is amplified by the forward amplifier 301 with the feedforward factor m, the amplified signal is added to the feedback signal from the DAC 313 at the adder node 302, as previously described, the node 302 may be a "signed" adder node, wherein in practice the feedback signal obtained via the DAC 313 is subtracted from the amplified signal of the input signal X (z) as conventionally in sigma-delta modulators. The output signal of the adder 302 is amplified by a gain amplifier 303 having a gain factor a1 and then supplied to an input port of an integrator 304, and the integrator 304 obtains an integrated signal according to the weighting of the input signal X (z) and the feedback signal.
The output of the integrator 304 is amplified by a forward amplifier 308 having a feed forward factor c1 on a feed forward path 323, and the output of the forward amplifier 308 is provided to a second input of the summing stage 310. Further, the input signal X (z) is amplified by the forward amplifier 307 with the feedforward factor m on the feedforward path 322, the output of the forward amplifier 307 is provided to the first input terminal of the summing stage circuit 310, the output of the integrator 304 is amplified by the gain amplifier 305 with the gain factor a2 on the loop filter, the output of the gain amplifier 305 is provided to the input port of the integrator 306, the output of the integrator 306 is amplified by the forward amplifier 309 with the feedforward factor c2 on the feedforward path 324, the output of the forward amplifier 309 is provided to the third input terminal of the summing stage circuit 310, finally the sum of the forward amplifiers 307 to 309 is obtained by the summing stage circuit 310, the output of the summing stage circuit 310 generates the quantization error E (z) after comparison in the quantizer 311, and finally the output signal Y (z) is obtained.
In this embodiment, the sigma-delta modulator 300 employs a 1-bit quantization architecture, so the feedback of the DAC 313 is 1, while the z-domain transfer function of the integrator is:
as a result, the output Y (in the frequency domain or z domain) of the sigma-delta modulator 300 of the present embodiment is:
[m×X(z)-Y(z)]×a1×H(z)×[c1+a2×H(z)×c2]+m×
X(z)+E(z)＝Y(z) (2)
where Y (z) represents a z-domain value of the output signal, X (z) represents the input signal, E (z) represents a quantization error of the quantizer 311, m, c1, and c2 represent feed forward factors, and a1 and a2 represent gain factors of the integrator.
Simplifying the formula (2) can obtain:
Y(z)＝H x (z)×X(z)+H e (z)×E(z) (3)
wherein H x (z) is a Signal Transfer Function (STF) that describes a function of the performance of the transition from input X to output Y. And H e (z) is the Noise Transfer Function (NTF) of the equivalent discrete-time sigma-delta modulator to which the sigma-delta modulator 300 is mapped for analysis using techniques well known to those skilled in the art, which describes a function of the performance transferred from the noise source to the output Y.
Substituting the values of the gain factor and the feedforward factor of the integrator in equation (3) yields:
H x (z)＝m (4)
as can be seen from the equations (4) and (5), the whole system can amplify the input signal by m times, and the programmable gain characteristic of the input signal can be realized by changing the value of the feedforward factor m. Whereas in the modulator 300 shown in fig. 4 the loop filter is an integrator, the modulator shapes the noise out of the low frequency region and into the high frequency region. This is because the integrator sums the error voltages and thus acts as a low pass filter for the input signal and a high pass filter for the quantization noise. Thus, most of the quantization noise is pushed into the high frequency region, and more noise can be removed in conjunction with the digital filter of fig. 3. The modulator of this embodiment therefore suppresses quantization noise as in the case of currently known sigma-delta modulators, and a good noise performance can be achieved by oversampling, noise shaping, digital filtering and sampling.
It should be noted that although the present embodiment is described in conjunction with a 1-bit quantization and 2-order full feed-forward sigma-delta modulator in fig. 4, the present invention may also use a multi-bit quantization or other order sigma-delta modulator by changing the number of integrators and the number of bits of the DAC in the loop filter.
In summary, the present invention provides a sigma-delta modulator for use in the field of sensor detection, which employs a feed-forward path to perform forward amplification on an analog input signal, and then adjusts the amplification factor of the input signal to implement a programmable gain characteristic on the input signal. When the sigma-delta modulator is applied to an analog signal processing circuit in a sensor signal chain, a preceding-stage amplification module can be designed to be a fixed gain, and the gain adjustment of an input signal is realized through the sigma-delta modulator, so that after the offset voltage of the preceding-stage amplification module is adjusted, the offset voltage of a signal input end cannot be influenced even if the gain of the circuit is changed, and the circuit has good CMRR characteristics under different gains. In addition, the sigma-delta modulator of the embodiment can push most quantization noise into a high frequency region and filter the quantization noise through oversampling, noise shaping, digital filtering and sampling, and has good noise suppression performance. Therefore, the sigma-delta modulator according to the embodiment of the present invention has the characteristics of gain programmability and high common mode rejection ratio, and can be applied to the field of high-precision sensor detection, particularly, in the case where the CMRR requirement is relatively high.
It will be understood by those of ordinary skill in the art that the words "during," "when," and "when 8230; \8230when" as used herein in connection with the operation of a circuit are not strict terms referring to actions occurring immediately upon the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
Moreover, it is further understood that the use of relational terms such as first and second, and the like, herein, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (15)
1. A sigma-delta modulator for sensor detection, comprising:
an input node configured to receive an analog input signal;
a first feed-forward path coupled to the input node for forward amplifying the analog input signal;
an adder circuit for obtaining a sum between the analog input signal after forward amplification and a feedback signal;
a loop filter coupled to the adder circuit and including a cascaded plurality of integrator circuits for transmitting an integrated signal according to the summed signal obtained by the adder circuit;
a plurality of second feed-forward paths, each for forward amplifying an integrated signal output by a respective integrator circuit;
a summing stage circuit for obtaining a sum between the forward amplified analog input signal and the forward amplified integrated signal; and
a quantizer, coupled to the output node, arranged to receive the output signal of the summing stage circuit and form a digital output signal from the output signal of the summing stage circuit.
2. The sigma-delta modulator of claim 1, further comprising:
a feedback path coupling the output node to the adder circuit for providing the feedback signal to the adder circuit in accordance with the digital output signal.
3. A sigma-delta modulator as claimed in claim 2, wherein the feedback path comprises a digital-to-analogue converter.
4. A sigma-delta modulator as claimed in claim 1, wherein a first forward amplifier having a first feedforward factor is provided in the first feedforward path.
5. A sigma-delta modulator as claimed in claim 4, wherein a second forward amplifier having a second feedforward factor is provided in the second feedforward path.
6. The sigma-delta modulator of claim 5, wherein the loop filter further comprises:
a gain amplifier disposed before each of the integrator circuits, respectively, for gain amplifying the signal supplied to the corresponding integrator circuit.
7. A sigma-delta modulator as claimed in claim 6, wherein the sigma-delta modulator is a 2-order sigma-delta modulator.
8. A sigma-delta modulator as claimed in claim 7, wherein the signal transfer function of the sigma-delta modulator is:
H x (z)＝m
wherein m is a first feed forward factor of the first forward amplifier.
9. A sigma-delta modulator as claimed in claim 8, wherein the programmable gain adjustment of the analogue input signal is achieved by adjusting the value of the first feedforward factor.
10. A sigma-delta modulator as claimed in claim 7, wherein the noise transfer function of the sigma-delta modulator is:
where a1 and a2 are the gain factors of the gain amplifier before each integrator circuit in the loop filter, c1 and c2 are the second feedforward factors of each second forward amplifier, and z is the discrete time domain.
11. An analog signal processing circuit comprising:
the pre-stage amplification module is used for carrying out fixed gain amplification on the differential input signal to obtain a processed signal;
a programmable gain modulator for converting the processed signal into a modulated signal; and
a digital filter for filtering the modulated signal to obtain a digital signal,
wherein the programmable gain modulator is implemented by a sigma-delta modulator as claimed in any of claims 1 to 10.
12. The analog signal processing circuit of claim 11, wherein the pre-amplification module comprises: a switching modulator, a chopper amplifier, and first to fifth resistors,
wherein the first ends of the first resistor and the second resistor are respectively coupled to the positive input voltage signal and the negative input voltage signal of the differential input signal,
second ends of the first and second resistors are coupled to positive and negative inputs of the chopper amplifier via the switch-modulator,
the positive output end and the negative output end of the chopper amplifier are respectively used for providing a positive output voltage signal and a negative output voltage signal of a processing signal,
the third resistor and the fifth resistor are sequentially coupled to the input end of the switch modulator and the negative output end of the chopper amplifier,
the fourth resistor is coupled between the input end of the switch modulator and the positive output end of the chopper amplifier.
13. The analog signal processing circuit of claim 12, wherein the first resistor and the second resistor have equal resistance values, and the third resistor and the fourth resistor have equal resistance values.
14. The analog signal processing circuit of claim 13, wherein resistance values of the first resistor, the second resistor, the third resistor, and the fourth resistor are used to set a gain of the pre-amplification module.
15. The analog signal processing circuit of claim 12, wherein the fifth resistance is a variable resistor.
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