CN115664397B - PWM regulating circuit and chip - Google Patents
PWM regulating circuit and chip Download PDFInfo
- Publication number
- CN115664397B CN115664397B CN202211652902.4A CN202211652902A CN115664397B CN 115664397 B CN115664397 B CN 115664397B CN 202211652902 A CN202211652902 A CN 202211652902A CN 115664397 B CN115664397 B CN 115664397B
- Authority
- CN
- China
- Prior art keywords
- frequency
- value
- register
- duty ratio
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention provides a PWM regulating circuit and a chip, comprising: a frequency adjusting module, a duty ratio adjusting module, a clock module and a comparing module,a clock module provides a clock reference for the PWM regulating circuit; the frequency adjusting module realizes the maximum value of the frequency of the PWM signal to be 2 through a first threshold value N The precision of the fundamental frequency is improved; the duty ratio adjusting module enables the duty ratio of the PWM signal to achieve a maximum value of 2 through a second threshold value M The precision of the times is improved; the comparison module is connected with the output ends of the clock module, the frequency adjustment module and the duty ratio adjustment module, performs clock counting based on a clock reference, and generates PWM signals with improved frequency and duty ratio precision by comparing the clock count value with the output value of the frequency adjustment module and comparing the clock count value with the output value of the duty ratio adjustment module. The minimum adjustable precision of the frequency and the resolution of the PWM signal is not limited by the frequency of the main clock, and the precision of the PWM signal is equivalently improved. Simple structure, easy and simple to handle, application scope is wide.
Description
Technical Field
The present invention relates to the field of integrated circuit design and application technology, and in particular, to a PWM regulator circuit and a chip.
Background
PWM, i.e., pulse width modulation (Pulse Width Modulation), is widely used in driving power supplies, motors, LED lighting, audio power amplifiers, and the like. For the traditional counting type PWM circuit, the duty ratio and the frequency are determined by a common main clock period, the frequency and the duty ratio of the PWM signal are set through register configuration, and after the register configuration is completed, the highest precision of the frequency and the duty ratio of the PWM signal is equal to one main clock period, and the frequency and the duty ratio of the PWM signal cannot be improved under the condition that a prescaler is not used.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a PWM adjusting circuit and a chip, which are used for solving the problem in the prior art that how to improve the accuracy of the frequency and the duty ratio of the PWM signal without using a prescaler.
To achieve the above and other related objects, the present invention provides a PWM adjusting circuit comprising: frequency regulation module, duty cycle regulation module, clock module and comparison module, wherein:
the clock module provides a clock reference for the PWM regulating circuit;
the frequency adjusting module enables the frequency of the PWM signal to achieve maximum value of 2 through a first threshold value N The precision of the fundamental frequency is improved, wherein N is a natural number which is more than or equal to 1;
the duty ratio adjusting module enables the duty ratio of the PWM signal to achieve a maximum value of 2 through a second threshold value M The precision of the multiple is improved, wherein M is a natural number which is more than or equal to 1;
the comparison module is connected to the output ends of the clock module, the frequency adjustment module and the duty ratio adjustment module, performs clock counting based on a clock reference, and generates PWM signals with improved frequency and duty ratio precision by comparing the clock count value with the output value of the frequency adjustment module and the output value of the duty ratio adjustment module.
Optionally, the frequency adjustment module includes a frequency register and a frequency booster, where an input end of the frequency booster is connected to an output end of the frequency register, and the first threshold is generated by the frequency booster.
Optionally, the frequency register includes an integer bit frequency register and a fractional bit frequency register, wherein the integer bit frequency register determines an integer bit of the first threshold; the decimal frequency register determines the decimal of the first threshold, wherein the decimal frequency register has N output values, each output value forms an arithmetic series, the first term of the arithmetic series is 0, and the tolerance is 1/2 N And the maximum value of the series of arithmetic differences is less than 1.
Optionally, the frequency booster includes: a first cycle counter, a first 1-plus-arbiter, a first adder, and a first encoder, wherein:
the first adder is connected with the integer bit frequency register and a digital 1;
the first cycle counter is used for generating cycle periods, wherein the number of the cycle periods is 2 N ；
The input end of the first 1 adding judgment device is connected with the output end of the first cycle counter and the output end of the decimal frequency register;
the input end of the first encoder is connected with the output end of the first adder, the output end of the integer bit frequency register and the output end of the first 1-adding judger, wherein the bit number of the encoded value of the first encoder is equal to N, and the encoded value of the first encoder corresponds to the output value of the decimal bit frequency register one by one; based on the encoded value of the first encoder, to determine whether the first adder performs an addition operation of integer bits of the first threshold with a number "1", wherein the number of addition operations performed in each of the loop periods is equal to the encoded value of the first encoder.
Optionally, the duty cycle adjustment module includes a duty cycle register and a duty cycle lifter, wherein an input end of the duty cycle lifter is connected with an output end of the duty cycle register, and the second threshold is generated through the duty cycle lifter.
Optionally, the duty cycle register includes an integer duty cycle register and a fractional duty cycle register, wherein a value of the integer duty cycle register is equal to a value of an integer of the second threshold; the value of the decimal duty ratio register is equal to the value of the decimal of the second threshold, wherein the decimal duty ratio register has M output values, each output value forms an arithmetic sequence, the first term of the arithmetic sequence is 0, and the tolerance is 1/2 M And the maximum value of the series of arithmetic differences is less than 1.
Optionally, the duty cycle booster includes: a second cycle counter, a second 1-adding judger, a second adder and a second encoder, wherein:
the second adder is connected with the integer bit duty ratio register and the digital 1;
the second cycle counter is used for generating cycle periods, wherein the number of the cycle periods is 2 M ；
The input end of the second 1 adding judgment device is connected with the output end of the second cycle counter and the output end of the decimal duty ratio register;
the input end of the second encoder is connected with the output end of the second adder, the output end of the integer bit duty ratio register and the output end of the second 1-adding judger, wherein the bit number of the encoded value of the second encoder is equal to M, and the encoded value of the second encoder corresponds to the output value of the decimal bit duty ratio register one by one; based on the encoded value of the second encoder, to determine whether the second adder performs an addition operation of integer bits of the second threshold with a number "1", wherein the number of addition operations performed in each of the loop periods is equal to the encoded value of the second encoder.
Optionally, the clock module comprises a phase locked loop.
Optionally, the comparing module includes: counter, frequency comparator, duty cycle comparator and PWM output control unit, wherein:
the input end of the counter is connected with the output end of the clock module;
the frequency comparator is connected with the counter and the frequency adjusting module, wherein when the count value of the counter exceeds the first threshold value, the frequency comparator outputs a zero clearing signal which enables the counter to count again;
the duty ratio comparator is connected with the counter and the duty ratio adjusting module, wherein the duty ratio comparator obtains PWM signals with improved frequency and duty ratio precision by comparing output values of the counter and the duty ratio adjusting module;
the input end of the PWM output control unit is connected with the output end of the duty ratio comparator, and outputs PWM signals; and loading the frequency information of the PWM signal to the frequency comparator to synchronize the frequency.
To achieve the above and other related objects, the present invention provides a chip for generating a PWM signal with improved accuracy of both frequency and duty cycle, the chip including at least one of the PWM adjustment circuits.
As described above, the PWM regulating circuit and the chip have the following beneficial effects:
1) The PWM regulating circuit and the chip of the invention ensure that the minimum adjustable precision of the frequency and the resolution of the PWM signal is not limited by the main clock frequency, and equivalently improve the precision of the PWM signal.
2) The PWM regulating circuit and the chip have the advantages of simple structure, simple and convenient operation and wide application range.
Drawings
Fig. 1 shows a schematic diagram of a PWM regulating circuit according to the present invention.
Fig. 2 is a schematic circuit diagram of a frequency adjustment module according to the present invention.
Fig. 3 shows a schematic diagram of the PWM signal after the frequency accuracy is improved.
Fig. 4 is a schematic circuit diagram of the duty cycle adjustment module of the present invention.
Fig. 5 shows a schematic diagram of the PWM signal after the accuracy of the duty cycle is improved.
Description of the reference numerals
1-a PWM regulating circuit; 11-a frequency adjustment module; 111-frequency registers; 1111-integer bit frequency register; 1112-a decimal frequency register; 112-frequency booster; 1121-a first cycle counter; 1122-first plus 1 determiner; 1123-a first adder; 1124-first encoder; 12-a clock module; 121-a phase-locked loop; 13-a duty cycle adjustment module; 131-duty cycle register; 1311-integer duty cycle register; 1312-a decimal place duty cycle register; 132-duty cycle booster; 1321-a second cycle counter; 1322-second add 1 determiner; 1323-a second adder; 1324-a second encoder; 14-a comparison module; 141-a frequency comparator; 142-duty cycle comparator; 143-a counter; 144-PWM output control unit.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 1 to 5, the present embodiment provides a PWM adjusting circuit 1, the PWM adjusting circuit 1 including: a frequency adjustment module 11, a duty cycle adjustment module 13, a clock module 12 and a comparison module 14, wherein:
as shown in fig. 1, the clock module 12 provides a clock reference to the PWM adjustment circuit 1.
Specifically, as an example, clock module 12 includes a phase locked loop 121. It should be noted that, the phase-locked loop is a feedback circuit, and the phase-locked loop is used to synchronize the clock on the circuit with the phase of an external clock, and the phase-locked loop realizes synchronization by comparing the phase of an external signal with the phase of a voltage-controlled crystal oscillator, and in the process of comparison, the phase-locked loop circuit can continuously adjust the clock phase of the local crystal oscillator according to the phase of the external signal until the phases of the two signals are synchronized. In this embodiment, the PLL 121 provides the counter 143 of the comparing module 14 with the master clock pll_clk through phase synchronization, and one period of the master clock pll_clk is the minimum adjustable precision d of the PWM signal. It should be further noted that, the Phase-locked Loop is generally composed of a Phase Detector (PD), a Filter (LF), and a voltage-controlled oscillator (VCO, voltage Controlled Oscillator), and the Phase-locked Loop 121 is specifically disposed in a feedback path of a frequency Phase formed by a prescaler, which is not described in detail herein.
As shown in fig. 1, the frequency adjustment module 11 makes the frequency of the PWM signal achieve a maximum value of 2 through the first threshold UFREQ N The precision of the fundamental frequency is improved, wherein N is a natural number greater than or equal to 1.
Specifically, as an example, as shown in fig. 2, the frequency adjustment module 11 includes a frequency register 111 and a frequency booster 112, where an input terminal of the frequency booster 112 is connected to an output terminal of the frequency register 111, and the first threshold UFREQ is generated by the frequency booster 112.
More specifically, as shown in fig. 2, the frequency register 111 includes an integer bit frequency register 1111 and a decimal frequency register 1112, wherein the integer bit frequency register 1111 determines the integer digits of the first threshold UFREQ, wherein the value of the integer digits of the first threshold UFREQ is Φ; the decimal frequency register 1112 determines the decimal place of the first threshold UFREQ, wherein the decimal frequency register 1112 has N output values, each of which constitutes an arithmetic series with a first order of 0 and a tolerance of 1/2 N And the maximum value of the arithmetic series is less than 1. When N is equal to 2, that is, the frequency of the PWM signal achieves an improvement in accuracy of a maximum value of 4 times the fundamental frequency, the decimal frequency register 1112 has 4 output values of 0, 0.25, 0.5, and 0.75, respectively. It should be noted that, because there is a decimal place, the first threshold UFREQ is a dynamically changing value, the dynamically changing amount is determined by the decimal frequency register 1112, and the number of kinds of values of the decimal frequency register 1112 is related to the first encoder 1124.
More specifically, as shown in fig. 2, the frequency booster 112 includes: a first cycle counter 1121, a first 1-up determiner 1122, a first adder 1123, and a first encoder 1124, wherein:
the first adder 1123 is connected to the integer bit frequency register 1111 and the number "1", wherein the first adder 1123 obtains Φ+1 after addition operation;
the first cycle counter 1121 is used to generate cycle periods, wherein the number of cycle periods is 2 N When N is equal to 2, the number of cycle periods is 4;
the input of the first add 1 arbiter 1122 is connected to the output of the first cycle counter 1121 and the output of the decimal frequency register 1112;
the input end of the first encoder 1124 is connected to the output end of the first adder 1123, the output end of the integer bit frequency register 1111 and the output end of the first add 1 judgment unit 1122, where the number of bits of the encoded value of the first encoder 1124 is equal to N, the encoded value of the first encoder 1124 corresponds to the output value of the decimal frequency register 1112 one by one, and when N is equal to 2, the encoded values of the first encoder 1124 are respectively 00, 01, 10 and 11, where 00, 01, 10 and 11 are binary encoded values, the output value of the decimal frequency register 1112 corresponding to 00 is 0, the output value of the decimal frequency register 1112 corresponding to 01 is 0.25, the output value of the decimal frequency register 1112 corresponding to 10 is 0.5, and the output value of the decimal frequency register 1112 corresponding to 11 is 0.75; determining whether the first adder 1123 performs an addition operation of the integer bit of the first threshold UFREQ with the number "1" based on the encoded value of the first encoder 1124, wherein the number of addition operations performed in each cycle period is equal to the encoded value of the first encoder 1124, wherein when the encoded value of the first encoder 1124 is 00, 00 is converted into 0 in decimal, indicating that the integer bit of the first threshold UFREQ is not subjected to an addition operation with the number "1"; when the code value of the first encoder 1124 is 01, the 01 is converted into decimal value 1, which indicates that the integer bit of the first threshold UFREQ and the number "1" perform 1 addition operation; when the encoded value of the first encoder 1124 is 10, the 10 is converted to a decimal value of 2, which indicates that the integer bits of the first threshold UFREQ are added 2 times with the number "1"; when the encoded value of the first encoder 1124 is 11, the encoded value of 11 is converted into decimal value of 3, which indicates that the integer bit of the first threshold UFREQ and the number "1" perform 3 addition operations, the corresponding relationship is as follows:
| first encoder [1:0 ]] | |
Cycle 2 | Cycle 3 | Cycle 4 |
| 00 | φ | φ | φ | φ |
| 01 | φ | φ | φ | φ+1 |
| 10 | φ | φ+1 | φ | φ+1 |
| 11 | φ | φ+1 | φ+1 | φ+1 |
The corresponding time sequence relationships of 00, 01, 10 and 11 are shown in fig. 3.
As can be seen from the correspondence, when the encoding value of the first encoder 1124 is 00, the frequency of the PWM signal is raised to 0; when the code value of the first encoder 1124 is 01, the frequency-improved accuracy of the PWM signal is 0.25d, where a period of the main clock pll_clk is the original minimum frequency adjustable accuracy d of the PWM signal, because the integer bits of the first threshold UFREQ and the number of the digits "1" are added 1 time, the number of the cycle periods is 4, and the digits "1" are evenly distributed in 4 cycle periods, that is, 0.25d can be obtained after weighting operation is performed on 0.25 and the original minimum frequency adjustable accuracy of the PWM signal, and meanwhile, 0.25 is the output value of the small digit frequency register 1112. It should be noted that, the addition operation of the integer bit of the first threshold UFREQ and the number "1" for 1 time is not necessarily limited to the 4 th cycle period, and should be flexibly set according to a specific usage scenario. Similarly, when the encoded value of the first encoder 1124 is 10, the frequency of the PWM signal is raised to 0.5d; when the code value of the first encoder 1124 is 11, the frequency of the PWM signal is raised to 0.75d, and the specific derivation is not described here.
As shown in fig. 1, the duty ratio adjusting module 13 makes the duty ratio of the PWM signal achieve a maximum value of 2 through the second threshold value UDUTY M And improving the precision of the multiple, wherein M is a natural number which is more than or equal to 1.
Specifically, as an example, as shown in fig. 1, the duty cycle adjustment module 13 includes a duty cycle register 131 and a duty cycle booster 132, where an input terminal of the duty cycle booster 132 is connected to an output terminal of the duty cycle register 131, and the second threshold value UDUTY is generated via the duty cycle booster 132.
More specifically, as shown in fig. 4, the duty cycle register 131 includes an integer duty cycle register 1311 and a decimal duty cycle register 1312, wherein the value of the integer duty cycle register 1311 is equal to the integer value of the second threshold UDUTYWherein the value of the integer bits of the second threshold UDUTY is δ; the value of the fractional duty cycle register 1312 is equal to the value of the fractional digits of the second threshold value UDUTY, wherein the fractional duty cycle register 1312 has M output values, each output value forms an arithmetic series, the first term of the arithmetic series is 0, and the tolerance is 1/2 M And the maximum value of the series of arithmetic differences is less than 1. When M is equal to 2, that is, the duty ratio of the PWM signal achieves an improvement in accuracy of a maximum value of 4 times the fundamental frequency, the fractional duty ratio register 1312 has 4 output values of 0, 0.25, 0.5, and 0.75, respectively. It should be noted that, because there is a decimal place, the second threshold UDUTY is a dynamically changing value, the dynamic change amount is determined by the decimal place duty cycle register 1312, and the number of kinds of values of the decimal place duty cycle register 1312 is related to the second encoder 1324.
More specifically, as an example, as shown in fig. 4, the duty ratio booster 132 includes: a second cycle counter 1321, a second add 1 arbiter 1322, a second adder 1323, and a second encoder 1324, wherein:
the second adder 1323 is connected to the integer duty cycle register 1311 and the number "1", where the second adder 1323 performs an addition operation with the integer duty cycle register 1311 to obtain δ+1;
the second cycle counter 1321 is used to generate cycle periods, wherein the number of cycle periods is 2 M When M is equal to 2, the number of cycle periods is 4;
the input end of the second 1-up judger 1322 is connected with the output end of the second cycle counter 1321 and the output end of the fractional duty cycle register 1312;
the input end of the second encoder 1324 is connected to the output end of the second adder 1323, the output end of the integer duty cycle register 1311, and the output end of the second add 1 judger 1322, where the number of bits of the encoded value of the second encoder is equal to M, the encoded value of the second encoder 1324 corresponds to the output value of the fractional duty cycle register 1312 one by one, and when M is equal to 2, the encoded values of the second encoder 1324 are 00, 01, 10, 11, respectively, where 00, 01, 10, 11 are binary encoded values, the output value of the fractional duty cycle register 1312 corresponding to 00 is 0, the output value of the fractional duty cycle register 1312 corresponding to 01 is 0.25, the output value of the fractional duty cycle register 1312 corresponding to 10 is 0.5, and the output value of the fractional duty cycle register 1312 corresponding to 11 is 0.75; determining whether the second adder 1323 performs an addition operation of the integer bit of the second threshold UDUTY and the number "1" based on the encoded value of the second encoder, wherein the number of addition operations performed in each cycle period is equal to the encoded value of the second encoder 1324, wherein when the encoded value of the second encoder 1324 is 00, 00 is converted into 0 in decimal, it is explained that the integer bit of the second threshold UDUTY and the number "1" do not perform the addition operation; when the code value of the second encoder 1324 is 01, the conversion of 01 into decimal value is 1, which indicates that the integer bit of the second threshold UDUTY performs 1 addition operation with the number "1"; when the code value of the second encoder 1324 is 10, the code value of 10 is converted into decimal value of 2, which indicates that the integer bit of the second threshold UDUTY performs 2 addition operations with the number "1"; when the code value of the second encoder 1324 is 11, the code value of 11 is converted into decimal value of 3, which indicates that the integer bit of the second threshold UDUTY performs 3 addition operations with the number "1", the corresponding relationship is as follows:
| second encoder [1:0 ]] | |
Cycle 2 | Cycle 3 | Cycle 4 |
| 00 | δ | δ | δ | δ |
| 01 | δ | δ | δ | δ+1 |
| 10 | δ | δ+1 | δ | δ+1 |
| 11 | δ | δ+1 | δ+1 | δ+1 |
The corresponding time sequence relationships of 00, 01, 10 and 11 are shown in fig. 5.
As can be seen from the above correspondence, when the encoding value of the second encoder 1324 is 00, the duty ratio of the PWM signal is raised to 0; when the code value of the second encoder 1324 is 01, the frequency-raised precision of the PWM signal is 0.25d, where the period of one main clock pll_clk is the original minimum duty ratio adjustable precision d of the PWM signal, because the integer bit of the second threshold UDUTY and the number of the digits "1" are added for 1 time, the number of the cyclic periods is 4, and the digits "1" are evenly distributed in 4 cyclic periods, that is, 0.25d is obtained after the weighting operation is performed on the 0.25 and the original minimum duty ratio adjustable precision of the PWM signal, and meanwhile, 0.25 is the output value of the decimal duty ratio register 1312. It should be noted that, the addition operation of the integer bits of the second threshold UDUTY and the number "1" is not necessarily limited to the 4 th cycle, and should be flexibly set according to the specific usage scenario. Similarly, when the code value of the second encoder 1324 is 10, the accuracy of the duty ratio improvement of the PWM signal is 0.5d; when the code value of the second encoder 1324 is 11, the duty cycle of the PWM signal is raised to 0.75d, and the specific derivation process is not described here.
As shown in fig. 1, the comparing module 14 is connected to the output ends of the clock module 12, the frequency adjusting module 11 and the duty cycle adjusting module 13, and performs clock counting based on a clock reference, and generates PWM signals with improved frequency and duty cycle accuracy by comparing the clock count value with the output value of the frequency adjusting module 11 and comparing the clock count value with the output value of the duty cycle adjusting module 13, wherein the output value of the frequency adjusting module 11 is the first threshold UFREQ, and the output value of the duty cycle adjusting module 13 is the second threshold UDUTY.
Specifically, as an example, as shown in fig. 1, the comparison module 14 includes: a counter 143, a frequency comparator 141, a duty ratio comparator 142, and a PWM output control unit 144, wherein:
an input terminal of the counter 143 is connected to an output terminal of the clock module 12, wherein the counter 143 counts a master clock pll_clk provided by the clock module 12;
the frequency comparator 141 is connected to the counter 143 and the frequency adjustment module 11, wherein when the count value CNT of the counter 143 exceeds the first threshold UFREQ, the frequency comparator 141 outputs a clear signal cnt_clr, and the clear signal cnt_clr causes the counter 143 to count again;
the duty ratio comparator 142 is connected with the counter 143 and the duty ratio adjusting module 13, wherein the duty ratio comparator 142 obtains a PWM signal with improved frequency and duty ratio precision by comparing the count value CNT of the counter 143 with the output value (i.e., the second threshold UDUTY) of the duty ratio adjusting module 13, and the signal output by the duty ratio comparator 142 is pwm_c;
an input end of the PWM output control unit 144 is connected with an output end of the duty ratio comparator 142, and outputs a PWM signal, wherein the signal output by the PWM output control unit 144 is pwm_o; and Loads (RELOAD) frequency information of the PWM signal (referred to as pwm_o) to the frequency comparator 141 to synchronize the frequencies, wherein the process of frequency synchronization includes: the frequency portion of pwm_o is loaded (reloaded) to frequency comparator 141, and frequency comparator 141 further compares first threshold UFREQ, count value CNT of counter 143, and the frequency portion of pwm_o, ultimately keeping pwm_c and pwm_o consistent in frequency.
The embodiment also provides a chip for generating a PWM signal with improved frequency and duty cycle accuracy, the chip comprising: at least one of the PWM regulation circuits. It should be noted that, the chip may be set by an IP core (full name: semiconductor intellectual property core, chinese name full name: intellectual property core); IP core refers to the mature design of circuit modules with independent functions in the chip. By repeatedly using the pre-designed mature circuit module, a complex system is built, and the complex system is simplified to form a core by one key. It should be further noted that the chip configuration includes, but is not limited to, an IP core, and may be implemented by using an ASIC, where ASIC (Application Specific Integrated Circuit) is an application specific integrated circuit, and refers to an integrated circuit that is designed and manufactured according to a specific user requirement and a specific electronic system requirement. Further, as long as PWM signals with improved frequency and duty ratio accuracy can be generated, any chip configuration is applicable, and the present embodiment is not limited thereto.
In summary, the PWM adjusting circuit and the chip of the present invention include: frequency regulation module, duty cycle regulation module, clock module and comparison module, wherein: the clock module provides a clock reference for the PWM regulating circuit; the frequency adjusting module enables the frequency of the PWM signal to achieve maximum value of 2 through a first threshold value N The precision of the fundamental frequency is improved, wherein N is a natural number which is more than or equal to 1; the duty ratio adjusting module enables the duty ratio of the PWM signal to achieve a maximum value of 2 through a second threshold value M The precision of the multiple is improved, wherein M is a natural number which is more than or equal to 1; the comparison module is connected with the output ends of the clock module, the frequency adjustment module and the duty ratio adjustment module, and performs clock counting based on a clock referenceAnd generating PWM signals with improved frequency and duty ratio precision by comparing the clock count value with the output value of the frequency adjusting module and comparing the clock count value with the output value of the duty ratio adjusting module. The PWM regulating circuit and the chip of the invention ensure that the minimum adjustable precision of the frequency and the resolution of the PWM signal is not limited by the main clock frequency, and equivalently improve the precision of the PWM signal. The PWM regulating circuit and the chip have the advantages of simple structure, simple and convenient operation and wide application range. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (6)
1. A PWM regulation circuit, comprising at least: frequency regulation module, duty cycle regulation module, clock module and comparison module, wherein:
the clock module provides a clock reference for the PWM regulating circuit;
the frequency adjusting module enables the frequency of the PWM signal to achieve maximum value of 2 through a first threshold value N The precision of the fundamental frequency is improved, wherein N is a natural number which is greater than or equal to 1, the frequency adjusting module comprises a frequency register and a frequency lifter, wherein the input end of the frequency lifter is connected with the output end of the frequency register, the first threshold value is generated through the frequency lifter, the frequency register comprises an integer bit frequency register and a decimal frequency register, and the integer bit frequency register determines the integer bit of the first threshold value; the decimal frequency register determines the decimal of the first threshold, wherein the decimal frequency register hasN kinds of output values, each of which constitutes an arithmetic series, the first term of the arithmetic series being 0, the tolerance being 1/2 N And the maximum value of the series of arithmetic is less than 1, wherein the frequency booster comprises: a first cycle counter, a first 1-plus-arbiter, a first adder, and a first encoder, wherein:
the first adder is connected with the integer bit frequency register and a digital 1;
the first cycle counter is used for generating cycle periods, wherein the number of the cycle periods is 2 N ；
The input end of the first 1 adding judgment device is connected with the output end of the first cycle counter and the output end of the decimal frequency register;
the input end of the first encoder is connected with the output end of the first adder, the output end of the integer bit frequency register and the output end of the first 1-adding judger, wherein the bit number of the encoded value of the first encoder is equal to N, and the encoded value of the first encoder corresponds to the output value of the decimal bit frequency register one by one; determining, based on the encoded value of the first encoder, whether the first adder performs an addition operation of integer bits of the first threshold with a number "1", wherein the number of addition operations performed in each of the loop periods is equal to the encoded value of the first encoder;
the duty ratio adjusting module enables the duty ratio of the PWM signal to achieve a maximum value of 2 through a second threshold value M The precision of the multiple is improved, wherein M is a natural number which is greater than or equal to 1, the duty cycle adjusting module comprises a duty cycle register and a duty cycle lifter, the input end of the duty cycle lifter is connected with the output end of the duty cycle register, and the second threshold value is generated through the duty cycle lifter;
the comparison module is connected to the output ends of the clock module, the frequency adjustment module and the duty ratio adjustment module, performs clock counting based on a clock reference, and generates PWM signals with improved frequency and duty ratio precision by comparing the clock count value with the output value of the frequency adjustment module and the output value of the duty ratio adjustment module.
2. The PWM adjustment circuit according to claim 1, wherein: the duty cycle register comprises an integer duty cycle register and a decimal duty cycle register, wherein the value of the integer duty cycle register is equal to the value of the integer of the second threshold; the value of the decimal duty ratio register is equal to the value of the decimal of the second threshold, wherein the decimal duty ratio register has M output values, each output value forms an arithmetic sequence, the first term of the arithmetic sequence is 0, and the tolerance is 1/2 M And the maximum value of the series of arithmetic differences is less than 1.
3. The PWM adjustment circuit according to claim 2, wherein: the duty cycle booster includes: a second cycle counter, a second 1-adding judger, a second adder and a second encoder, wherein:
the second adder is connected with the integer bit duty ratio register and the digital 1;
the second cycle counter is used for generating cycle periods, wherein the number of the cycle periods is 2 M ；
The input end of the second 1 adding judgment device is connected with the output end of the second cycle counter and the output end of the decimal duty ratio register;
the input end of the second encoder is connected with the output end of the second adder, the output end of the integer bit duty ratio register and the output end of the second 1-adding judger, wherein the bit number of the encoded value of the second encoder is equal to M, and the encoded value of the second encoder corresponds to the output value of the decimal bit duty ratio register one by one; based on the encoded value of the second encoder, to determine whether the second adder performs an addition operation of integer bits of the second threshold with a number "1", wherein the number of addition operations performed in each of the loop periods is equal to the encoded value of the second encoder.
4. The PWM adjustment circuit according to claim 1, wherein: the clock module includes a phase locked loop.
5. The PWM adjustment circuit according to claim 1, wherein: the comparison module comprises: counter, frequency comparator, duty cycle comparator and PWM output control unit, wherein:
the input end of the counter is connected with the output end of the clock module;
the frequency comparator is connected with the counter and the frequency adjusting module, wherein when the count value of the counter exceeds the first threshold value, the frequency comparator outputs a zero clearing signal which enables the counter to count again;
the duty ratio comparator is connected with the counter and the duty ratio adjusting module, wherein the duty ratio comparator obtains PWM signals with improved frequency and duty ratio precision by comparing output values of the counter and the duty ratio adjusting module;
the input end of the PWM output control unit is connected with the output end of the duty ratio comparator, and outputs PWM signals; and loading the frequency information of the PWM signal to the frequency comparator to synchronize the frequency.
6. The utility model provides a chip for the precision that generates frequency and duty cycle is all obtained the PWM signal that promotes, its characterized in that: the chip comprises: at least one PWM regulating circuit according to any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211652902.4A CN115664397B (en) | 2022-12-22 | 2022-12-22 | PWM regulating circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211652902.4A CN115664397B (en) | 2022-12-22 | 2022-12-22 | PWM regulating circuit and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115664397A CN115664397A (en) | 2023-01-31 |
| CN115664397B true CN115664397B (en) | 2023-04-21 |
Family
ID=85022146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211652902.4A Active CN115664397B (en) | 2022-12-22 | 2022-12-22 | PWM regulating circuit and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115664397B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004364366A (en) * | 2003-06-02 | 2004-12-24 | Seiko Epson Corp | Pwm control system |
| CN102629863A (en) * | 2012-04-06 | 2012-08-08 | 开源集成电路(苏州)有限公司 | PWM (Pulse Width Modulation) circuit and LED drive circuit |
| CN107222189B (en) * | 2017-05-03 | 2020-10-23 | 中科众志信通(大连)科技有限公司 | Digital pulse width modulator |
-
2022
- 2022-12-22 CN CN202211652902.4A patent/CN115664397B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN115664397A (en) | 2023-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7459951B2 (en) | Self-calibrating digital pulse-width modulator (DPWM) | |
| US7098708B2 (en) | Low-power direct digital synthesizer with analog interpolation | |
| US20120032824A1 (en) | Successive approximation register analog-to-digital converter, and operating clock adjustment method therefor | |
| CN101908883B (en) | Programmable decimal frequency divider | |
| US20240039543A1 (en) | Apparatus for Digital Representation of Angular Difference | |
| CN108092662B (en) | Frequency synthesis device and method thereof | |
| Familier et al. | Second and third-order noise shaping digital quantizers for low phase noise and nonlinearity-induced spurious tones in fractional-$ N $ PLLs | |
| Jin et al. | Quantization Noise Suppression in Fractional-$ N $ PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider | |
| CN111404550B (en) | Analog-to-digital converter and clock generation circuit thereof | |
| US9543960B1 (en) | Multi-stage frequency dividers having duty cycle correction circuits therein | |
| US7215211B2 (en) | Prescaler for a fractional-N synthesizer | |
| CN115664397B (en) | PWM regulating circuit and chip | |
| US20110089983A1 (en) | Loop type clock adjustment circuit and test device | |
| CN113630118A (en) | Low power apparatus and method for clock doubling | |
| US8867696B2 (en) | Fractional frequency divider | |
| CN114710154B (en) | Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration | |
| US9590637B1 (en) | High-speed programmable frequency divider with 50% output duty cycle | |
| CN207896957U (en) | A kind of high-speed frequency divider | |
| CN108055040B (en) | ADC structure based on multi-phase clock and analog-to-digital conversion method thereof | |
| CN207896958U (en) | A kind of high-speed frequency divider with duty cycle adjustment function | |
| CN214675120U (en) | High-speed continuous integer frequency division circuit | |
| US9564904B2 (en) | Asynchronous high-speed programmable divider | |
| CN115664388B (en) | Triangular wave generating circuit for delta-sigma fractional frequency division phase-locked loop | |
| Akram et al. | All digital duty-cycle corrector for integrated phase noise improvement in phase-locked loop | |
| CN114337652B (en) | Frequency divider circuit and frequency synthesizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |