CN115658570B - Flash memory programming method and flash memory interface circuit - Google Patents
Flash memory programming method and flash memory interface circuit Download PDFInfo
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- CN115658570B CN115658570B CN202211599034.8A CN202211599034A CN115658570B CN 115658570 B CN115658570 B CN 115658570B CN 202211599034 A CN202211599034 A CN 202211599034A CN 115658570 B CN115658570 B CN 115658570B
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Abstract
The invention relates to the technical field of circuit design, and provides a flash memory programming method and a flash memory interface circuit, wherein the method comprises the following steps: receiving a programming request of a flash memory to acquire a data state of a programming address; if the data state of the programming address is a first set state, determining the programming state of the programming and erasing control module, wherein the programming state comprises a chip selection establishing stage, a programming stage and a chip selection maintaining stage; if the programming state is that the programming erasure control module finishes a chip selection establishing stage and is in a programming stage, acquiring target programming data; and after the programming phase is finished, directly entering the programming phase to program the target programming data. The invention directly programs the new data after the programming stage is finished, and does not need to complete the chip selection holding stage, re-enter the chip selection establishing stage and program the last time, thereby realizing continuous programming operation, saving the programming time of the flash memory and improving the efficiency of the system accessing the flash memory.
Description
Technical Field
The present invention relates to the field of circuit design technologies, and in particular, to a flash memory programming method and a flash memory interface circuit.
Background
Currently, flash memories mainly include two array structures, which are NOR flash memory (NOR flash) and NAND flash memory (NAND flash). The NOR-structured flash memory has a slower programming and erasing speed than the NAND-structured flash memory, but has a faster read access speed than the NAND-structured flash memory, and the NOR-structured flash memory can directly run a program and can operate data in units of bytes, whereas the NAND-structured flash memory cannot directly run a program in units of blocks (generally 512 bytes).
Currently, the flash programming process is less optimized, and as flash capacity increases, small capacity device programming may take several seconds, but large capacity device programming may take more than 10 seconds or even more than half a minute, one minute, etc. Taking the STM32F103ZE chip as an example, the minimum time required for programming 16 bits at a time is 40us, the maximum time is 70us, and the next programming can be performed only after one programming is finished, and the total programming of the flash memory main storage capacity of 512KB requires 10.24 seconds in the minimum time calculation, but actually the required time may be much larger than the value. Therefore, there is a need to solve the optimization problem of flash programming.
Disclosure of Invention
The invention provides a flash memory programming method and a flash memory interface circuit, which are used for solving the optimization problem of flash memory programming, and realize continuous programming operation by directly programming new data after a programming stage is finished without completing a chip selection holding stage, then re-entering a chip selection establishing stage and finally programming, thereby saving the flash memory programming time and improving the efficiency of a system accessing the flash memory.
The invention provides a flash memory programming method, which comprises the following steps:
receiving a programming request of a flash memory to acquire a data state of a programming address;
if the data state of the programming address is a first set state, determining the programming state of a programming and erasing control module, wherein the programming state comprises a chip selection establishing stage, a programming stage and a chip selection maintaining stage;
if the programming state is that the program erasing control module finishes the chip selection establishing stage and is in the programming stage, target programming data are obtained;
and directly entering the programming phase after the programming phase is finished so as to program the target programming data.
In one embodiment, the receiving a programming request of the flash memory comprises:
determining the comparison result of the programming address with the value of the address recording register and the target query address respectively;
if the comparison result is programming address hit, the address recording register is adopted to record the programming address, the value of the query counter is recalculated, and the data state pointed by the first state recording register is updated;
if the comparison result is that the programming address is not hit, replacing the value of the address recording register with the value of the programming address, clearing the value of the query counter, performing flash memory access based on the programming address, and recording the data state pointed by the target query address to a second state recording register;
the program address hit means that the program address is the same as or between one of the value of the address recording register and the target inquiry address, and the value of the inquiry counter is a set value.
In one embodiment, the method further comprises:
receiving a read access request of the flash memory to acquire a read waiting state of a flash memory read access register;
if the read waiting state is a second set state, the first instruction prefetch cache register is effective, the flash memory is accessed to read data through the read access control module, and the read data are returned to the bus;
and if the read waiting state is a third set state, the first instruction prefetch cache register and the second instruction prefetch cache register are both effective, the flash memory is accessed to read data through the read access control module, and the read data are returned to the bus.
In one embodiment, after receiving the read access request of the flash memory to obtain the read waiting status of the flash memory read access register, the method includes:
and if the read access request misses the first instruction pre-fetching cache register and the second instruction pre-fetching cache register, clearing the data of the first instruction pre-fetching cache register and the second instruction pre-fetching cache register, accessing the data of the flash memory based on the access address of the read access request, and returning the accessed data to the bus.
The present invention also provides a flash memory interface circuit, comprising:
the control register module is used for controlling the programming and erasing control module;
the programming and erasing control module is used for receiving a programming request of the flash memory to obtain a programming state of the programming and erasing control module; if the programming state is that the programming erasure control module finishes a chip selection establishing stage and is in a programming stage, acquiring target programming data; and after the programming phase is finished, directly entering the programming phase to program the target programming data.
In one embodiment, the program-erase control module comprises an address register, a query counter, a first status register, and a second status register;
the address recording register is used for recording a programming address;
the inquiry counter is used for recording the number of inquired addresses;
the first state recording register is used for recording a data state pointed by the programming address;
the second state recording register is used for recording the data state pointed by the target query address;
and the programming and erasing control module performs data query of flash memory programming based on the address recording register, the query counter, the first state recording register and the second state recording register so as to program the flash memory after the data query is finished.
In one embodiment, the flash memory interface circuit further comprises a read access control module, the read access control module is connected to the control register module, and the control register module is used for controlling the read access control module;
the read access control module is used for receiving a read access request of the flash memory so as to perform data access on the flash memory based on the read access request;
the read access control module comprises a first instruction prefetching cache register and a second instruction prefetching cache register;
the first instruction prefetch cache register and the second instruction prefetch cache register are used for acquiring instruction data in advance.
In one embodiment, the flash memory interface circuit further comprises a power-on management module, and the power-on management module is respectively connected with the control register module, the program-erase control module and the read access control module;
the power-on management module is used for controlling the power-on process of the flash memory; in the process of powering on the flash memory, the programming and erasing control module suspends programming the flash memory, and the reading access control module suspends data access to the flash memory.
In one embodiment, the control register module comprises a flash read access register, a flash status register, a flash control register, and a flash erase address register;
the flash memory read access register is connected with the read access control module and is used for controlling a read access process;
the flash memory state register is connected with the power-on management module and the programming and erasing control module and is used for determining the power-on state, the programming state and the erasing state of the flash memory;
the flash memory control register is connected with the programming and erasing control module and is used for controlling the programming operation and the erasing operation of the flash memory;
the flash memory erasing address register is connected with the programming erasing control module and used for determining the erasing address of the flash memory.
In one embodiment, the flash memory interface circuit further comprises a selector, an input end of the selector is respectively connected with the program-erase control module and the read access control module, and an output end of the selector is connected with the flash memory;
the selector is used for selecting the flash memory control signals input by the programming and erasing control module and the read access control module.
The flash memory programming method and the flash memory interface circuit provided by the invention acquire the data state of a programming address by receiving the programming request of the flash memory; if the data state of the programming address is a first set state, determining the programming state of a programming and erasing control module, wherein the programming state comprises a chip selection establishing stage, a programming stage and a chip selection maintaining stage; if the programming state is that the program erasing control module finishes the chip selection establishing stage and is in the programming stage, target programming data are obtained; and directly entering the programming phase after the programming phase is finished so as to program the target programming data. The invention directly programs the new data after the programming stage is finished, and does not need to complete the chip selection holding stage, re-enter the chip selection establishing stage and program the last time, thereby realizing continuous programming operation, saving the programming time of the flash memory and improving the efficiency of the system accessing the flash memory.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method for programming a flash memory according to the present invention;
FIG. 2 is a second flowchart illustrating a flash memory programming method according to the present invention;
FIG. 3 is a schematic flow chart of data query provided by the present invention;
FIG. 4 is a flow diagram illustrating instruction prefetching provided by the present invention;
FIG. 5 is a circuit diagram of a flash memory interface according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The flash programming method and flash interface circuit of the present invention are described below in conjunction with fig. 1-5.
Specifically, the present invention provides a flash memory programming method, including:
after receiving a programming request sent by an external system to the program-erase controller module through the bus, a data query before programming is performed, and after the data query is finished, a data state of the programming address is acquired, for example, the internal logic determines the data state of the programming address according to the state recording register.
it should be noted that both the programming operation and the timing sequence of the flash memory are complex, and in order to prevent the flash memory from being programmed incorrectly, it is necessary to check whether the data states of the programming addresses are all 1 before the flash memory is programmed, and because the flash memory is programmed from 1 to 0, if the data states pointed by the programming addresses are not all 1, the probability of errors occurring in the programming results is relatively high. The conventional programming processing mode is to read the flash data pointed by the programming address to judge whether all 1 s exist, if not, a programming error occurs, otherwise, the designated flash address is programmed, and the next programming also needs to read the data to judge and then program, and the programming is discontinuous, which causes a great amount of time loss.
After determining the data state of the programming address, judging whether the data state of the programming address is an all 1 state (namely, a first set state), if so, determining the programming state of the programming-erasing control module, namely, determining which phase (a chip selection establishing phase, a programming phase and a chip selection keeping phase) of flash memory programming the programming-erasing control module is currently in.
it should be noted that the target program data refers to new program data.
And if the programming state is that the program-erase control module finishes a chip selection establishing stage and is in a programming stage, acquiring target programming data.
The internal logic judges whether the programming state of the current programming and erasing control module finishes the chip selection establishing stage of the flash memory and is in the programming stage, if the programming state is in the programming stage, the new data is directly programmed after the programming stage is finished, and the program is not needed to be finished firstly in the chip selection maintaining stage, then re-enter the chip selection establishing stage and finally be programmed, so that the data finishes the continuous programming operation. After the programming phase is finished, the corresponding state bit of the state recording register needs to be modified to be 0, which indicates that the programming address finishes programming and is not the all 1 state.
When the internal logic enters a programming stage, the programming and erasing control module clears the busy bit and the operation ending bit of the flash memory status register of the control register module, and software can judge to carry out next programming according to the two bits, so that a next programming request is initiated through the bus. The programming and erasing control module receives a new programming request in a programming stage, sets a busy bit of a flash memory status register of the control register module and a clearing operation ending bit, caches a new programming address and data, and enters the programming stage again to program new data after the current programming stage is ended.
The system bus initiates programming requests of continuous addresses in the programming stage, continuous/uninterrupted programming can be realized for 15 times (which can be determined based on programming requirements), the time which can be saved is 14 x (chip select setup time + chip select hold time), the time depends on the timing requirements of the flash memory, and generally the chip select setup time + chip select hold time is longer than the programming time, so that the optimization of continuous programming can obtain considerable programming time reduction.
It should be noted that if the system master frequency is low or the programming time required by the flash memory is short during programming, when a certain condition is reached, due to the communication consumption of the external device or software, the system bus cannot initiate a new programming request in time at the programming stage, and this situation cannot realize continuous programming, but does not affect the normal programming function.
In one embodiment, referring to fig. 2, after the data query is finished, it is determined whether the data states of the programming addresses are all 1, and if not, the programming is incorrect; if yes, judging whether the programming erasing control module is in a programming stage, if so, modifying the state record, and enabling the corresponding state bit of the register to be in a non-all-1 state; if the state is in the chip selection establishing stage of flash memory programming, after the chip selection establishing stage is finished, the programming stage is entered, then the state record is modified, and the corresponding state bit of the register is in a non-all 1 state. And further, judging whether new programming data exist or not, if so, directly entering a programming stage, and if not, entering a chip selection holding stage.
According to the flash memory programming method provided by the embodiment of the invention, the data state of a programming address is acquired by receiving a programming request of a flash memory; if the data state of the programming address is a first set state, determining the programming state of the programming and erasing control module, wherein the programming state comprises a chip selection establishing stage, a programming stage and a chip selection maintaining stage; if the programming state is that the programming erasure control module finishes a chip selection establishing stage and is in a programming stage, acquiring target programming data; and after the programming phase is finished, directly entering the programming phase to program the target programming data. The embodiment of the invention directly programs the new data after the programming stage is finished, and does not need to complete the chip selection holding stage, re-enter the chip selection establishing stage and program at last, thereby realizing continuous programming operation, saving the programming time of the flash memory and improving the efficiency of the system accessing the flash memory.
In one embodiment, the receiving a programming request of the flash memory comprises: determining the comparison result of the programming address with the value of the address recording register and the target query address respectively; if the comparison result is programming address hit, the address recording register is adopted to record the programming address, the value of the query counter is recalculated, and the data state pointed by the first state recording register is updated; and if the comparison result is that the programming address is not hit, replacing the value of the address recording register with the value of the programming address, clearing the value of the query counter, performing flash memory access based on the programming address, and recording the data state pointed by the target query address to a second state recording register.
It should be noted that, the program address hit means that the program address is the same as or between one of the value of the address recording register and the target query address, and the value of the query counter is a set value.
The target query address is the last query address, the last query address is equal to the sum of the value of the address record register and the value of the query counter, and the maximum value of the query counter can be 15.
Referring to fig. 3, data query is required before programming the flash memory, the data query logic is located inside the program-erase control module, and the program-erase control module includes an address register, a query counter, and 2 status registers. The address recording register is used for recording a programming address; the query counter is used for recording the number of queried addresses; the first state recording register (namely, the state recording register 1) is used for recording the data state pointed by the programming address; the second status recording register (i.e. status recording register 2) is used to record the data status pointed to by the target inquiry address.
The width of the state recording register is determined according to the data size of the flash memory and the one-time programming size, if the data of the flash memory is 32 bits and the one-time programming size is 16 bits, the width of the state recording register is 2 bits, each bit records the data state of 16 bits, the state of all 1 data is set to be 1, otherwise, the state is set to be 0.
When a system bus initiates a programming request, the internal logic obtains a programming address, compares the programming address with the value of the address register and the last query address, and calls a programming address hit if the programming address is the same as or between the value of the address register and the last query address and the query counter is not 0. If the programming address hits, the value of the address record register is replaced by the value of the current programming address, and the query counter is also recalculated, wherein the calculation formula is as follows:
query counter = last query address-current programming address +1;
the state recording register points to the data state of the current programming address, and if the current programming address is consistent with the value of the address recording register, the first state recording register is unchanged; if the current programming address is consistent with the last query address, the value of the first status recording register is replaced by the value of the second status recording register, otherwise, the value of the first status recording register represents the all 1 state of the data, because the data between the address recording register and the last query address are all subjected to the all 1 check. And finally, finishing the data query phase, and enabling the internal logic to enter a programming process.
If the programming address is not hit, the value of the address recording register is replaced by the value of the current programming address, the query counter is cleared, the state recording register is initialized, the programming address is used as the current address for accessing the flash memory to access the flash memory, the flash memory is sequentially accessed from the address until the query counter is equal to 15 or the query data is not all 1, and the last query address is recorded to point to the data state to the second state recording register. And finally, finishing the data query phase, and enabling the internal logic to enter a programming process.
According to the embodiment of the invention, data query is carried out before flash memory programming so as to reduce programming errors, thereby improving the accuracy of flash memory programming.
Based on the foregoing embodiment, an embodiment of the present invention provides a flash memory access method, including: receiving a read access request of a flash memory to acquire a read waiting state of a read access register of the flash memory; if the read waiting state is a second set state, the first instruction prefetch cache register is effective, the flash memory is accessed through the read access control module to read data, and the read data is returned to the bus; and if the read waiting state is a third set state, the first instruction prefetch cache register and the second instruction prefetch cache register are both effective, the flash memory is accessed through the read access control module to read data, and the read data is returned to the bus.
And if the read access request does not hit the first instruction pre-fetching cache register and the second instruction pre-fetching cache register, clearing the data of the first instruction pre-fetching cache register and the second instruction pre-fetching cache register, accessing the data of the flash memory based on the access address of the read access request, and returning the accessed data to the bus.
It should be noted that instruction prefetching refers to fetching required data in advance, and is available when in use, the instruction prefetching logic is located in a read access control module, the read access control module includes a first instruction prefetching cache register (instruction prefetching cache register 1) and a second instruction prefetching cache register (instruction prefetching cache register 2), each instruction prefetching cache register has an address corresponding to an address of the data in the flash memory, and each instruction prefetching cache register has a corresponding status flag indicating whether the register is empty.
Referring to fig. 4, if the instruction prefetch function is not turned on, when the system bus reads the flash memory, the read access control module directly accesses the flash memory and returns data to the system bus. When the instruction prefetch enabling position of the flash memory read access register of the control register module is set, the instruction prefetch function of the read access control module is started, and the instruction prefetch cache register can be used by the internal logic.
After an external system sends a read access request of a flash memory to a read access control module through a bus, a read waiting state of a flash memory read access register of a control register module is obtained, when a read waiting state bit of the flash memory read access register is set to be in a 0 state (namely, a second set state), only a first instruction prefetch cache register is effective, and only when the system bus sends the read access request, the read access control module can access the flash memory to read data and return the data to the bus, if the address of the access request hits the address of the first instruction prefetch cache register, the access of the flash memory is not needed, and the data is directly returned to the bus, wherein the second set state means that the read waiting state is 0.
When the read wait state bit of the flash memory read access register is set to a state other than 0 (i.e., a third set state), both the first instruction prefetch cache register and the second instruction prefetch cache register are used. If the bus read access request hits in one of the 2 instruction prefetch cache registers, the data may be returned directly to the system bus without controlling the system bus to wait.
If the system bus read access request does not hit the instruction prefetch cache register, the data and the state of the 2 instruction prefetch cache registers are all cleared, the instruction prefetch logic accesses the flash memory data from the currently requested access address and returns to the bus, if the width of the flash memory data is larger than the width of the system bus data, the read data is stored in the first instruction prefetch cache register, otherwise, the access address is increased by one, and the flash memory is continuously accessed to store the data in the first instruction prefetch cache register. And when the data of the first instruction prefetch cache register is not empty, the access address continues to add an access flash memory and stores the read data in a second instruction prefetch cache register. When none of the 2 instruction prefetch cache registers are empty, instruction prefetch operation is suspended.
If one of the 2 instruction prefetch cache registers is empty of data, the instruction prefetch logic initiates an instruction prefetch process to automatically prefetch flash instructions in sequence. If the current address of the instruction prefetch cache register is greater than the address of another instruction prefetch cache register, then the current address of the instruction prefetch cache register is incremented to access the flash memory and the retrieved data is stored in the instruction prefetch cache register. If the current address of the instruction prefetch cache register is less than the address of another instruction prefetch cache register, then the current address of the other instruction prefetch cache register is incremented by one to access the flash memory and store the retrieved data in the instruction prefetch cache register.
The embodiment of the invention can acquire the instruction data in advance by setting the instruction prefetching function so as to save the data access time, thereby improving the efficiency of the system for accessing the flash memory.
Based on the foregoing embodiments, an embodiment of the present invention provides a flash memory interface circuit, including:
the control register module is used for controlling the programming and erasing control module;
the program-erase control module is used for receiving a program request of the flash memory to acquire a program state of the program-erase control module; if the programming state is that the programming and erasing control module finishes a chip selection establishing stage and is in a programming stage, acquiring target programming data; and after the programming phase is finished, directly entering the programming phase to program the target programming data.
It should be noted that the embodiments of the present invention are mainly directed to a flash memory interface circuit designed for a flash memory with a NOR structure.
Referring to fig. 5, the flash memory interface circuit includes a control register module, a program erase control module, a read access control module, a power-on management module, a selector, and a flash memory, wherein the control register module is respectively connected to the program erase control module and the read access control module in a communication manner, and an external system configures registers of the control register module through a bus to complete initialization and control of the program erase control module and the read access control module. For example, the external system sends a control command or an initialization command to the control register module through the bus, so as to complete initialization or control of the program-erase control module and the read-access control module based on the command.
The external system sends a programming request to the programming and erasing controller module through the bus, and the programming and erasing controller module programs the flash memory. According to the value of the control register module register, the programming and erasing control module starts a programming and erasing state machine, and if the programming and erasing control module is in erasing control, the state machine immediately performs erasing operation; if the operation is the programming control, the state machine waits for the programming request of the bus, and after the operation is finished, the programming and erasing control module returns the operation finished state to the control register module.
The internal logic judges whether the programming state of the current programming and erasing control module finishes the chip selection establishing stage of the flash memory and is in the programming stage, if the programming state is in the programming stage, the new data is directly programmed after the programming stage is finished, and the program is not needed to be finished firstly in the chip selection maintaining stage, then re-enter the chip selection establishing stage and finally be programmed, so that the data finishes the continuous programming operation. After the programming phase is finished, the corresponding state bit of the state recording register needs to be modified to be 0, which indicates that the programming address finishes programming and is not the all 1 state.
When the internal logic enters a programming stage, the programming and erasing control module clears the busy bit and the operation ending bit of the flash memory status register of the control register module, and software can judge to carry out next programming according to the two bits, so that a next programming request is initiated through the bus. The programming and erasing control module receives a new programming request in a programming stage, sets a busy bit of a flash memory status register of the control register module and a clearing operation ending bit, caches a new programming address and data, and enters the programming stage again to program new data after the current programming stage is ended.
The system bus initiates programming requests of continuous addresses in the programming stage, continuous/uninterrupted programming can be realized for 15 times (which can be determined based on programming requirements), the time which can be saved is 14 x (chip select setup time + chip select hold time), the time depends on the timing requirements of the flash memory, and generally the chip select setup time + chip select hold time is longer than the programming time, so that the optimization of continuous programming can obtain considerable programming time reduction.
The external system sends a read data request to the read access control module through the bus, and the read access control module performs read operation on the flash memory and returns the read data to the bus. And according to the value of the control register module register, the read access control module completes initialization configuration and waits for external read access to the flash memory through the bus.
The flash memory interface circuit also comprises a power-on management module which is respectively in communication connection with the control register module, the programming and erasing control module and the read access control module; the power-on management module is used for controlling the power-on process of the flash memory.
The power-on management module executes the power-on operation of the flash memory after receiving the power-on reset of the system, and the system cannot perform programming or read access on the flash memory through the bus during the power-on period of the flash memory.
Furthermore, in the process of controlling the flash memory to be powered on, the system can cause the system to pause when the system programs or reads the flash memory through the bus, and the system can normally access the flash memory and continue to operate after the flash memory is powered on.
Furthermore, during the programming or erasing process of the programming and erasing control module, the system cannot perform read access on the flash memory through the bus, at this time, the read access may cause system suspension, and the data can be read out from the flash memory after the programming and erasing control module finishes the operation.
Further, when the read access control module performs read access to the flash memory, the system cannot program the flash memory through the bus, at this time, the program request may cause system suspension, and if the control register module is configured with an erase function, the erase operation may be performed after the read access is completed.
Furthermore, the control register module comprises an erasing control module, a programming control module, an instruction pre-fetching control module and a read access waiting control module, and when a corresponding register bit is set, the system can carry out erasing or programming operation; when the instruction prefetching control bit is set, the flash memory interface enables the instruction prefetching function; meanwhile, a read access waiting control bit can be synchronously set, and the read access can adapt to the system main frequency with different frequencies.
Further, the instruction prefetch function is turned on by default, and the function comprises two instruction prefetch cache registers, wherein the width of the registers is the width of the data read access of the flash memory. If the read access latency period is 0 and the instruction prefetch function is on, then only one instruction prefetch cache register is active.
Further, the program-erase control module can receive new program data to buffer during the programming process and then perform continuous programming, the module setting can be continuously programmed 15 times, and after 15 times, the state is cleared and new round of programming is restarted, wherein the number of continuous programming can be determined based on the programming requirement.
The flash memory interface circuit provided by the embodiment of the invention directly programs new data after the programming stage is finished, and does not need to finish the chip selection holding stage, re-enter the chip selection establishing stage and program at last, thereby realizing continuous programming operation, saving the programming time of the flash memory and improving the efficiency of the system accessing the flash memory.
Further, the programming and erasing control module comprises an address recording register, an inquiry counter, a first state recording register and a second state recording register; the address recording register is used for recording a programming address; the inquiry counter is used for recording the number of inquired addresses; the first state recording register is used for recording the data state pointed by the programming address; the second state recording register is used for recording the data state pointed by the target query address; and the programming and erasing control module performs data query of flash memory programming based on the address recording register, the query counter, the first state recording register and the second state recording register so as to program the flash memory after the data query is finished.
It should be noted that the program-erase control module has a system main frequency and a fixed-frequency clock, the 2 clocks may be asynchronous, and an interface inside the module handles the asynchronous problem between the system bus, the control register module signal and the module inside, and the interface is driven by the system main frequency. The module is connected with the control register module, receives the data configuration of the flash memory control register and the erasing address register, and returns the state to the flash memory state register.
Both programming and erasing of the flash memory consume a lot of time, and the programming and erasing control uses a clock with fixed frequency, so that the programming time sequence and the erasing time sequence of the flash memory can be determined according to the clock, and the design is simplified.
It should be noted that, although the erase timing of a general flash memory is very time-consuming, it is simple and cannot be effectively re-optimized. The programming operation and the time sequence of the flash memory are complex, in order to prevent the error programming of the flash memory, whether the data of a programming address is all 1 or not needs to be checked before the flash memory programming is carried out, because the flash memory programming is the property of programming from 1 to 0, if the flash memory data pointed by the address is not all 1, the programming result is wrong with high probability, and the invention does not adopt the situation to carry out the programming. The conventional programming processing mode is to read the flash data pointed by the programming address to judge whether all 1 s exist, if not, a programming error occurs, otherwise, the designated flash address is programmed, and the next programming also needs to read the data to judge and then program, and the programming is discontinuous, which causes a great amount of time loss.
The flash memory read access speed is generally high and belongs to nanosecond level, while the flash memory programming generally needs to go through a chip selection establishing stage, a programming stage and a chip selection maintaining stage, the whole process is 10 microseconds less, and dozens of microseconds or even hundreds of microseconds more. The programming phase is unavoidable, but the chip select setup phase and the chip select hold phase can be optimized, based on which the present invention proposes a continuous programming scheme.
The pre-programming data query logic is inside the program-erase control module, which includes an address register, a query counter, and 2 status register. The address recording register is used for recording a programming address; the query counter is used for recording the number of queried addresses; the first state recording register (namely, the state recording register 1) is used for recording the data state pointed by the programming address; the second status recording register (i.e. status recording register 2) is used to record the data status pointed to by the target inquiry address. The target query address refers to a last query address, the last query address is equal to the sum of the value of the address record register and the value of the query counter, and the maximum value of the query counter can be 15.
The width of the state recording register is determined according to the data size of the flash memory and the one-time programming size, if the data of the flash memory is 32 bits and the one-time programming size is 16 bits, the width of the state recording register is 2 bits, each bit records the data state of 16 bits, the state of all 1 data is set to be 1, otherwise, the state is set to be 0.
When a system bus initiates a programming request, the internal logic obtains a programming address, compares the programming address with the value of the address register and the last query address, and calls a programming address hit if the programming address is the same as or between one of the value of the address register and the last query address and the query counter is not 0. If the programming address hits, the value of the address record register is replaced by the value of the current programming address, and the query counter is also recalculated, wherein the calculation formula is as follows:
query counter = last query address-current programming address +1;
the state recording register points to the data state of the current programming address, and if the current programming address is consistent with the value of the address recording register, the first state recording register is unchanged; if the current programming address is consistent with the last query address, the value of the first status recording register is replaced by the value of the second status recording register, otherwise, the value of the first status recording register represents the all 1 state of the data, because the data between the address recording register and the last query address are all subjected to the all 1 check. And finally, finishing the data query phase, and enabling the internal logic to enter a programming process.
If the programming address is not hit, the value of the address recording register is replaced by the value of the current programming address, the query counter is cleared, the state recording register is initialized, the programming address is used as the current address for accessing the flash memory to access the flash memory, the flash memory is sequentially accessed from the address until the query counter is equal to 15 or the query data is not all 1, and the last query address is recorded to point to the data state to the second state recording register. And finally, finishing the data query phase, and enabling the internal logic to enter a programming process.
According to the embodiment of the invention, data query is carried out before flash memory programming so as to reduce programming errors, thereby improving the accuracy of flash memory programming.
Furthermore, the flash memory interface circuit also comprises a read access control module, the read access control module is connected with the control register module, and the control register module is used for controlling the read access control module;
the read access control module is used for receiving a read access request of the flash memory so as to perform data access on the flash memory based on the read access request; the read access control module comprises a first instruction prefetching cache register and a second instruction prefetching cache register; the first instruction prefetch cache register and the second instruction prefetch cache register are used for pre-fetching instruction data.
It should be noted that instruction prefetching refers to fetching required data in advance, and is available when in use, the instruction prefetching logic is located in a read access control module, the read access control module includes a first instruction prefetching cache register (instruction prefetching cache register 1) and a second instruction prefetching cache register (instruction prefetching cache register 2), each instruction prefetching cache register has an address corresponding to an address of the data in the flash memory, and each instruction prefetching cache register has a corresponding status flag indicating whether the register is empty.
If the instruction prefetching function is not started, when the system bus reads and accesses the flash memory, the read access control module directly accesses the flash memory and returns data to the system bus. When the instruction prefetch enabling position of the flash memory read access register of the control register module is set, the instruction prefetch function of the read access control module is started, and the instruction prefetch cache register can be used by the internal logic.
When the read waiting status bit of the flash memory read access register of the control register module is set to 0, only the first instruction prefetch cache register is valid, and only when the system bus sends a read access request, the read access control module can access the flash memory to read data and return the data to the bus, if the access request address hits the address of the first instruction prefetch cache register, the flash memory does not need to be accessed and the data is directly returned to the bus.
When the read wait state bit of the flash memory read access register of the control register module is not set to 0, both the first instruction prefetch cache register and the second instruction prefetch cache register are used. If the bus read access request hits in one of the 2 instruction prefetch cache registers, the data may be returned directly to the system bus without controlling the system bus to wait.
If the system bus read access request does not hit the instruction prefetch cache register, the data and the state of the 2 instruction prefetch cache registers are all cleared, the instruction prefetch logic accesses the flash memory data from the currently requested access address and returns to the bus, if the data width of the flash memory is larger than the data width of the system bus, the read data is stored in the first instruction prefetch cache register, otherwise, the access address is increased by one, and the flash memory is continuously accessed to store the data in the first instruction prefetch cache register. And when the data of the first instruction prefetch cache register is not empty, the access address continues to add one to access the flash memory and stores the read data in the second instruction prefetch cache register. When none of the 2 instruction prefetch cache registers are empty, instruction prefetch operations are suspended.
If one of the 2 instruction prefetch cache registers is empty of data, the instruction prefetch logic initiates an instruction prefetch process to automatically prefetch flash instructions in sequence. If the current address of the instruction prefetch cache register is larger than the address of another instruction prefetch cache register, the current address of the instruction prefetch cache register is increased by one to access the flash memory and store the acquired data into the instruction prefetch cache register. If the current address of the instruction prefetch cache register is less than the address of another instruction prefetch cache register, then the current address of the other instruction prefetch cache register is incremented by one to access the flash memory and store the retrieved data in the instruction prefetch cache register.
The embodiment of the invention can acquire the instruction data in advance by setting the instruction prefetching function so as to save the data access time, thereby improving the efficiency of the system for accessing the flash memory.
Furthermore, the control register module comprises a flash memory read access register, a flash memory state register, a flash memory control register and a flash memory erasing address register; the flash memory read access register is connected with the read access control module and used for controlling the read access process; the flash memory state register is connected with the power-on management module and the programming and erasing control module and is used for determining the power-on state, the programming state and the erasing state of the flash memory; the flash memory control register is connected with the programming and erasing control module and is used for controlling the programming operation and the erasing operation of the flash memory; the flash memory erasing address register is connected with the programming erasing control module and used for determining the erasing address of the flash memory.
It should be noted that the control register module uses the system main frequency as an operation clock, and the control register module includes a flash memory read access register, a flash memory status register, a flash memory control register, and a flash memory erase address register.
The flash memory read access register is connected to the flash memory read access module and controls the read access process, and the register is operated by software. Wherein, the 0 th bit of the register is an instruction prefetching enabling bit, and the default setting starts the instruction prefetching function. Bits 1 to 3 are read wait state settings, and three bits can set the system read access flash memory 0 to 7 wait cycles to adapt to different system dominant frequencies.
The flash memory status register is connected to the power-on management module and the program-erase control module, the register being representative of the power-on, program and erase status of the flash memory, the register being controlled by hardware. Wherein, the 0 th bit of the register is a busy status bit of the flash memory, and when the flash memory is in a power-on process, a programming process or an erasing process, the bit is set to remind the external flash memory of being in an inoperable state. The 1 st bit is a program error bit, and programming is performed when the flash data specified by the program address is not in all 1 states, which may cause a program error because the flash programming is from 1 to 0. Bit 2 is an end of operation bit that is set by hardware if programming is complete or erasing is complete.
The flash memory control register is connected to the program-erase control module and controls the program and erase functions of the flash memory, and the register is controlled by software. The 1 st bit of the register is a main storage programming enabling bit, when the bit is set, a system is allowed to initiate a programming request through a bus, and after the bit is set, only the main storage area of the flash memory can be programmed. Bit 2 is a chunk program enable bit that when set allows the system to initiate a program request over the bus, and when set only allows the chunk region of the flash memory to be programmed. The 3 rd bit is a main storage sector erasing enabling bit, after the bit is set, the programming erasing control module erases the corresponding sector of the flash memory main storage area according to the erasing address, and after the erasing is finished, the bit is cleared by hardware. The 4 th bit is an information block sector erasing enabling bit, after the bit is set, the programming erasing control module erases the corresponding sector of the flash memory information block according to the erasing address, and after the erasing is finished, the bit is cleared by hardware. The 5 th bit is a chip erasing enable bit, after the bit is set, the programming erasing control module erases the whole flash memory main storage area, and after the erasing is finished, the bit is cleared by hardware. The 5 th bit is a reserved bit and has no effect. The 6 th bit is a programming error interrupt enabling bit, when the bit is set, if the programming is wrong, the control register module generates a programming error interrupt, and the interrupt can be cleared by clearing the programming error status bit of the flash memory status register. The 7 th bit is an operation end interrupt enable bit, and when the 7 th bit is set, if programming or erasing is finished and no programming error is generated, the control register module generates an operation end interrupt, and the operation end state bit of the flash memory state register is cleared to clear the interrupt. It should be noted that the 0 th bit to the 4 th bit of the flash control register are mutually exclusive, and only one enable bit can be set at the same time.
The erasing address register is connected to the programming and erasing control module and is controlled by software, the bit width of the register is determined according to the capacity of the flash memory, and the register determines the sector address when the sector is erased.
The embodiment of the invention realizes the functions of electrifying the flash memory, coding the flash memory, erasing the flash memory and the like by setting various registers of different types through the control register module, and improves the efficiency of the system for accessing the flash memory.
Furthermore, the flash memory interface circuit also comprises a selector, wherein the input end of the selector is respectively connected with the programming erasure control module and the read access control module, and the output end of the selector is connected with the flash memory; and the selector is used for selecting the flash memory control signals input by the programming and erasing control module and the read access control module.
It should be noted that the flash memory interface circuit includes two input end selectors, the input ends of the selectors are respectively connected with the program-erase control module and the read-access control module, and the output ends are connected with the flash memory. The selector is used for gating the flash memory control signals of the program-erase control module and the read-access control module and is connected to the flash memory. The control signals of the programming erasing control module and the reading access control module to the flash memory are independent, but the operations of the 2 modules to the flash memory are mutually exclusive, and only one module can operate the flash memory at the same time. When the programming-erasing control module works, the output of the selector is controlled by the programming-erasing control module, and when the reading access control module works, the output of the selector is controlled by the reading access control module.
The embodiment of the invention selects the flash memory control signals input by the programming erasure control module and the read access control module based on the selector by setting the selector, ensures that the flash memory is correctly controlled to execute corresponding operation, and improves the working efficiency.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of programming a flash memory, comprising:
receiving a programming request of a flash memory to acquire a data state of a programming address;
if the data state of the programming address is a first set state, determining the programming state of a programming and erasing control module, wherein the programming state comprises a chip selection establishing stage, a programming stage and a chip selection maintaining stage;
if the programming state is that the program erasing control module finishes the chip selection establishing stage and is in the programming stage, target programming data is obtained, and the target programming data refers to new programming data;
and after the programming stage is finished, directly entering the programming stage of the target programming data to program the target programming data, wherein the internal logic judges whether the programming state of the current programming and erasing control module finishes the chip selection establishing stage of the flash memory and is in the programming stage, if the programming state is in the programming stage, the new programming data is directly programmed after waiting for the end of the programming stage, and the programming is not required to be finished at the chip selection maintaining stage, enter the chip selection establishing stage again and finally be programmed.
2. The method of claim 1, wherein after receiving a programming request for the flash memory, the method comprises:
determining a comparison result between the programming address and the value of the address recording register and a target query address respectively;
if the comparison result is programming address hit, the address recording register is adopted to record the programming address, the value of the query counter is recalculated, and the data state pointed by the first state recording register is updated;
if the comparison result is that the programming address is not hit, replacing the value of the address recording register with the value of the programming address, clearing the value of the query counter, performing flash memory access based on the programming address, and recording the data state pointed by the target query address to a second state recording register;
the program address hit means that the program address is the same as or between one of the value of the address recording register and the target inquiry address, and the value of the inquiry counter is a set value.
3. The method of programming a flash memory of claim 1, further comprising:
receiving a read access request of the flash memory to acquire a read waiting state of a flash memory read access register;
if the read waiting state is a second set state, the first instruction prefetch cache register is effective, the flash memory is accessed to read data through the read access control module, and the read data is returned to the bus;
and if the read waiting state is a third set state, the first instruction prefetch cache register and the second instruction prefetch cache register are both effective, the flash memory is accessed to read data through the read access control module, and the read data are returned to the bus.
4. The method of claim 3, wherein after receiving the read access request of the flash memory to obtain the read wait state of the flash memory read access register, the method comprises:
and if the read access request misses the first instruction pre-fetching cache register and the second instruction pre-fetching cache register, clearing the data of the first instruction pre-fetching cache register and the second instruction pre-fetching cache register, accessing the data of the flash memory based on the access address of the read access request, and returning the accessed data to the bus.
5. A flash memory interface circuit applied to the flash memory programming method of any one of claims 1 to 4, comprising:
the control register module is used for controlling the programming and erasing control module;
the program-erase control module is used for receiving a program request of the flash memory to acquire a program state of the program-erase control module; if the programming state is that the programming erasure control module finishes a chip selection establishing stage and is in a programming stage, acquiring target programming data, wherein the target programming data refers to new programming data; after the programming stage is finished, directly entering the programming stage of the target programming data to program the target programming data;
the internal logic judges whether the programming state of the current programming and erasing control module finishes the chip selection establishing stage of the flash memory and is in the programming stage, if the programming state is in the programming stage, new programming data is directly programmed after the programming stage is finished, and the programming is not required to be finished first, then the chip selection maintaining stage is re-entered into the chip selection establishing stage and finally the programming is carried out.
6. The flash memory interface circuit of claim 5, wherein the program-erase control module comprises an address register, a query counter, a first status register, and a second status register;
the address recording register is used for recording a programming address;
the inquiry counter is used for recording the number of inquired addresses;
the first state recording register is used for recording the data state pointed by the programming address;
the second state recording register is used for recording the data state pointed by the target query address;
and the programming and erasing control module performs data query of flash memory programming based on the address recording register, the query counter, the first state recording register and the second state recording register so as to program the flash memory after the data query is finished.
7. The flash memory interface circuit of claim 5, further comprising a read access control module, said read access control module being coupled to said control register module, said control register module being configured to control said read access control module;
the read access control module is used for receiving a read access request of the flash memory so as to perform data access on the flash memory based on the read access request;
the read access control module comprises a first instruction prefetching cache register and a second instruction prefetching cache register;
the first instruction prefetch cache register and the second instruction prefetch cache register are used for acquiring instruction data in advance.
8. The flash memory interface circuit of claim 7, further comprising a power-on management module, said power-on management module being connected to said control register module, said program-erase control module, and said read access control module, respectively;
the power-on management module is used for controlling the power-on process of the flash memory; in the process of powering on the flash memory, the programming and erasing control module suspends programming the flash memory, and the reading access control module suspends data access to the flash memory.
9. The flash memory interface circuit of claim 8, wherein the control register module comprises a flash memory read access register, a flash memory status register, a flash memory control register, and a flash memory erase address register;
the flash memory read access register is connected with the read access control module and is used for controlling the read access process;
the flash memory state register is connected with the power-on management module and the programming and erasing control module and is used for determining the power-on state, the programming state and the erasing state of the flash memory;
the flash memory control register is connected with the programming and erasing control module and is used for controlling the programming operation and the erasing operation of the flash memory;
the flash memory erasing address register is connected with the programming erasing control module and used for determining the erasing address of the flash memory.
10. The flash memory interface circuit of claim 9, further comprising a selector having an input connected to the program erase control module and the read access control module, respectively, and an output connected to the flash memory;
the selector is used for selecting the flash memory control signals input by the programming and erasing control module and the read access control module.
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| US6567302B2 (en) * | 1998-12-29 | 2003-05-20 | Micron Technology, Inc. | Method and apparatus for programming multi-state cells in a memory device |
| US7103684B2 (en) * | 2003-12-02 | 2006-09-05 | Super Talent Electronics, Inc. | Single-chip USB controller reading power-on boot code from integrated flash memory for user storage |
| US8850103B2 (en) * | 2009-08-28 | 2014-09-30 | Microsoft Corporation | Interruptible NAND flash memory |
| US8996788B2 (en) * | 2012-02-09 | 2015-03-31 | Densbits Technologies Ltd. | Configurable flash interface |
| JP5804584B1 (en) * | 2014-10-30 | 2015-11-04 | ウィンボンド エレクトロニクス コーポレーション | Method for programming NAND flash memory |
| TWI658465B (en) * | 2018-02-02 | 2019-05-01 | 華邦電子股份有限公司 | Memory device and program/erase method thereof |
| KR102608825B1 (en) * | 2018-04-26 | 2023-12-04 | 에스케이하이닉스 주식회사 | Memory controller and operating method thereof |
| CN109710546A (en) * | 2018-12-13 | 2019-05-03 | 北京航星机器制造有限公司 | A kind of multi-bank flash-memory controller based on field programmable gate array |
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