CN115658568A

CN115658568A - FIFO device and data processing method thereof

Info

Publication number: CN115658568A
Application number: CN202211375761.6A
Authority: CN
Inventors: 赵周
Original assignee: Shenzhen Yunbao Intelligent Co ltd
Current assignee: Shenzhen Yunbao Intelligent Co ltd
Priority date: 2022-11-04
Filing date: 2022-11-04
Publication date: 2023-01-31

Abstract

The invention provides an FIFO device and a data processing method thereof, comprising a data writing port, a data reading port, an empty and full indication control module, a reading control module, a writing control module, an output register and a register file; the empty and full indication control module is used for counting the data storage quantity of the FIFO device and indicating the current empty and full state of the FIFO device; the reading control module is used for updating the pointing position of the reading pointer; the write control module is used for storing the data to be written into a register file or an output register according to a write request signal, a read request signal, the current empty and full state and the pointing position of a read pointer; the output register is connected with the read data port and used for storing the next data to be read out to be output; and the register file is used for storing other data except the data to be read out which is to be output next. The invention does not carry out combinational logic output through a multiplexer, can optimize the time sequence and reduce the congestion possibly existing in the back-end layout and wiring.

Description

FIFO device and data processing method thereof

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to an FIFO device and a data processing method thereof.

Background

A First-in First-out queue (FIFO) is a data buffer widely used in ASIC design, and has the characteristic of First-in First-out, i.e., data of the FIFO is read First, and the Output sequence is consistent with the Input sequence, and is generally used to buffer some information such as commands and data.

The conventional FIFO is generally divided into a conventional FIFO and a prefetch FIFO, and the data is prepared only in the next beat after the read enable signal of the conventional FIFO is valid, as shown in fig. 1, for the conventional prefetch FIFO, the data to be read is already prepared before the read enable signal of the prefetch FIFO is valid, that is, in the case of non-empty, the read enable signal and the read data are simultaneously valid, and the next beat is the next data. In the prior art, when reading a FIFO, a multiplexer is usually used to read data needed next time from a register file in the FIFO, but as the bit width of data increases and the depth of the FIFO increases, the delay generated by the multiplexer is larger, the congestion caused by the delay is also more serious, and the critical timing path and the layout and routing at the back end of the circuit are affected.

Disclosure of Invention

The invention aims to provide an FIFO device and a data processing method thereof, which solve the technical problems that the delay generated by a multiplexer is larger, the congestion is more serious and the key time sequence path and the back-end layout and wiring of a circuit are influenced along with the increase of the data bit width and the increase of the FIFO depth in the prior art.

In one aspect, a FIFO device is provided, comprising:

the device comprises a data writing port, a data reading port, an empty and full indication control module, a reading control module, a writing control module, an output register and a register file;

the depth of the register file is set to be N-1, the depth of the output register is set to be 1, and N is an integer greater than or equal to 2;

the write data port is used for receiving a write request signal and data to be written;

the read data port is used for receiving a read request signal;

the empty and full indication control module is used for counting the data storage quantity of the FIFO device and indicating the current empty and full state of the FIFO device; the data storage amount comprises a sum of the amounts of data stored in the register file and the output register;

the reading control module is used for updating the pointing position of the reading pointer;

the write control module is used for storing the data to be written into the register file or the output register according to the write request signal, the read request signal, the current empty and full state and the pointing position of a read pointer; updating the pointing position of the write pointer;

the output register is connected with the read data port and used for storing the next data to be read out to be output; when the read data port receives the read request signal, outputting the data to be read to the read data port;

and the register file is used for storing other data except the data to be read out to be output next.

Preferably, the empty and full indication control module is specifically configured to:

when the current data storage state of the register file is empty and the current data storage state of the output register is empty, judging that the current empty-full state of the FIFO device is empty;

when the current data storage state of the register file is full and the current data storage state of the output register is full, judging that the current empty-full state of the FIFO device is full;

and when the current data storage state of the register file is not empty and not full and the current data storage state of the output register is full, judging that the current empty and full state of the FIFO device is not empty and not full.

Preferably, the write control module is specifically configured to:

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is empty, the data to be written is stored in the output register.

Preferably, the write control module is specifically configured to:

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is full and the read data port does not receive a read request signal, the write operation of the data to be written is not performed;

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is full and the read data port receives a read request signal, the data to be read is transferred from the register file to be stored in the output register according to the data to be read which is output next time and is determined by the pointing position of the read pointer; and storing the data to be written into the corresponding position in the register file according to the pointing position of the write pointer.

Preferably, the write control module is specifically configured to:

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, the read data port does not receive the read request signal, and the number of data stored in the current FIFO device is one, the data to be written is stored in the corresponding position in the register file according to the pointing position of the write pointer;

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, and the read data port receives the read request signal, and the number of data stored in the current FIFO device is one, the data to be written is stored in the output register.

Preferably, the write control module is specifically configured to:

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, the read data port does not receive the read request signal, and the number of data stored in the current FIFO device is at least two, the data to be written is stored in the corresponding position in the register file according to the pointing position of the write pointer;

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, and the read data port receives the read request signal, and the number of data stored in the current FIFO device is at least two, the data to be written is stored in the output register.

Preferably, the method further comprises the following steps:

a clock port for receiving a clock signal;

the write enable port is used for receiving a write enable signal to activate the data write function of the FIFO device;

the read enable port is used for receiving a read enable signal to activate the data reading function of the FIFO device.

In another aspect, a data processing method of a FIFO device is provided for controlling the FIFO device, including:

the write data port receives a write request signal and data to be written;

the read data port receives a read request signal;

the empty and full indication control module counts the data storage quantity of the FIFO device and indicates the current empty and full state of the FIFO device; the data storage amount comprises a sum of the amounts of data stored in the register file and the output register;

the reading control module updates the pointing position of the reading pointer;

the write control module stores the data to be written into the register file or the output register according to the write request signal, the read request signal, the current empty and full state and the pointing position of a read pointer; updating the pointed position of the write pointer;

the output register is connected with the read data port to store the next data to be read out to be output; when the read data port receives the read request signal, outputting the data to be read to the read data port;

the register file stores data other than the data to be read out to be output next.

Preferably, the counting the data storage amount of the FIFO device and indicating the current empty-full state of the FIFO device specifically includes:

Preferably, the storing the data to be written into the register file or the output register according to the write request signal, the read request signal, the current empty-full state, and a pointing position of a read pointer specifically includes:

Preferably, the storing the data to be written into the register file or the output register according to the write request signal, the read request signal, the current empty/full status, and a pointing position of a read pointer specifically includes:

The invention has the following beneficial effects:

the FIFO device and the data processing method thereof provided by the invention separate the traditional register file into the register file and the output register, the occupied area of the FIFO device is almost the same as that of the traditional register file, and redundant registers are not used. The read data port is directly connected to the output register, and does not carry out combinational logic output through the multiplexer, namely, no redundant combinational logic exists in the middle, and the purpose of optimizing the time sequence can be achieved when the read data port is used on a key time sequence path; the write control module flexibly controls whether the data to be written should be stored in the register file or the output register according to the real-time state of the FIFO device, and simultaneously moves the stored data to be read in the register file and the output register; if the pre-fetching FIFO with large depth or large bit width is used, the effect is better, the back end is facilitated to carry out layout and wiring, and the purposes of optimizing time sequence and reducing possible congestion during layout and wiring of the back end are achieved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.

FIG. 1 is a diagram of a synchronous FIFO in the prior art.

FIG. 2 is a diagram of a FIFO device according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating a data processing method of an FIFO device according to an embodiment of the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.

Fig. 2 is a schematic diagram of an embodiment of a FIFO device according to the invention. In this embodiment, the FIFO device includes: the device comprises a write control module, a read control module, a register file, an output register, an empty and full indication control module, a write data port, a write enable port, a read data port and a read enable port; the first end of the write control module is connected with a write data port and a write enable port, the second end of the write control module is connected with the read control module, the third end of the write control module is respectively connected with the register file and the output register, and the fourth end of the write control module is connected with the empty and full indication control module; the other end of the read control module is connected with a read enabling port, the other end of the output register is connected with a read data port, and the other end of the empty and full indication control module is connected with the register file and the output register; the write data end, the write enable port, the read enable port and the read data port are arranged in a clock domain; that is, the read data port is directly connected to the output register without performing combinational logic output through the multiplexer, and meanwhile, the write control module flexibly controls whether the data to be written is stored in the register file or the output register according to the real-time state (including an empty state and a read-write request state) of the current FIFO, and also controls whether the data to be read is transferred from the register file to the output register. The data writing port and the write enabling port are used in a matched mode, writing is performed only when enabling is effective, only the data writing port cannot know when data is written, the data reading port and the read enabling port are the same in structure, and repeated description is omitted.

Further, the depth of the register file is set to be N-1, the depth of the output register is set to be 1, and N is an integer greater than or equal to 2; that is, compared to the conventional common FIFO, the data is stored uniformly in the register file, that is, the depth of the register file is set to N uniformly, where N represents the common depth of the conventional synchronous FIFO. In this embodiment, the setting of the depth of the register is divided into setting the depth of the register file to be N-1 and setting the depth of the output register to be 1, that is, the sum of the depths of the register file and the output register is the same as the depth of the register file of the existing FIFO, so that the setting is almost the same as the area of the existing FIFO, no extra register is used, the above-mentioned reduction of extra paths can be realized, the purpose of optimizing the timing sequence on the timing sequence path is achieved, and the congestion during the back-end layout and wiring is reduced.

In this embodiment, the write data port is configured to receive a write request signal and data to be written; the read data port is used for receiving a read request signal; the empty and full indication control module is used for counting the data storage quantity of the FIFO device and indicating the current empty and full state of the FIFO device; the data storage amount comprises a sum of the amounts of data stored in the register file and the output register; the reading control module is used for updating the pointing position of the reading pointer; the write control module is used for storing the data to be written into the register file or the output register according to the write request signal, the read request signal, the current empty and full state and the pointing position of a read pointer; updating the pointing position of the write pointer; the output register is connected with the read data port and used for storing the next data to be read out to be output; when the read data port receives the read request signal, outputting the data to be read to the read data port; the register file is used for storing other data except the data to be read out to be output next; a clock port for receiving a clock signal; the write enable port is used for receiving a write enable signal to activate the data write function of the FIFO device; the read enable port is used for receiving a read enable signal to activate the data reading function of the FIFO device. It can be understood that on the basis of the above structure, the functions of the read control module, the empty and full indication control module, the read pointer and the write pointer are basically not changed, such as: the read control module updates the data quantity stored by the FIFO device and updates the read pointer when a read request exists; the read pointer control points to the position of the data to be read next time in the register; write pointer control, indicating the location where the next write data is written to the register file; and the empty and full indication control module is responsible for counting the number of data stored in the current FIFO device and outputting the empty and full states of the FIFO device.

In a specific embodiment, based on the structure of the FIFO device, the write control module, the register file, the output register, and the empty/full indication control module play a main role in controlling the data write-in and read-out processes. Specifically, the empty and full indication control module is further configured to detect a current data storage state of the register file and a current data storage state of the output register; when the current data storage state of the register file is empty and the current data storage state of the output register is empty, judging that the current empty-full state of the FIFO device is empty; when the current data storage state of the register file is full and the current data storage state of the output register is full, judging that the current empty-full state of the FIFO device is full; and when the current data storage state of the register file is not empty and not full and the current data storage state of the output register is full, judging that the current empty and full state of the FIFO device is not empty and not full. It can be understood that the register file and the output register are full and empty, and there are no cases that the output register is empty and the register file is full (because there is data in the register file that will be moved to the output register when the data is read from the output register), there are only the following three cases 1 and all empty; 2. all full, 3, register file not empty, output register full (not empty not full). Therefore, whether the FIFO is empty or full can be known through the statistics of the storage quantity, the FIFO is empty if the quantity is 0, and the quantity = the FIFO depth is full (namely, the FIFO depth is full, the specific quantity refers to N-1 plus 1, and the data quantity is N)

More specifically, data read-write positions and logics in different states are specifically distinguished according to different empty-full states and different read-write requirements, as follows:

in embodiment 1, when the write data port receives a write request signal and data to be written, if the current empty/full status of the FIFO device is empty, the data to be written is stored in the output register. That is, when the write control module receives a write request signal, it identifies the current empty-full state of the FIFO device; and if the current empty and full state of the FIFO device is empty, controlling to write the write data into the output register, and keeping the write pointer control signal and the read pointer control signal unchanged. Understandably, the situation refers to that when a data writing request is sent to a data writing port, if an FIFO device is empty, namely the data quantity is 0, the writing data is written into an output register at the moment, and a writing pointer and a reading pointer are kept unchanged; .

In embodiment 2, when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is full and the read data port does not receive a read request signal, the write operation of the data to be written is not performed; when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is full and the read data port receives a read request signal, the data to be read is transferred from the register file to be stored in the output register according to the data to be read which is output next time and is determined by the pointing position of the read pointer; and storing the data to be written into the corresponding position in the register file according to the pointing position of the write pointer.

That is, when the write control module receives the write request signal, it identifies the current empty-full state of the FIFO device; if the current empty-full state of the FIFO device is full, detecting whether the reading request signal is received; when the read request signal is not received, determining that write data cannot be written; and when the read request signal is received, writing data is stored in a corresponding position in the register file according to a write pointer control signal, and read data which is determined according to the read request signal and is output next time is transferred from the register file to be stored in the output register. Understandably, the situation refers to that when the data writing request is provided to the data writing port, if the FIFO device is full and no reading request signal exists, the data cannot be written; if the FIFO device has a read request signal, the data can be normally written according to the position of the write pointer, and the next read data corresponding to the read pointer is moved from the register file into the output register. In this embodiment it is understood that the register file is full (the amount of data reaches N-1), and in practice the output register must be full when the register file is full.

Embodiment 3, when the write control module receives the write request signal, it identifies the current empty/full status of the FIFO device; if the current empty-full state of the FIFO device is not empty or not full, detecting whether the reading request signal and the data quantity stored in the current FIFO device are received or not; it will be appreciated that this time refers to the register file not being full and the output refers to the register being full, but there may be two cases in this embodiment: 1. only one data is possible in the output register, not in the register file; 2. the existence of a plurality of data may mean that the register file is not full, or the number of the register files is not full, and the conditions that the register file is full and the output register is empty do not exist.

In case 1, when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, and the read data port does not receive the read request signal, and the number of data stored in the current FIFO device is one, the data to be written is stored in a corresponding location in the register file according to the pointing location of the write pointer; when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, and the read data port receives the read request signal, and the number of data stored in the current FIFO device is one, the data to be written is stored in the output register.

That is, when the read request signal is not received and the number of data stored in the current FIFO device is only one, it is determined that write data is stored in a corresponding position in the register file according to the write pointer control signal, the read pointer control signal remains unchanged and the write pointer control signal is updated; and when the read request signal is received and the number of the data stored in the current FIFO device is only one, judging that the write data is stored in the output register, keeping the write pointer control signal unchanged and updating the read pointer control signal. Understandably, when the data writing request is provided to the data writing port, if only one piece of data exists in the FIFO device, when no reading request signal exists, the data is written into the register file according to the writing pointer, the reading pointer is kept unchanged, and meanwhile, the writing pointer is updated; if so, the data is written into the output register, the write pointer is kept unchanged, and the read pointer is updated.

In case 2, when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, and the read data port does not receive the read request signal, and the number of data stored in the current FIFO device is at least two, the data to be written is stored in the corresponding position in the register file according to the pointing position of the write pointer; when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is non-empty and non-full, and the read data port receives the read request signal, and the number of data stored in the current FIFO device is at least two, the data to be written is stored in the output register.

That is, when it is detected that the number of data stored in the current FIFO device is at least two, it is determined that write data is stored in a corresponding position in the register file according to a write pointer control signal, and the write pointer control signal is updated; when the read request signal is received and the number of data stored in the current FIFO device is multiple, the read data which is determined according to the read request signal and is output next time is transferred from the register file to the output register, and the read pointer control signal is updated. Understandably, when a data writing request is sent to a data writing port, if the FIFO device has more than 2 data but the FIFO is not full, the writing data is written into the register file according to the position pointed by the writing pointer, and the writing pointer is updated; and if the read request signal exists, the next read data corresponding to the read pointer is moved into the output register from the register file at the same time, and the read pointer is updated.

Fig. 3 is a schematic diagram of an embodiment of a data processing method for a FIFO device according to the invention. In this embodiment, the method comprises the steps of:

the write data port receives a write request signal and data to be written;

the read data port receives a read request signal;

In this embodiment, when the current data storage state of the register file is empty and the current data storage state of the output register is empty, it is determined that the current empty-full state of the FIFO device is empty;

and when the current data storage state of the register file is non-empty and non-full and the current data storage state of the output register is full, judging that the current empty-full state of the FIFO device is non-empty and non-full.

In a specific implementation, when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is empty, the data to be written is stored in the output register.

Specifically, when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is full and the read data port does not receive a read request signal, the write operation of the data to be written is not performed;

It should be noted that the method described in the above embodiment corresponds to the FIFO device described in the above embodiment, and therefore, portions of the method described in the above embodiment which are not described in detail can be obtained by referring to the contents of the FIFO device described in the above embodiment, and are not described herein again.

In summary, the embodiment of the invention has the following beneficial effects:

the FIFO device and the data processing method thereof provided by the invention separate the mode of uniformly storing data in the traditional register file into the register file and the output register, the area size is almost the same, and redundant registers are not used. The read data port is directly connected to the output register without performing combinational logic output through a multiplexer, namely, no redundant combinational logic exists in the middle, and the purpose of optimizing the time sequence can be achieved when the read data port is used on a key time sequence path; the write control module flexibly controls write input to be stored in the register file or the output register according to the real-time state of the FIFO, and simultaneously moves data in the register file and the output register.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.

Claims

1. A FIFO apparatus, comprising:

the read data port is used for receiving a read request signal;

2. The FIFO device of claim 1, wherein the empty-full indication control module is specifically configured to:

3. The FIFO device of claim 2, wherein the write control module is specifically configured to:

4. The FIFO device of claim 2, wherein the write control module is specifically configured to:

5. The FIFO device of claim 2, wherein the write control module is specifically configured to:

6. The FIFO device of claim 2, wherein the write control module is specifically configured to:

7. The FIFO device of claim 1, further comprising:

a clock port for receiving a clock signal;

8. A data processing method of a FIFO device according to any one of claims 1 to 7, comprising the steps of:

the write data port receives a write request signal and data to be written;

the read data port receives a read request signal;

the read control module updates the pointing position of the read pointer;

9. The method of claim 8, wherein said counting the number of data stores of the FIFO device and indicating a current empty-full status of the FIFO device comprises:

10. The method as claimed in claim 9, wherein said storing said data to be written into said register file or said output register according to said write request signal, said read request signal, said current empty-full status, and a position pointed to by a read pointer comprises:

11. The method as claimed in claim 9, wherein said storing said data to be written into said register file or said output register according to said write request signal, said read request signal, said current empty-full status, and a position pointed to by a read pointer comprises:

when the write data port receives a write request signal and data to be written, if the current empty-full state of the FIFO device is full and the read data port receives a read request signal, the data to be read is stored in the output register from the register file according to the data to be read which is output next time and is determined by the pointing position of the read pointer; and storing the data to be written into the corresponding position in the register file according to the pointing position of the write pointer.

12. The method as claimed in claim 9, wherein said storing said data to be written into said register file or said output register according to said write request signal, said read request signal, said current empty-full status, and a position pointed to by a read pointer comprises:

13. The method as claimed in claim 9, wherein said storing the data to be written into the register file or the output register according to the write request signal, the read request signal, the current empty and full status, and a pointing position of a read pointer comprises: