CN115658559B - Memory address mapping method and device and chip - Google Patents

Memory address mapping method and device and chip Download PDF

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CN115658559B
CN115658559B CN202211652939.7A CN202211652939A CN115658559B CN 115658559 B CN115658559 B CN 115658559B CN 202211652939 A CN202211652939 A CN 202211652939A CN 115658559 B CN115658559 B CN 115658559B
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descriptor
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intervals
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CN115658559A (en
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Moore Threads Technology Co Ltd
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Abstract

The invention relates to the technical field of memory management. The invention provides a memory address mapping method, which comprises the following steps: receiving a first address of a first address space, wherein the first address space is divided into a plurality of address intervals, and the size of each address interval is the same and is a positive integer power of 2; acquiring the number m of devices using a first address space, and generating a serial number of each device, wherein m is greater than or equal to 1 and less than or equal to the number of the plurality of address intervals; determining a descriptor uniquely corresponding to the first address from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals; the first address is mapped to a second address of a second address space based on the uniquely corresponding descriptor. In addition, the invention also relates to a mapping device and a chip comprising the mapping device. The invention can be better suitable for coarse-grained application scenes and can realize the spatial isolation of a plurality of devices on hardware addresses.

Description

Memory address mapping method and device and chip
Technical Field
The present disclosure relates to the field of memory management technologies, and in particular, to a memory address mapping method based on a custom descriptor, a device to which the memory address mapping method is applied, and a chip including the device.
Background
Currently, in the management of memory by an operating system, it is usually necessary to map the physical address of the local memory of a device to a virtual address. The granularity of the existing Memory Management Unit (MMU) for translating the address space of the memory is as accurate as 4K/16K/64K, a large number of page table entries are needed to describe the whole address space, so that a page table comprising the page table entries cannot be completely stored locally due to being too large, and in order to improve the translation speed in an application, a cache (cache) is needed to cache the page table comprising the large number of page table entries. However, when the address space frequently and greatly shifts, the page table in the cache may fail to hit, and the corresponding page table needs to be reloaded, resulting in a large system overhead. Furthermore, in many address mapping application scenarios, the granularity of the address space for translation may be much larger than 4K/16K/64K, for example, in some application scenarios, the granularity of the address space for translation may be as high as hundreds of megabytes. In this case, if the existing MMU is used, since the granularity of the fixed 4K/16K/64K cannot be adjusted according to the actual needs of the application scenario, the address space with a coarse granularity can only be described by using a method including multiple levels and multiple page table entries, which leads to frequent reloading of the page table and thus has a great negative effect on the cost and efficiency of the system.
Therefore, a flexible, simple, adaptive and low-cost method is needed to implement mapping or conversion of memory addresses in various application scenarios.
Disclosure of Invention
According to a first aspect of the present disclosure, there is provided a memory address mapping method, including: receiving a first address of a first address space, wherein the first address space is divided into a plurality of address intervals, and the size of each address interval is the same and is a positive integer power of 2; acquiring the number m of devices using the first address space, and generating a serial number of each device, wherein m is an integer greater than or equal to 1 and less than or equal to the number of the plurality of address intervals; determining a descriptor uniquely corresponding to the first address from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, wherein each descriptor includes: indicating information indicating the accessibility of the corresponding address interval, indicating information indicating the size of an effective address interval in the corresponding address interval, wherein the effective address interval can be subjected to address mapping, and a target base address; mapping the first address to a second address of a second address space based on the uniquely corresponding descriptor.
According to some exemplary embodiments of the present disclosure, the plurality of address intervals is 2 n An address interval, n is an integer greater than or equal to 0, m is greater than or equal to 1 and less than or equal to 2 n And the m sets of descriptors are m x 2 n A descriptor.
According to some exemplary embodiments of the present disclosure, the descriptor includes a mode control part and a target address information part including the target base address, and the mode control part includes: a valid bit indicating accessibility of the corresponding address interval, a secondary descriptor information bit indicating whether a secondary descriptor is included, a valid address interval information bit indicating a size of a valid address interval in the corresponding address interval where address mapping is possible.
According to some exemplary embodiments of the present disclosure, the number m of the devices is 1, and n is an integer greater than 0, wherein the determining, from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, a descriptor uniquely corresponding to the first address comprises: determining a descriptor uniquely corresponding to the first address based on a value of an index information bit in the first address, wherein the index information bit is composed of predetermined n bits in the first address.
According to some exemplary embodiments of the present disclosure, the number m of the devices is 1, and n is equal to 0, wherein the determining, from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, a descriptor uniquely corresponding to the first address includes: a descriptor corresponding to a unique address interval is determined as the descriptor uniquely corresponding to the first address.
According to some of the example embodiments of the present disclosure, the mapping the first address to a second address of a second address space based on the uniquely corresponding descriptor comprises: acquiring a first address offset item from the first address; obtaining the target base address from a target address information portion of the uniquely corresponding descriptor; determining, based on a value of a valid bit of the unique corresponding descriptor, that an address range to which the unique corresponding descriptor corresponds is accessible; determining that the first address is within an effective address interval of an address interval corresponding to the unique corresponding descriptor based on the first address offset entry and a value of an effective address interval information bit of the unique corresponding descriptor; generating the second address based on the first address offset entry and a target base address of the unique corresponding descriptor.
According to some exemplary embodiments of the disclosure, the first address is a 32-bit address and the second address is a 40-bit address, and wherein the obtaining a first address offset entry from the first address comprises: and taking the value of the 0 th bit to the 31-nth bit of the first address as the first address offset item, wherein n is an integer which is greater than or equal to 0 and less than or equal to 16.
According to some exemplary embodiments of the present disclosure, the descriptor is 32 bits, the 0 th bit to the 7 th bit of the descriptor are the mode control part, the 8 th bit to the 31 th bit of the descriptor are the target address information part, and wherein the obtaining the target base address from the target address information part of the uniquely corresponding descriptor comprises: determining a value of bits 24-n through 31 in the uniquely corresponding descriptor as the target base address.
According to some of the example embodiments of this disclosure, the generating the second address based on the first address offset term and the target base address of the unique corresponding descriptor comprises: taking the first address offset entry as bits 0 through 31-n of the second address; the target base address is taken as bits 32-n through 39 of the second address.
According to some exemplary embodiments of the present disclosure, the number m of the devices is greater than 1, and n is greater than 0, wherein the determining, from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, a descriptor uniquely corresponding to the first address comprises: determining a corresponding descriptor group from the m descriptor groups based on the serial number of the device; determining the uniquely corresponding descriptor from the corresponding descriptor set based on a value of an index information bit in the first address, wherein the index information bit is composed of predetermined n bits in the first address.
According to some example embodiments of the present disclosure, the device is a virtual machine.
According to some exemplary embodiments of the disclosure, in case the number m of the devices is larger than 1, the mapping the first address to a second address of a second address space based on the uniquely corresponding descriptor comprises: acquiring a first address offset item from the first address; obtaining the target base address from a target address information portion of the uniquely corresponding descriptor; determining, based on a value of a valid bit of the unique corresponding descriptor, that an address range to which the unique corresponding descriptor corresponds is accessible; determining that the first address is within an effective address interval of an address interval corresponding to the unique corresponding descriptor based on the first address offset entry and a value of an effective address interval information bit of the unique corresponding descriptor; generating the second address based on the first address offset term and a target base address of the unique corresponding descriptor.
According to some exemplary embodiments of the disclosure, the first address is a 35-bit address and the second address is a 40-bit address, and wherein the obtaining a first address offset entry from the first address comprises: taking the value of the 0 th bit to the 34 th-nth bit of the first address as the first address offset entry, wherein n is an integer greater than or equal to 0 and less than or equal to 19.
According to some exemplary embodiments of the present disclosure, the descriptor is 32 bits, the 0 th bit to the 7 th bit of the descriptor are the mode control part, the 8 th bit to the 31 th bit of the descriptor are the target address information part, and wherein the obtaining the target base address from the target address information part of the uniquely corresponding descriptor comprises: determining a value of bits 27-n through 31 of the uniquely corresponding descriptor as the target base address.
According to some of the example embodiments of the present disclosure, the generating the second address based on the first address offset entry and the target base address of the unique corresponding descriptor comprises: taking the first address offset entry as bits 0 through 34-n of the second address; the target base address is taken as bits 35-n through 39 of the second address.
According to some exemplary embodiments of the present disclosure, the memory address mapping method further includes: when the secondary descriptor information bit indicates the presence of a secondary descriptor, determining a storage address of the secondary descriptor from the target address information portion.
According to some exemplary embodiments of the present disclosure, the memory address mapping method further includes: when the descriptor uniquely corresponding to the first address indicates that the corresponding address interval is inaccessible or indicates that the first address is located outside an effective address interval in the corresponding address interval, prompting that the access to the first address is illegal.
According to a second aspect of the present disclosure, there is provided a memory address mapping apparatus, comprising: a first address receiving module configured to: receiving a first address of a first address space, wherein the first address space is divided into a plurality of address intervals, and the size of each address interval is the same and is a positive integer power of 2; a device number and serial number acquisition module configured to: acquiring the number m of devices using the first address space, and generating a serial number of each device, wherein m is an integer greater than or equal to 1 and less than or equal to the number of the plurality of address intervals; a descriptor determination module configured to: determining a descriptor uniquely corresponding to the first address from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, wherein each descriptor includes: indicating information indicating the accessibility of the corresponding address interval, indicating information indicating the size of an effective address interval in the corresponding address interval, wherein the effective address interval can be subjected to address mapping, and a target base address; an address mapping module configured to: mapping the first address to a second address of a second address space based on the unique corresponding descriptor.
According to some exemplary embodiments of the present disclosure, in the memory address mapping device, the plurality of address intervals are 2 n An address interval, n is an integer greater than or equal to 0, m is greater than or equal to 1 and less than or equal to 2 n And the m sets of descriptors are m x 2 n A descriptor.
According to some exemplary embodiments of the present disclosure, the descriptor determining module includes m × 2 n A register, wherein each register stores the m × 2 n One of the descriptors.
According to a third aspect of the present disclosure, there is provided a chip including the memory address mapping apparatus according to the third aspect of the present disclosure and its various exemplary embodiments.
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So that the manner in which the above recited features, characteristics and advantages of the present disclosure can be understood in detail, a more particular description of embodiments of the present disclosure, briefly summarized above, may be had by reference to the appended drawings, in which; in the drawings:
FIG. 1 schematically illustrates, in flow diagram form, a method of memory address mapping in accordance with some demonstrative embodiments of the disclosure;
fig. 2 schematically illustrates a format of a descriptor according to some exemplary embodiments of the present disclosure;
fig. 3a and 3b respectively illustrate further details of the step of determining a unique corresponding descriptor in the memory address mapping method illustrated in fig. 1, according to some exemplary embodiments of the present disclosure;
FIG. 4 illustrates further details of the step of generating a second address in the memory address mapping method of FIG. 1, in accordance with some demonstrative embodiments of the disclosure;
FIGS. 5a and 5b schematically illustrate an application scenario for address expansion bits, according to some exemplary embodiments of the present disclosure;
FIG. 6 illustrates further details of the step of determining a unique corresponding descriptor in the memory address mapping method illustrated in FIG. 1, according to further exemplary embodiments of the present disclosure;
FIG. 7 schematically illustrates an application scenario for checking and transforming addresses accessed by a virtual machine, in accordance with some demonstrative embodiments of the disclosure;
FIG. 8 schematically illustrates, in block diagram form, the structure of a memory address mapping apparatus in accordance with some demonstrative embodiments of the present disclosure; and
fig. 9 schematically illustrates, in block diagram form, a structure of a chip in accordance with some exemplary embodiments of the present disclosure.
It is to be understood that the matter shown in the figures is merely schematic and, thus, not necessarily drawn to scale. Further, throughout the drawings, the same or similar features are indicated by the same or similar reference numerals.
Detailed Description
The following description provides specific details of various exemplary embodiments of the present disclosure so that those skilled in the art can fully understand and implement the technical solutions described in accordance with various exemplary embodiments of the present disclosure.
First, some terms involved in exemplary embodiments of the present disclosure are explained so that those skilled in the art can better understand the present invention.
Address space: in the present disclosure, the term "address space" refers to the total number of memory cells that an address having a particular number of bits can locate. For example, an address with a 32-bit number can be located 2 in total 32 Each memory unit has a corresponding address space of 4G; addresses with a bit number of 40 bits can be located with a total of 2 40 And thus the corresponding address space is 1T.
Virtual machine: in this disclosure, the term "virtual machine" refers to a computer system having hardware system functionality, emulated by software, running in a completely isolated environment. When creating a virtual machine, a part of the physical memory of the device needs to be used as the memory of the virtual machine. Thus, when multiple virtual machines exist, different portions of the physical memory of a device may be allocated to different virtual machines, such that each virtual machine can only legitimately access device memory allocated to itself. Also, each virtual machine is unaware of the existence of the other virtual machines.
Referring to fig. 1, a memory address mapping method according to some exemplary embodiments of the present disclosure is schematically illustrated in a flowchart. As shown in fig. 1, the memory address mapping method 100 includes steps 110, 120, 130, and 140.
In step 110, a first address of a first address space is received, wherein the first address space is divided into a plurality of address intervals, and each address interval has the same size and is a positive integer power of 2. It should be understood that in the memory address mapping method 100, the address space (i.e., the first address space) of the local memory can be divided into the required granularities (i.e., address blocks with a certain size) according to actual needs, rather than being continuously accumulated to the required granularities based on the fixed granularity of 4K/16K/64K as in the prior art. Therefore, the memory address mapping method 100 according to the present disclosure can be flexibly applied to various application scenarios requiring address spaces of different granularities, and is particularly suitable for coarse-grained application scenarios with granularity up to hundreds of megabytes. It should be appreciated that in some applications, only a portion of the plurality of address intervals of the first address space may be accessible, such as in the case of an application where the address space is locally accessible. In this case, the accessibility of each of the plurality of address intervals may be described by a descriptor such that only those address intervals that are allowed to be accessed can be accessed, and those address intervals that are not allowed to be accessed cannot be accessed. As a non-limiting example, a respective valid bit may be set in a descriptor corresponding to an address interval, whereby the address interval can be accessed if the value of the valid bit indicates that the corresponding address interval is valid, and the address interval cannot be accessed if the value of the valid bit indicates that the corresponding address interval is invalid.
In step 120, the number m of devices using the first address space is obtained and a serial number of each device is generated, where m is an integer greater than or equal to 1 and less than or equal to the number of the plurality of address intervals. In this step, the information about the devices using the first address space, i.e. the number and the serial number of the devices, may be obtained in any suitable way. The number of devices m is related to the number of sets of descriptors, and the serial number of a device may be combined with other parameters (e.g., the value of the index information bit) to determine the descriptor that uniquely corresponds to the first address. It should be appreciated that step 120 actually describes that the memory address mapping method 100 can be used in a variety of different application scenarios, for example, an application scenario in which address expansion is performed for one device, or an application scenario in which addresses accessed by a plurality of virtual machines are checked and transformed when the first address space is used by the virtual machines.
At step 130, a descriptor uniquely corresponding to the first address is determined from m groups and each group includes descriptors in one-to-one correspondence with the plurality of address intervals, wherein each descriptor includes: the address mapping method comprises indication information indicating accessibility of corresponding address intervals, indication information indicating effective address interval size capable of address mapping in the corresponding address intervals, and target base addresses. It can be seen that the total number of descriptors is equal to the product of the number of address intervals and the number of devices using the first address space, and one descriptor set may correspond to one device, and the descriptors in the descriptor set correspond to the address intervals one to one. The descriptors thus establish a link between the devices using the first address space and the address intervals of the first address space. Furthermore, the descriptor itself includes description information for the corresponding address interval (i.e., indication information indicating accessibility of the address interval and indication information indicating a valid address interval size), and includes address information for address mapping (i.e., a target base address). It should be understood that the range of valid address intervals should be less than or equal to the range of corresponding address intervals, as will be described in detail below. Therefore, based on the information included in the descriptor, the allocation use of each device with respect to each address section of the first address space can be obtained. It should be understood that in the memory address mapping method 100 according to the present disclosure, descriptors that have been generated as needed may be received from another device or system and stored in a corresponding storage (as a non-limiting example, in a register (e.g., in a chip register)) to provide a corresponding software interface, associated transformations, and address checking logic, among others. However, in other exemplary embodiments, the memory address mapping method may also generate the required descriptors as needed. Step 130 determines a descriptor uniquely corresponding to the first address from m groups, each group including descriptors in one-to-one correspondence with the plurality of address intervals, thereby enabling, in the memory address mapping method 100 according to the present disclosure, for each first address in the first address space, a uniquely corresponding descriptor to be determined so as to enable address mapping according to a target base address included in the descriptor. It should be understood that there are a number of methods of determining uniquely corresponding descriptors, depending on the number of address intervals and the number of devices using the first address space, which will be described in detail below.
According to some exemplary embodiments of the present disclosure, in step 110, the first address space is divided into 2 n An address interval, n being an integer greater than or equal to 0; in step 120, m is greater than or equal to 1 and less than or equal to 2 n An integer of (d); and in step 130, the m sets of descriptors are mx 2 n A descriptor. It should be understood that the division into 2 with respect to the first address space is n An address interval essentially because n bits of a first address in a first address space are used as index information bits such that the first address space is divided into 2 n An address interval. It can be seen therefrom that 2 n The parameter n in an address interval is actually the number of bits in the first address that are used as index information bits.
According to some example embodiments of the present disclosure, the descriptor may include a mode control part and a target address information part, and the target address information part may include a target base address. The mode control part may include: a valid bit indicating accessibility of the corresponding address interval, a secondary descriptor information bit indicating whether a secondary descriptor is included, and a valid address interval information bit indicating a size of a valid address interval in which address mapping is possible among the corresponding address intervals. Referring to fig. 2, a format of a descriptor according to the present disclosure is schematically illustrated. The descriptor is applicable to various exemplary embodiments according to the present disclosure. As shown in fig. 2, the descriptor may have a general length of, for example, a chip register, that is, 32 bits, of which 0 th bit to 7 th bit are a mode control part and 8 th bit to 31 th bit are a target address information part including a target base address. The descriptor defines a basic mode of current address mapping/translation in the mode control portion, including: the 0 th bit is a valid bit V indicating the accessibility of the corresponding address interval, which indicates that the current descriptor is invalid or the currently described address interval is inaccessible if 0, and indicates that the current descriptor is valid or the currently described address interval is accessible if 1; bit 1 is a secondary descriptor information bit I indicating whether a secondary descriptor is included, which indicates that the descriptor has only the current level if it is 0 and also has the next level description if it is 1, so as to enable finer-grained address mapping; the 2 nd bit is a reserved bit R and is used for adding more control information in some application scenes; the 3 rd bit to the 7 th bit are effective address interval information bits Size for indicating the Size of an effective address interval in the address interval corresponding to the descriptor, where address mapping can be performed.
It should be understood that the various values described above with respect to the significand V and the secondary descriptor info bit I in the descriptor are exemplary and not limiting. For example, in other exemplary embodiments, a valid bit V of 1 may indicate that the current descriptor is invalid or the currently described address range is not accessible, and a valid bit V of 0 may indicate that the current descriptor is valid or the currently described address range is accessible; similarly, the secondary descriptor information bit I is 1, which may indicate that there is only one current level of the descriptor, and when it is 0, which may indicate that there is a next level of the descriptor, so as to enable finer-grained address mapping. Therefore, the present disclosure does not set any limit to the specific manner in which the significant bit V and the secondary descriptor information bit I take on values. Further, the descriptor's effective address interval information bit Size includes its 3 rd bit to 7 th bit, whereby a total of 5 bits are provided to indicate the Size of the effective address interval in the address interval (i.e., various values ranging from 0x00 to 0x19 using 5 bits). The specific Size of the effective address interval indicated by the value of the effective address interval information bit Size depends on the granularity of division of the address space required in the current application scenario (in this regard, described in further detail below), so the Size of the effective address interval should be smaller than or equal to the Size of the corresponding address interval. Therefore, for the first address space, the first address of each address interval is combined with the effective address interval defined in the descriptor corresponding to the address interval, on one hand, smaller address space granularity can be defined relative to the size of the address interval, and on the other hand, effective address intervals (i.e. effective granularity) with different sizes can be defined for different address intervals. Therefore, through setting the effective address interval, more flexible and diversified mapping operation of the memory address can be realized.
It should be understood that the mode control portion of the descriptor shown in fig. 2 is merely exemplary, information bits in the descriptor may be additionally added as needed, and the number of bits used for the effective address interval information bit Size may also be varied, for example, there may be a greater or lesser number of bits. The present disclosure is not intended to be limited in any way in these respects.
With continued reference to fig. 2, bits 8 through 31 are the target address information portion of the descriptor, which includes the target Base address Dst _ Base for address mapping/translation. According to the present disclosure, the logic that performs address mapping/conversion may start from the highest order of the target address information part, and therefore, based on the descriptor shown in fig. 2, at most 24-order address information can be added at the time of address mapping/conversion (that is, the target Base address Dst _ Base may be 24-order at most). Of course, it should be understood that if the current application scenario does not require the addition of 24 bits of address information, the unused bits in the target address information portion will be set to the Reserved bit Reserved. Further, it should also be understood that if the secondary descriptor information bit I of the descriptor (e.g., bit 1 of the descriptor shown in FIG. 2) indicates that a secondary descriptor is also included, then the destination address information portion of the descriptor may also include an address indicating the storage location of the secondary descriptor.
With continued reference to FIG. 1, at step 140, the first address is mapped to a second address of a second address space based on the unique corresponding descriptor. As already described above, the mapping address information, i.e. the target base address, available for the first address is included in the uniquely corresponding descriptor. A second address corresponding to a first address can be generated using an address offset entry in the first address and a target base address in a uniquely corresponding descriptor, thereby mapping the first address in the first address space to the second address in the second address space. It should be understood that the first address space and the second address space involved in the memory address mapping method 100 according to the present disclosure may be any suitable address space of a memory. By way of non-limiting example, the first address space may be a local physical address space of a memory of any suitable device, and the second address space may be a global address space addressable by a chip bus. The present disclosure does not impose any limitations on the specific types of first address spaces and second address spaces.
It should also be understood that in the memory address mapping method 100 shown in fig. 1, the order of steps 110 to 140 is merely exemplary, which does not mean that steps 110 to 140 must be executed in the order shown in fig. 1. Indeed, steps 110 to 140 can be performed in any suitable order different from that shown in fig. 1, e.g. in parallel, or in reverse order. The present disclosure does not set any limit to the order of steps 110 to 140 in the memory address mapping method 100.
As can be seen from the above description, on one hand, the memory address mapping method 100 according to the present disclosure can divide the address space of the memory into the required granularity according to the actual needs, and therefore, can be flexibly applied to various application scenarios requiring address spaces of different granularities, and is particularly suitable for coarse-granularity application scenarios with granularity up to hundreds of megabytes; on the other hand, the memory address mapping method 100 according to the present disclosure configures different descriptors corresponding to each address range to different devices using the same address space, where accessibility and effective address ranges for each address range may be defined differently, thereby not only enabling more flexible and diversified mapping operations for memory addresses, but also enabling spatial isolation of each device on hardware addresses, which is particularly useful in applications of virtual machines. Therefore, the memory address mapping method 100 according to the present disclosure provides a flexible, simple, adaptive and low-cost memory address mapping method, which can be used for mapping or converting memory addresses in various application scenarios.
Referring to fig. 3a and 3b, further details of steps for determining uniquely corresponding descriptors in the memory address mapping method of fig. 1 are shown, respectively, according to some exemplary embodiments of the present disclosure.
As shown in fig. 3a, in the case that the number m of devices is 1 and the parameter n is an integer greater than 0, step 130 in the memory address mapping method 100 shown in fig. 1 can be further defined as step 130a: determining a descriptor uniquely corresponding to the first address based on a value of an index information bit in the first address, wherein the index information bit is composed of predetermined n bits in the first address. The number of devices m being 1 means that there is only one set of descriptors in total for describing the respective address intervals in the first address space, and therefore there is no need to determine one descriptor set from a plurality of descriptor sets. The parameter n is an integer greater than 0, which means that the first address space is not divided into only one address interval, and therefore, the index information bits are necessarily included in the first address of the first address space. Since each descriptor has a one-to-one correspondence with each address space, and each value of the index information bit in the first address also has a one-to-one correspondence with each address space, in this case, the uniquely corresponding descriptor can be determined based on the value of the index information bit in the first address. In addition, the index information bit may be formed by n bits from the highest bit in the first address, or may also be formed by n bits from the lowest bit in the first address, and even in some embodiments, the index information bit may be formed by n bits at a preset position in the first address, as long as the n bits forming the index information bit can be distinguished from other bits in the first address, which is not limited in this disclosure. It should be understood that the value of the index information bit actually defines the first address and 2 in the first address space n The correspondence between the address intervals, in other words the value of the index information bit, actually determines to which address interval the first address belongs. Thus, the value of the index information bit may be used to determine (or in conjunction with other parameters) a descriptor that uniquely corresponds to the first address.
As shown in fig. 3b, in the case that the number m of devices is 1 and the parameter n is equal to 0, step 130 in the memory address mapping method 100 shown in fig. 1 can be further defined as step 130b: determining a descriptor corresponding to a unique address interval as a descriptor uniquely corresponding to the first address. The number of devices m being 1 means that there is only one set of descriptors in total for describing the respective address intervals in the first address space, so there is no need to first determine a descriptor set from a plurality of descriptor sets. The parameter n equal to 0 means that the first address space is divided into only one address interval (that is, the entire first address space is one address interval), and 0 bits in the first address are taken as index information bits (that is, the index information bits are not included in the first address of the first address space). In this case, the first address space itself is a unique one address interval, and there is only one descriptor in total for describing the address interval, and therefore, the one descriptor can be determined as a descriptor uniquely corresponding to the first address. It should also be understood that in this case, since the index information bits are not included in the first addresses of the first address space, the first addresses are all used as address offset entries to generate corresponding second addresses along with the target base address of the descriptor.
As can be seen from the above description, the methods of determining uniquely corresponding descriptors illustrated in fig. 3a and 3b are applicable to application scenarios where only one device uses the first address space. In this case, the first address space may be divided into one or more address intervals, and in each address interval, a different effective address interval may also be set as needed to achieve flexible configuration for smaller granularity requirements while meeting coarse granularity requirements. It should also be understood that throughout this disclosure, the parameter n is simply the division of the first address space into 2 n The parameter n and the parameter m in each address interval are the number of devices using the first address space, and therefore, details of the parameters n and m will not be described below.
Referring to fig. 4, further details of the step of generating the second address in the memory address mapping method shown in fig. 1 are shown, according to some exemplary embodiments of the present disclosure. As shown in FIG. 4, step 140 of the memory address mapping method 100 may include steps 140-1, 140-2, 140-3, 140-4, and 140-5.
At step 140-1, obtaining a first address offset entry from the first address;
at step 140-2, obtaining the target base address from the target address information portion of the unique corresponding descriptor;
at step 140-3, determining that an address range to which the unique corresponding descriptor corresponds is accessible based on a value of a valid bit of the unique corresponding descriptor;
at step 140-4, determining that the first address is within the effective address range of the address range corresponding to the unique corresponding descriptor based on the first address offset entry and the value of the effective address range information bit of the unique corresponding descriptor;
at step 140-5, the second address is generated based on the first address offset term and the target base address of the unique corresponding descriptor.
It should be understood that, in the present disclosure, the value of all bits of the first address except the index information bit formed by n bits will be used as the first address offset entry. In some exemplary embodiments, the first address may be a 32-bit address and the second address may be a 40-bit address (as a non-limiting example, the first address may be, for example, a local physical address space of a memory of any suitable device, and the second address may be, for example, a chip-bus addressable global address), and thus step 140-1 may comprise: the value of the 0 th bit to the 31-nth bit of the first address is taken as the first address offset item (in the case where an index information bit is included in the first address, this also means that n bits from the 31 st bit of the first address constitute an index information bit), where n is an integer greater than or equal to 0 and less than or equal to 16. When the descriptor in the format shown in fig. 2 is used, the number of bits of the target address portion available for address expansion in the descriptor is at most 24 bits (i.e., 8 th bit to 31 th bit), and therefore, in the case where the second address is a 40-bit address, the first address to be expanded needs to provide address information of at least 0 th bit to 15 th bit, and thus, an integer having a value range of the parameter n that is greater than or equal to 0 and less than or equal to 16 can be obtained.
In an exemplary embodiment of expanding a 32-bit first address to a 40-bit second address, since the first address to be expanded needs to provide at least 0 th bit to 15 th bit of address information, the size of the minimum effective address interval that can be indicated by 5-bit effective address interval information bits in the descriptor is 2 16 =64K. Thus, table 1 below lists the sizes of the respective effective address intervals that the 5-bit effective address interval information bits of the descriptor can indicate in this case, where each effective address interval is a positive integer power of 2.
Number of bits: 7:3 Size of interval
0x00 64K
0x01 128K
0x02 256K
…… ……
0x0a 64M
0x0b 128M
0x0c 256M
0x0d 512M
…… ……
0x18 1T
0x19-0x1f Out of 40-bit addressing range
Table 1.
As shown in the above table, the maximum value of 5-bit effective address interval information bits of the descriptor is 0x1f, and if 0x00 represents an effective address interval size of 64K, 0x18 represents an effective address interval size of 1T (corresponding to an address space of 40 bits). It follows that it is sufficient to use 5 bits of effective address range information bits to describe the size of the various effective address ranges in an application scenario that extends a 32-bit first address to a 40-bit second address. It should be understood that the number of bits of the effective address range information bits in the descriptor may also have different settings depending on the number of bits of the first address and the second address, e.g., more or fewer bits may be employed to form the effective address range information bits in the descriptor.
In the case of using a descriptor having the format shown in fig. 2, in the above exemplary embodiment of extending the 32-bit first address into the 40-bit second address, step 140-2 may further include: determining a value of bits 24-n through 31 in the uniquely corresponding descriptor as the target base address. In step 140-3, the address range in which the first address is located is determined to be accessible based on the value of the valid bit in the uniquely corresponding descriptor. And, in step 140-4, it is determined that the first address is within the valid address range of the address range corresponding to the unique corresponding descriptor. Since the effective address interval of each address interval is a range determined in conjunction with the effective address interval starting from the first address of the address interval in various applications according to the present disclosure, for any first address, as long as the first address offset term thereof is less than or equal to the size of the effective address interval, it can be determined that the first address is within the range of the effective address interval of the corresponding address interval. If the first address offset entry is greater than the size of the effective address interval, then it can be determined that the first address is outside the range of effective address intervals of the corresponding address interval. Furthermore, it should also be understood that the size of the effective address interval should be less than or equal to the size of the corresponding address interval. Therefore, if the size of the effective address interval is set to be larger than the size of the corresponding address interval in the application, in actual operation, the memory address mapping method may consider the size of the effective address interval as equal to the size of the corresponding address interval by default; additionally or alternatively, the memory address mapping method may also prompt that the size of the effective address interval is currently set to be larger than the size of the corresponding address interval. It should be appreciated that in other exemplary embodiments, when the descriptor uniquely corresponding to the first address indicates that the corresponding address interval is not accessible, or indicates that the first address is outside of a valid address interval in the corresponding address interval, access to the first address may be prompted to be illegal.
With continued reference to FIG. 4, step 140-5 may further include: taking the first address offset entry as bits 0 through 31-n of the second address; and, treating the target base address as bits 32-n through 39 of the second address. In this step, the second address is generated by concatenating the first address offset item and the target base address, thereby implementing the mapping of the first address space to the second address of the second space.
It should be understood that, in this exemplary embodiment, the size (i.e., granularity) of the address interval that needs to be divided may be determined according to the actual needs of the application scenario, and the specific value of the parameter n is determined. For example, the size of the first address space with 32 bits of address bits is 4G, if the size of the address interval is divided into 256M according to the actual needs of the application scenario, then 16 descriptors are needed to describe the whole first address space, and then the value of the parameter n may be 4; if the size of the address interval is divided into 512M, 8 descriptors are needed to describe the whole first address space, and the value of the parameter n may be 3; the rest of the cases can be analogized.
Referring to fig. 5a and 5b, which schematically illustrate an application scenario of address expansion bits, according to some exemplary embodiments of the present disclosure, the application scenario may apply the memory address mapping method as shown in fig. 1, 3a, 3b, and 4 together. FIGS. 5a and 5b illustrate a process of extending a 32-bit first address (e.g., a local physical address space of a memory of any suitable device) into a 40-bit second address (e.g., a chip bus addressable global address), wherein the first address space is divided into 2 4 And (i.e., 16) address intervals, each address interval having a size of 256M.
As shown in fig. 5a, the format of the descriptors used in the application scenario is shown. The descriptor still has a length of 32 bits and has a format similar to that of the descriptor shown in fig. 2. The only difference is that since the first address space is divided into 16 address intervals, 16 descriptors are needed, so that 4 bits in the first address are used as index information bits. In this case, when extending from a 32-bit first address to a 40-bit second address, the first address already provides a 28-bit first address offset entry, and therefore only 12 bits of extended address information need actually be added. Therefore, the number of bits of the target base address available for address expansion bits in the descriptor should be 12 bits. In the descriptor shown in fig. 5a, it is defined that bits 20 to 31 are target Base addresses Dst _ Base for address extension, and bits 8 to 19 are Reserved bits Reserved.
Fig. 5b schematically shows the process of address expansion. As shown in fig. 5b, the first placeThe address is a 32-bit address, since the first address space is divided into 2 4 Since 16 descriptors are required for each (i.e., 16) address interval, the 28 th bit to the 31 th bit of the first address can be defined as Index information bits Index, the values of which can be used to select the corresponding descriptors, and accordingly, the 0 th bit to the 27 th bit of the first address can be defined as the first address Offset item Offset. A uniquely corresponding descriptor can be determined according to the value of the Index information bit Index, and the content of the 20 th bit to the 31 th bit in the descriptor can be used as the target Base address Dst _ Base. When the value of the valid bit V of the uniquely corresponding descriptor is valid (i.e., indicates that the corresponding address range in the first address space is accessible), and when the first address Offset item is less than or equal to the value of the valid address range information bit Size in the uniquely corresponding descriptor, the first address Offset item Offset may be taken as the 0 th bit to the 27 th bit of the second address, and the target Base address Dst _ Base may be taken as the 28 th bit to the 39 th bit of the second address, thereby obtaining the corresponding second address. It can be seen that through the process shown in FIG. 5b, a 32-bit first address of the first address space can be expanded to a 40-bit second address of the second address space.
It should be understood that, as a non-limiting example, the first address of the first address space may be a local physical address for accessing the memory of any suitable device, and the second address of the second address space may be a global address addressed using the chip bus. In the exemplary embodiment shown in fig. 5a and 5b, the address interval may be divided according to actual needs, and therefore, the granularity of address mapping may be much larger than 4K, so that only several descriptors are needed to implement address mapping. In the final design implementation, all transitions can be implemented in 1 clock cycle, thus achieving a low cost, compact, and efficient design.
Referring to fig. 6, further details of the step of determining a unique corresponding descriptor in the memory address mapping method shown in fig. 1 are shown, according to further exemplary embodiments of the present disclosure. The application scenario of the exemplary embodiment to which fig. 6 relates is that of multiple devicesIn the case of using the same address space, for example, in a virtualization scenario, the addresses accessed by the virtual machines are checked and converted. In such an application scenario, the total hardware resources may be divided into m shares, where m is greater than 1 and less than or equal to 2 n And these hardware resources may be allocated to m devices (e.g., m virtual machines). Thus, each device may correspond to a set of descriptors that specify which hardware resources may be used by the device. Therefore, in this application scenario, step 130 in the memory address mapping method 100 shown in fig. 1 may include steps 130c-1 and 130c-2:
determining a corresponding descriptor set from the m descriptor sets based on the serial number of the device at step 130 c-1;
in step 130c-2, the uniquely corresponding descriptor is determined from the corresponding descriptor set based on a value of an index information bit in the first address, wherein the index information bit is composed of predetermined n bits in the first address.
It should be understood that the descriptors in each set may specify which address intervals in the first address space are accessible and which address intervals are not accessible according to the specific value of the respective valid bit. The allocation of the sets of descriptors to the hardware resources corresponding to the first address space may be different from each other. Thus, each set of descriptors essentially describes an allocation of hardware resources to the first address space. Therefore, determining a corresponding descriptor set from the m descriptor sets is essentially to select a hardware resource allocation corresponding to the device from the m hardware resource allocation manners. Furthermore, since there are multiple sets of descriptors, steps 130c-1 and 130c-2 are essentially determining the unique corresponding descriptors in the form of two-dimensional indices in this application scenario. For example, the two-dimensional index may include a sequence number of the device and a value of the index information bit. Of course, it should be understood that any other suitable two-dimensional form of indexing is possible, and the disclosure is not so limited.
After the memory address mapping method 100 according to the present disclosure determines the uniquely corresponding descriptor using the steps shown in fig. 6, the memory address mapping method 100 may continue to use the step 140 shown in fig. 4 to map the first address in the first address space to the second address in the second address space.
In some exemplary embodiments, the first address may be a 35-bit address and the second address may be a 40-bit address (as a non-limiting example, the first address may be, for example, a local memory physical address space assigned to a device or virtual machine, and the second address may be, for example, a chip bus addressable global address), so in this case, step 140-1 may comprise: the value of the 0 th bit to the 34 th-n th bit of the first address is taken as the first address offset item (which means that n bits from the 34 th bit of the first address constitute index information bits), where n is an integer greater than or equal to 0 and less than or equal to 19. The value range of the parameter n in the above exemplary embodiment is obtained as follows: when the descriptor in the format shown in fig. 2 is adopted, the number of bits of the target address portion available for address extension in the descriptor is at most 24 bits (i.e., 8 th bit to 31 th bit), and therefore, in the case where the second address is a 40-bit address, the address to be mapped (e.g., the first address) needs to provide address information of at least 0 th bit to 15 th bit, thereby obtaining an integer having a value range of the parameter n that is greater than or equal to 0 and less than 19. Furthermore, in the process of transforming a 34-bit first address into a 40-bit second address, since an address to be mapped (e.g., the first address) needs to provide at least 0 th bit to 15 th bit of address information, a minimum section size that a 5-bit effective address section information bit of the descriptor can indicate is 2 16 =64K. As described in detail above, the size of each effective address interval that can be indicated by the 5-bit effective address interval information bit in this case is also shown in table 1, and will not be described herein again. It should also be understood that the number of bits of the effective address range information bits in the descriptor may also have different settings depending on the number of bits of the first and second addresses, e.g., more or fewer bits may be employed to form the effective address range information bits in the descriptor.
In the case of using a descriptor having the format shown in fig. 2, in the above exemplary embodiment of mapping a 35-bit first address to a 40-bit second address, step 140-2 may further include: determining a value of bits 27-n through 31 of the uniquely corresponding descriptor as the target base address. In step 140-3, the address range in which the first address is located is determined to be accessible based on the value of the valid bit in the uniquely corresponding descriptor. And, in step 140-4, the first address is determined to be within the effective address range of the address range corresponding to the uniquely corresponding descriptor. Because in each application according to the present disclosure, the effective address interval of each address interval is a range determined in conjunction with the effective address interval, starting from the first address of the address interval. Thus, for any first address, as long as its address offset entry is less than or equal to the size of the effective address interval, it can be determined that the first address is within the range of the effective address interval of the corresponding address interval. If the address offset entry is greater than the size of the effective address interval, then it can be determined that the first address is outside the range of effective address intervals of the corresponding address interval. Furthermore, it should also be understood that the size of the effective address interval should be less than or equal to the size of the corresponding address interval. Therefore, if in an application, the size of the effective address interval is set to be larger than the size of the corresponding address interval, in actual operation, the memory address mapping method according to the present disclosure may consider the size of the effective address interval equal to the size of the corresponding address interval by default; additionally or alternatively, the memory address mapping method may also prompt that the size of the effective address interval is currently set to be larger than the size of the corresponding address interval, so that the operator may reset the setting. It should be appreciated that in other exemplary embodiments, when the descriptor uniquely corresponding to the first address indicates that the corresponding address range is inaccessible or that the first address is outside of a valid address range in the corresponding address range, access to the first address may be prompted to be illegal.
With continued reference to FIG. 4, step 140-5 may further include: taking the first address offset entry as bits 0 through 34-n of the second address; and, treating the target base address as bits 35-n through 39 of the second address. In this step, the second address is generated by splicing the first address offset item and the target base address, thereby implementing the mapping of the first address space to the second address of the second space.
It should be understood that, in this exemplary embodiment, the size (i.e., granularity) of the address interval that needs to be divided may be determined according to the actual needs of the application scenario, and then the specific value of the parameter n is determined. For example, the size of the 35-bit first address space is 32G, if the size of the address interval is divided into 512M according to the actual needs of the application scenario, then 2 is needed 6 If there are 64 descriptors to describe the whole first address space, the parameter n may take the value of 6; the rest of the cases may be analogized.
Referring to fig. 7, an application scenario for checking and transforming addresses accessed by a virtual machine is schematically illustrated, and the application scenario may apply the memory address mapping method as collectively illustrated in fig. 1, 4 and 6. Fig. 7 shows one of a set of descriptors for a virtual machine, and a mapping and permission checking mechanism of local virtual machine addresses to global addresses, where the first address may be a 35-bit address (e.g., a local memory physical address space assigned to a device or virtual machine) and the second address may be a 40-bit address (e.g., a chip bus addressable global address). The first address space (i.e., the address space to which the local virtual machine address belongs) is divided into 2 6 And (i.e., 64) address intervals, and thus, each address interval has a size of 512M, it is possible to specify bits 29 to 34 in the first address as Index information bits Index, and accordingly, it is possible to specify bits 0 to 28 in the first address as a first address Offset item Offset. According to the VMID of the virtual machine, a corresponding descriptor group can be determined from m descriptor groups, and then according to the value of the Index information bit Index, a unique corresponding descriptor group can be determined from the corresponding descriptor groupAnd (4) sign. The contents of the 21 st bit to the 31 st bit in the uniquely corresponding descriptor may be referred to as a target Base address Dst _ Base. When the value of the valid bit V of the uniquely corresponding descriptor is valid (i.e., indicates that the corresponding address range in the first address space is accessible), and when the first address Offset item is less than or equal to the value of the valid address range information bit Size in the uniquely corresponding descriptor, the first address Offset item Offset may be taken as the 0 th bit to the 28 th bit of the second address, and correspondingly, the target Base address Dst _ Base may be taken as the 29 th bit to the 39 th bit of the second address, thereby obtaining the corresponding second address (i.e., global address) in the second address space (i.e., in the global address space to which the global address belongs). In addition, if the value of the valid bit V of the corresponding descriptor is invalid, it means that the address range to which the current virtual machine attempts to access is illegal, and thus, the corresponding logic may prevent the illegal out-of-range access request and may prompt that the access request is illegal.
In the exemplary embodiment shown in fig. 7, on one hand, the address intervals may be divided according to actual needs, so that the granularity of address mapping is much larger than 4K, and thus only a plurality of descriptors are needed to implement address mapping, and on the other hand, different address intervals of hardware resources may be allocated to different virtual machines by grouping the descriptors and setting the valid bits of the descriptors, so that spatial isolation of hardware addresses may be provided for device memory virtualization. In the final design implementation, all the conversion of the memory address mapping of each virtual machine with the hardware address being spatially isolated can be implemented in 2 clock cycles, thereby implementing a low-cost, concise and efficient design.
Referring to fig. 8, a structure of a memory address mapping apparatus according to some exemplary embodiments of the present disclosure is schematically illustrated in a block diagram.
As shown in fig. 8, the memory address mapping apparatus 300 includes: a first address receiving module 310, a device number and sequence number obtaining module 320, a descriptor determining module 330, and an address mapping module 340. The first address receiving module 310 is configured to: a first address of a first address space is received,the first address space is divided into a plurality of address intervals, and the size of each address interval is the same and is a positive integer power of 2. The device number and serial number acquisition module 320 is configured to: acquiring the number m of devices using the first address space, and generating a serial number of each device, wherein m is an integer greater than or equal to 1 and less than or equal to the number of the plurality of address intervals. The descriptor determining module 330 is configured to: determining a descriptor uniquely corresponding to the first address from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, wherein each descriptor includes: the address mapping method comprises indication information indicating accessibility of corresponding address intervals, indication information indicating effective address interval size capable of address mapping in the corresponding address intervals, and target base addresses. The address mapping module 340 is configured to: mapping the first address to a second address of a second address space based on the uniquely corresponding descriptor. According to some exemplary embodiments of the present disclosure, in the memory address mapping apparatus 300, the plurality of address intervals are 2 n An address interval, n is an integer greater than or equal to 0, m is greater than or equal to 1 and less than or equal to 2 n And the m sets of descriptors are m x 2 n A descriptor. As has been described previously, it should be understood that 2 is the number of address intervals involved n An address interval essentially because n bits of a first address in a first address space are used as index information bits, thereby causing the first address space to be divided into 2 n An address interval. According to some example embodiments of the present disclosure, the descriptor determining module 330 of the memory address mapping apparatus 300 may include m × 2 n A register, wherein each register stores the m × 2 n One of the descriptors.
Referring to fig. 9, the structure of a chip according to some exemplary embodiments of the present disclosure is schematically shown in block diagram form. As shown in fig. 9, the chip 500 may include a memory address mapping apparatus 300. It should be understood that chip 500 may be any suitable chip known in the art, including but not limited to a CPU chip, a GPU chip, and the like. The present disclosure does not impose any limitations on the specific type of chip.
It should be understood that the exemplary memory address mapping apparatus 300 illustrated in fig. 8 of the present disclosure may be implemented in any suitable hardware circuitry. These hardware circuits may be implemented using any suitable technique or combination of techniques known in the art. By way of non-limiting example, these techniques include, but are not limited to: discrete logic circuits with logic gates for implementing logic functions on data signals, application specific integrated circuits with appropriate combinational logic gates, programmable gate arrays, field programmable gate arrays, application specific integrated circuits, and the like.
It should be further understood that all or part of the steps of the exemplary memory address mapping methods shown in fig. 1, fig. 3a, fig. 3b, fig. 4, and fig. 6 of the present disclosure may be implemented not only by the memory address mapping apparatus 300 shown in fig. 8, but also by a list of executable instructions. The list of executable instructions may be embodied in any suitable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a system including a processor or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
The terminology used in the present disclosure is for the purpose of describing embodiments in the present disclosure only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and "comprising," when used in this disclosure, specify the presence of stated features but do not preclude the presence or addition of one or more other features. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various features, these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the description of the present specification, the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
It should be understood that the various steps of the methods shown in the flowcharts or otherwise described herein are merely exemplary and are not meant to imply that the steps of the methods shown or described must be performed in accordance with the steps shown or described. Rather, various steps of the methods shown in the flowcharts or otherwise described herein may be performed in a different order than presented in the present disclosure or may be performed concurrently. Further, the methods shown in the flowcharts or otherwise described herein may include other additional steps as desired.
Although the present disclosure has been described in detail in connection with some exemplary embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present disclosure is limited only by the accompanying claims.

Claims (15)

1. A memory address mapping method, comprising:
receiving a first address of a first address space, wherein the first address space is divided into a plurality of address intervals, and the size of each address interval is the same and is a positive integer power of 2;
acquiring the number m of devices using the first address space, and generating a serial number of each device, wherein m is an integer greater than or equal to 1 and less than or equal to the number of the plurality of address intervals;
determining a descriptor uniquely corresponding to the first address from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, wherein a total number of the descriptors is equal to a product of a number of the address intervals and a number of the devices, each group of descriptors corresponds to one device, and each descriptor includes: the method comprises the steps of indicating accessibility of a corresponding address interval in the first address space, indicating information indicating the size of an effective address interval in the corresponding address interval, wherein the effective address interval is obtained by dividing the corresponding address interval again according to the required partition granularity of the first address space, and the size of the effective address interval is smaller than or equal to the size of the corresponding address interval, and a target base address, wherein the number of bits of the target base address is determined based on the number of bits of the first address, the number of bits of a second address space, into which the first address is mapped, and the number of descriptors of each group;
mapping the first address to a second address of a second address space based on the uniquely corresponding descriptor.
2. The memory address mapping method according to claim 1, characterized in that: the plurality of address intervals are 2 n An address interval, n is an integer greater than or equal to 0, and m is greater than or equal to 1 and less than or equal to2 n The m sets of descriptors are m x 2 n A descriptor.
3. The memory address mapping method of claim 2, wherein the descriptor includes a mode control part and a target address information part including the target base address, and the mode control part includes: a valid bit indicating accessibility of the corresponding address interval, a secondary descriptor information bit indicating whether a secondary descriptor is included, a valid address interval information bit indicating a size of a valid address interval in the corresponding address interval where address mapping is possible.
4. The memory address mapping method according to claim 3, wherein the number m of the devices is 1, and n is an integer greater than 0, wherein the determining, from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, a descriptor uniquely corresponding to the first address comprises:
determining a descriptor uniquely corresponding to the first address based on a value of an index information bit in the first address, wherein the index information bit is composed of predetermined n bits in the first address.
5. The memory address mapping method according to claim 3, wherein the number m of devices is 1, and n is equal to 0, wherein the determining, from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, a descriptor uniquely corresponding to the first address comprises:
a descriptor corresponding to a unique address interval is determined as the descriptor uniquely corresponding to the first address.
6. The memory address mapping method according to claim 4 or 5, wherein mapping the first address to a second address of a second address space based on the uniquely corresponding descriptor comprises:
acquiring a first address offset item from the first address;
obtaining the target base address from a target address information portion of the uniquely corresponding descriptor;
determining, based on a value of a valid bit of the unique corresponding descriptor, that an address range to which the unique corresponding descriptor corresponds is accessible;
determining that the first address is within an effective address interval of an address interval corresponding to the unique corresponding descriptor based on the first address offset entry and a value of an effective address interval information bit of the unique corresponding descriptor;
generating the second address based on the first address offset entry and a target base address of the unique corresponding descriptor.
7. The memory address mapping method according to claim 3, wherein the number m of devices is greater than 1, and n is greater than 0, wherein the determining, from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, a descriptor uniquely corresponding to the first address comprises:
determining a corresponding descriptor group from the m descriptor groups based on the serial number of the device;
determining the uniquely corresponding descriptor from the corresponding descriptor set based on a value of an index information bit in the first address, wherein the index information bit is composed of predetermined n bits in the first address.
8. The memory address mapping method of claim 7, wherein the device is a virtual machine.
9. The method of claim 7, wherein mapping the first address to a second address of a second address space based on the unique corresponding descriptor comprises:
acquiring a first address offset item from the first address;
obtaining the target base address from a target address information portion of the uniquely corresponding descriptor;
determining, based on a value of a valid bit of the unique corresponding descriptor, that an address range to which the unique corresponding descriptor corresponds is accessible;
determining that the first address is within an effective address interval of an address interval corresponding to the unique corresponding descriptor based on the first address offset entry and a value of an effective address interval information bit of the unique corresponding descriptor;
generating the second address based on the first address offset entry and a target base address of the unique corresponding descriptor.
10. The memory address mapping method according to claim 3, further comprising: when the secondary descriptor information bit indicates the presence of a secondary descriptor, determining a storage address of the secondary descriptor from the target address information portion.
11. The memory address mapping method according to claim 1, further comprising: when the descriptor uniquely corresponding to the first address indicates that the corresponding address interval is inaccessible or indicates that the first address is located outside an effective address interval in the corresponding address interval, prompting that the access to the first address is illegal.
12. A memory address mapping apparatus, comprising:
a first address receiving module configured to: receiving a first address of a first address space, wherein the first address space is divided into a plurality of address intervals, and the size of each address interval is the same and is a positive integer power of 2;
a device number and serial number acquisition module configured to: acquiring the number m of devices using the first address space, and generating a serial number of each device, wherein m is an integer greater than or equal to 1 and less than or equal to the number of the plurality of address intervals;
a descriptor determination module configured to: determining a descriptor uniquely corresponding to the first address from m groups and each group including descriptors in one-to-one correspondence with the plurality of address intervals, wherein a total number of the descriptors is equal to a product of a number of the address intervals and a number of the devices, each group of descriptors corresponds to one device, and each descriptor includes: indicating information indicating accessibility of a corresponding address interval in the first address space, indicating information indicating a size of an effective address interval in the corresponding address interval, where address mapping is possible, and a target base address, where the effective address interval is obtained by dividing the corresponding address interval again according to a required granularity of partitioning the first address space, and the size of the effective address interval is smaller than or equal to the size of the corresponding address interval, where the number of bits of the target base address is determined based on the number of bits of the first address, the number of bits of a second address space, where the first address is mapped, and the number of each set of descriptors;
an address mapping module configured to: mapping the first address to a second address of a second address space based on the unique corresponding descriptor.
13. The memory address mapping apparatus according to claim 12, wherein: the plurality of address intervals are 2 n An address interval, n is an integer greater than or equal to 0, and m is greater than or equal to 1 and less than or equal to 2 n The m sets of descriptors are mx 2 n A descriptor.
14. The memory address mapping apparatus of claim 13, wherein the descriptor determining module comprises m x 2 n A register, wherein each register stores the m × 2 n One descriptor of the descriptors.
15. A chip comprising the memory address mapping device according to any one of claims 12 to 14.
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