CN115658400A - Method and system for testing computing chip, computer equipment and storage medium - Google Patents
Method and system for testing computing chip, computer equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a method and a system for testing a computing chip, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring operation data of a target chip, predicting fault operation risks according to the operation data, and generating corresponding prediction result data; judging whether a target chip has a fault operation risk or not according to the prediction result data, if so, judging a risk grade corresponding to the target chip, and determining a target test mode adaptive to the risk grade; acquiring test result data synchronously generated by a target chip in the target test mode, and generating a corresponding repair decision according to the test result data; the invention can realize the timely control of the operation risk while the chip operates, thereby improving the test comprehensiveness of the chip. The intelligent diagnosis and repair of chip faults can be realized, and the fault diagnosis and repair efficiency and the automation degree are improved.
Description
Technical Field
The invention relates to the technical field of electric power industrial control network security, in particular to a method and a system for testing a computing chip, computer equipment and a storage medium.
Background
Edge computing and cloud computing are computing operation modes for processing big data, wherein the edge computing specifically extends computing, network, storage and other capabilities to a network edge near the Internet of things equipment, so that data do not need to be transmitted to a remote cloud, some complex intelligent applications can be processed at a local edge, and the technology further meets the requirements of agile connection, real-time service, data optimization, application intelligence, privacy protection and the like, so that data transmission is more efficient and safer.
At present, in the power industry, because the chip structure is fine and the manufacturing process is complicated, potential defects can be inevitably left in the production process, if the generated defects cannot be accurately detected in time, the quality of finished products can be affected, and equipment operation faults can be caused under severe conditions. In order to ensure the quality of a chip, the prior art usually tests the chip before the chip leaves a factory, however, a corresponding test platform is lacked in the actual application process of the chip, so that the accurate test of a potential fault cannot be guaranteed, and the problem of incomplete test exists.
Disclosure of Invention
This section is for the purpose of summarizing some aspects of embodiments of the invention and to briefly introduce some preferred embodiments. In this section, as well as in the abstract and the title of the invention of this application, simplifications or omissions may be made to avoid obscuring the purpose of the section, the abstract and the title, and such simplifications or omissions are not intended to limit the scope of the invention.
The present invention has been made in view of the above-mentioned problems.
Therefore, the technical problem solved by the invention is as follows: the method can accurately test the potential faults of the chip and solve the problem of incomplete test.
In order to solve the technical problems, the invention provides the following technical scheme:
in a first aspect, an embodiment of the present invention provides a method for testing a computing chip, including:
acquiring operation data of a target chip, predicting fault operation risks according to the operation data, and generating corresponding prediction result data;
judging whether a target chip has a fault operation risk or not according to the prediction result data, if so, judging a risk grade corresponding to the target chip, and determining a target test mode adaptive to the risk grade;
and acquiring test result data synchronously generated by the target chip in the target test mode, and generating a corresponding repair decision according to the test result data.
As a preferable scheme of the test method of the computing chip, wherein:
the operation data comprises a real-time operation state, a calculation performance parameter generated in the real-time operation state, historical fault operation information and a calculation performance parameter generated in the real-time operation state; the calculation performance parameters comprise calculation rate, calculation error rate and operation frequency; and calculating the risk probability in a comprehensive evaluation mode according to the actual value of the calculated performance parameter and the corresponding standard value range, and predicting the fault operation risk according to the calculated risk probability to generate corresponding prediction result data.
As a preferable scheme of the test method of the computing chip, wherein:
the calculation of the risk probability includes:
firstly, judging whether the actual value of each calculation performance parameter is in a preset standard value range, if at least one parameter in each calculation performance parameter is in the preset standard value range, adjusting a test period, and calculating the risk probability in the next test period; if no parameter in the various calculation performance parameters is within a preset standard value range, performing weighted calculation of risk probability according to the deviation degree between the actual value and the corresponding standard value of the corresponding calculation performance parameter;
the weighting calculation includes: and setting the weighting coefficient, limiting the value range of the weighting coefficient to 0-1, wherein the greater the deviation degree between the actual value of the corresponding calculation performance parameter and the corresponding standard value is, the more important the calculation performance is maintained, and the closer the value of the corresponding assigned weighting coefficient is to 1.
As a preferable scheme of the test method of the computing chip, wherein:
the determining a risk level includes: calculating a risk trend coefficient according to the prediction result data and by combining historical fault operation information; and integrating the risk trend coefficient, the risk trend characteristics, the covered influence range and the influence degree on the running state of the equipment, calculating a corresponding risk value caused by the potential fault, and judging the risk grade according to the risk value.
As a preferable scheme of the test method of the computational chip, wherein:
the value range of the risk trend coefficient is 0-1, the larger the influence degree of the risk operation trend on the calculation performance of the chip is, the closer the value of the corresponding risk trend coefficient is to 1;
the risk level comprises five types of no risk, low risk, medium risk, high risk and extremely high risk, wherein the risk value is set as k, and when the k is greater than or equal to 80, the risk level is judged to be the extremely high risk level; when k is less than 80 but greater than or equal to 60, determining the risk level as a high risk level; when k is less than 60 but greater than or equal to 30, determining the risk level as medium risk; when k is less than 30 but equal to or greater than 10, the risk level is determined to be a no risk level.
In a second aspect, an embodiment of the present invention provides a computing chip test system, including:
the risk prediction module is used for acquiring the operation data of the target chip, calculating the risk probability according to the operation data, predicting the fault operation risk and generating corresponding prediction result data;
the test module is used for judging the corresponding risk grade of the target chip and determining a target test mode which is suitable for the risk grade if the target chip is judged to have the fault operation risk according to the obtained prediction result data;
and the repair suggestion module is used for acquiring test result data synchronously generated by the corresponding target chip in the target test mode and generating a corresponding repair decision according to the test result data.
As a preferable scheme of the test system of the computing chip, wherein:
the system also includes a dead pixel recording module, wherein:
and the dead pixel recording module is used for acquiring the test result data and recording the dead pixel position according to the test result data.
As a preferable aspect of the test system for a computing chip, wherein:
the system also comprises a decision classification module and a decision calling module, wherein:
the decision classification module is used for carrying out data classification on the obtained repair decisions and carrying out partition storage on the obtained repair decisions according to data classification conditions, wherein the calculated performance parameters related to the corresponding repair decisions, the corresponding obtained risk probability values and the risk operation trends are synchronously cached in the storage process;
the decision calling module is used for calling and feeding back a target decision from the stored repair decisions based on at least one of the calculated performance parameters, the risk probability values and the risk operation trends acquired in real time, and triggering the repair suggestion module to generate a corresponding repair decision under the condition of failure in matching.
In a third aspect, an embodiment of the present invention provides a computing device, including:
a memory and a processor;
the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions, when the one or more programs are executed by the one or more processors, to cause the one or more processors to implement the method for testing a computing chip according to any embodiment of the present invention.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the computer-executable instructions implement the method for testing a computing chip.
The invention has the beneficial effects that: according to the invention, the running data of the target chip is obtained, and the fault running risk is predicted according to the running data, so that the running risk can be timely controlled while the chip runs, and the test comprehensiveness of the chip is improved. In addition, when the corresponding target chip has a fault operation risk, a target test mode adaptive to the corresponding risk level can be determined according to the obtained prediction result data, and a corresponding repair decision is generated according to the correspondingly obtained test result data, so that intelligent diagnosis and repair of chip faults are realized, and the fault diagnosis and repair efficiency and the automation degree are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:
FIG. 1 is a schematic structural diagram of a computer chip test system according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for testing a computing chip according to a second embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures of the present invention are described in detail below, and it is apparent that the described embodiments are a part, not all or all of the embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Furthermore, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
The present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially in general scale for convenience of illustration, and the drawings are only exemplary and should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Also in the description of the present invention, it should be noted that the terms "upper, lower, inner and outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms first, second, or third are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The terms "mounted, connected" and "connected" in the present invention are to be construed broadly, unless otherwise explicitly specified or limited, for example: can be fixedly connected, detachably connected or integrally connected; they may be mechanically, electrically, or directly connected, or indirectly connected through intervening media, or may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
Example 1
Referring to fig. 1, a first embodiment of the present invention provides a system for testing a computing chip, where the system 100 includes a risk prediction module 101, a test module 102, and a repair suggestion module 103, which are communicatively connected, where:
the risk prediction module 101 is configured to obtain operation data of a target chip, predict a fault operation risk according to the operation data, and generate corresponding prediction result data, where the operation data includes a real-time operation state, a calculation performance parameter generated in the real-time operation state, and historical fault operation information.
The test module 102 is configured to determine a target test mode adapted to a corresponding risk level when the corresponding target chip is considered to have a failure operation risk according to the obtained prediction result data,
the repair suggestion module 103 is configured to obtain test result data synchronously generated by the corresponding target chip in the target test mode, and generate a corresponding repair decision according to the test result data.
Furthermore, the risk prediction module is also used for predicting the failure operation risk through the following steps: the method comprises the steps of obtaining a real-time running state of a target chip and calculation performance parameters generated in the real-time running state, wherein the calculation performance parameters comprise a calculation rate, a calculation error rate and a running frequency. Calculating the risk probability in a comprehensive evaluation mode according to the actual value of the calculated performance parameter and the corresponding standard value range; and predicting the fault operation risk according to the calculated risk probability.
The risk prediction module is further used for calculating the risk probability by the following steps: judging whether the actual value of each calculation performance parameter is within a preset standard value range, if at least one of the calculation performance parameters is determined to judge the condition, adjusting the test period, and calculating the risk probability in the next test period; otherwise, carrying out weighted calculation of the risk probability according to the deviation degree between the actual value and the corresponding standard value of the corresponding calculation performance parameter.
Specifically, the risk prediction module may calculate a comparison result between an actual value and a standard value range of the performance parameter, and when it is determined that the actual value is within the standard value range, the risk prediction module considers that the probability of the current running risk is low, and may enter a next test period, and immediately may calculate the risk probability in the next test period under the condition of adjusting the test period. The risk prediction module can adjust the test period according to the comprehensive operation condition of the target chip, and when each calculation performance parameter can meet the judgment condition, the test period can be properly prolonged.
It should be noted that the risk prediction module adjusts the test period according to the comprehensive operation condition of the target chip, which avoids wasting resources and can achieve the effect of reducing cost.
Aiming at the condition of running risk, the risk prediction module can also calculate the deviation degree between the actual value and the corresponding standard value of the corresponding calculation performance parameter, and set the weighting coefficient according to the deviation degree and the importance of the calculation performance parameter on maintaining the calculation performance. For example, the value range of the weighting coefficient is limited to 0 to 1, wherein if the degree of deviation between the actual value of the corresponding calculation performance parameter and the corresponding standard value is more important for maintaining the calculation performance, the value of the weighting coefficient corresponding thereto is closer to 1.
It should be noted that the risk brought to the operation of the equipment by describing the uncertainty of the calculated performance parameters improves the pre-judgment capability of the equipment on the risk and ensures the safe and stable operation of the equipment.
Further, the testing module is further configured to determine a risk level by: calculating a risk trend coefficient according to the acquired prediction result data and by combining historical fault operation information; and integrating the risk trend coefficient, the risk trend characteristics, the covered influence range and the influence degree on the running state of the equipment, calculating a corresponding risk value caused by the potential fault, and judging the risk grade according to the risk value.
Specifically, the test module may perform, according to the obtained prediction result data, judgment of the risk operation trend in combination with the historical fault operation information, and perform calculation of the risk trend coefficient according to the degree of influence of the judged risk operation trend on the chip calculation performance. The value range of the risk trend coefficient can be 0-1, wherein under the condition that the influence degree of the risk operation trend on the calculation performance of the chip is larger, the value of the corresponding risk trend coefficient is closer to 1.
Specifically, the risk level may include five types of no, low, medium, high and extremely high risks, wherein if the risk value is set to k, it may be assumed that: (1) When k is greater than or equal to 80, determining the risk level as an extremely high risk level; (2) When k is less than 80 but greater than or equal to 60, determining the risk level as a high risk level; (3) When k is less than 60 but greater than or equal to 30, determining the risk level as medium risk; (4) When k is less than 30 but greater than or equal to 10, the risk level is determined to be a no risk level. The above determination range is not limited to this manner, and in different embodiments, the determination range may be flexibly set according to the operation state of the device, the operation environment, the prior experience, and the like, which is not limited in the embodiment of the present application.
The system also includes a dead pixel recording module, wherein:
the dead pixel recording module is also used for obtaining test result data and recording the dead pixel position according to the test result data.
It should be noted that, through the dead pixel recording module, the recording data of the dead pixel position can be synchronously fed back to the equipment operation and maintenance personnel, so that the equipment operation and maintenance personnel can quickly locate the fault pixel position according to the acquired dead pixel position data, analyze the fault reason generated at the fault pixel position, and improve the equipment repair efficiency.
The system also comprises a decision classification module and a decision calling module, wherein:
the decision classification module is used for carrying out data classification on the obtained repair decisions and carrying out partition storage on the obtained repair decisions according to data classification conditions, wherein the calculated performance parameters related to the corresponding repair decisions, the corresponding obtained risk probability values and the risk operation trends are synchronously cached in the storage process.
Specifically, the decision classification module may perform partition storage on each item of acquired repair decision data through a built-in cache space, and may also analyze the number of times of calling each item of stored data in the storage process, and preferentially move the target stored data out of the storage area to release the cache space for target stored data with a small number of times of calling if the data is not called after storage.
In the storage process, for the data to be cached, the decision classification module may further adjust the caching speed of the data to be cached according to the size of the remaining available cache space and the device operating state, or when it is determined that the remaining available cache space does not guarantee full-disk storage of the data to be cached, a corresponding data compression method may be adopted, for example, a redundancy compression method or a lossless compression method (it should be noted that the redundancy compression method or the lossless compression method is also called a lossless compression method or an entropy encoding method.
The decision calling module is used for calling and feeding back a target decision from the stored repair decisions based on at least one of the calculated performance parameters, the risk probability values and the risk operation trends acquired in real time, and triggering the repair suggestion module to generate a corresponding repair decision under the condition of failed matching.
Specifically, when the decision calling module performs partition storage on each obtained repair decision, the decision calling module may perform associated storage on at least one of a calculation performance parameter, a risk probability value, and a risk operation trend related to the repair decision. Therefore, in the next testing process, under the condition that the corresponding risk operation trend is obtained through calculation, for example, whether the repair decision related to the corresponding risk operation trend is generated or not can be judged according to the corresponding risk operation trend, if yes, the repair decision is directly called, and otherwise, the repair suggestion module is triggered to generate the corresponding repair decision.
It should be noted that the decision calling module can improve the system operation efficiency by avoiding repeated generation of the repair decision, and can also perform data processing by combining with the previous processing experience, thereby improving the data processing efficiency and reducing the use cost.
Example 2
Referring to fig. 2, a method for testing a computing chip is provided as an embodiment of the present invention, and in order to verify the beneficial effects of the present invention, scientific demonstration is performed through simulation experiments.
S1: the method comprises the steps of obtaining operation data of a target chip by a trigger risk prediction module, predicting fault operation risks according to the operation data, and generating corresponding prediction result data, wherein the operation data comprise a real-time operation state, calculation performance parameters generated in the real-time operation state and historical fault operation information.
Specifically, the risk prediction module is triggered to acquire a real-time running state of the target chip and calculation performance parameters generated in the real-time running state, wherein the calculation performance parameters include a calculation rate, a calculation error rate and a running frequency.
And the trigger risk prediction module calculates the risk probability in a comprehensive evaluation mode according to the actual value of the calculated performance parameter and the corresponding standard value range.
And the trigger risk prediction module predicts the fault operation risk according to the calculated risk probability.
The calculating of the risk probability according to the actual value of the calculated performance parameter and the corresponding standard value range by a comprehensive evaluation mode comprises the following steps:
the method comprises the steps that a risk prediction module is triggered to judge whether actual values of various calculation performance parameters are within a preset standard value range, if at least one parameter of the calculation performance parameters is determined to be within the preset standard value range, a test period is adjusted, and risk probability calculation is carried out in the next test period; and if no parameter in the various calculation performance parameters is within a preset standard value range, performing weighted calculation of the risk probability according to the deviation degree between the actual value and the corresponding standard value of the corresponding calculation performance parameter.
S2: and the trigger test module determines a target test mode adaptive to the corresponding risk level when the corresponding target chip is considered to have a fault operation risk according to the acquired prediction result data.
S3: and the trigger repair suggestion module acquires test result data synchronously generated by the corresponding target chip in the target test mode and generates a corresponding repair decision according to the test result data.
Compared with the traditional computational chip test method, the computational chip test method used in the simulation experiment has the following experimental effects:
| conventional methods | Method for producing a composite material | |
| Chip test coverage | 98％ | 100％ |
| Mean time to failure diagnosis of chip | 320ns | 240ns |
| Efficiency of chip fault repair | 48％ | 79％ |
Therefore, the method for testing the computing chip used in the embodiment can realize timely handling and control of the operation risk and improve the comprehensiveness of chip testing while ensuring the operation of the chip by acquiring the operation data of the target chip and predicting the fault operation risk according to the operation data. In addition, according to the obtained prediction result data, when the corresponding target chip is considered to have the fault operation risk, a target test mode adaptive to the corresponding risk level is determined, and a corresponding repair decision is generated according to the corresponding obtained test result data, so that intelligent diagnosis and repair of chip faults can be realized, and the fault diagnosis and repair efficiency and the automation degree are improved.
It should be noted that the above-mentioned embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (10)
1. A method for testing a computing chip, comprising:
acquiring operation data of a target chip, predicting fault operation risks according to the operation data, and generating corresponding prediction result data;
judging whether a fault operation risk exists in the target chip or not according to the prediction result data, if so, judging a risk grade corresponding to the target chip, and determining a target test mode adaptive to the risk grade;
and acquiring test result data synchronously generated by the target chip in the target test mode, and generating a corresponding repair decision according to the test result data.
2. The computing chip testing method of claim 1, comprising: the operation data comprises a real-time operation state, a calculation performance parameter generated in the real-time operation state, historical fault operation information and a calculation performance parameter generated in the real-time operation state; the calculation performance parameters comprise calculation rate, calculation error rate and operation frequency; and calculating the risk probability in a comprehensive evaluation mode according to the actual value of the calculated performance parameter and the corresponding standard value range, and predicting the fault operation risk according to the calculated risk probability to generate corresponding prediction result data.
3. The computational chip testing method of claim 2 wherein the calculating of the risk probability includes:
firstly, judging whether the actual value of each calculation performance parameter is in a preset standard value range, if at least one parameter in each calculation performance parameter is in the preset standard value range, adjusting a test period, and calculating the risk probability in the next test period; if no parameter in the various calculation performance parameters is within a preset standard value range, performing weighted calculation of risk probability according to the deviation degree between the actual value and the corresponding standard value of the corresponding calculation performance parameter;
the weighting calculation includes: and setting the weighting coefficient, limiting the value range of the weighting coefficient to 0-1, wherein the greater the deviation degree between the actual value of the corresponding calculation performance parameter and the corresponding standard value is, the more important the calculation performance is maintained, and the closer the value of the corresponding assigned weighting coefficient is to 1.
4. The computing chip testing method of claim 1, wherein said determining a risk level comprises: calculating a risk trend coefficient according to the prediction result data and by combining historical fault operation information; and integrating the risk trend coefficient, the risk trend characteristics, the covered influence range and the influence degree on the running state of the equipment, calculating a corresponding risk value caused by the potential fault, and judging the risk grade according to the risk value.
5. The test method for the computing chip of claim 4, wherein the value range of the risk trend coefficient is 0-1, and the larger the influence degree of the risk operation trend on the computing performance of the chip is, the closer the value of the corresponding risk trend coefficient is to 1;
the risk level comprises five types of no risk, low risk, medium risk, high risk and extremely high risk, wherein the risk value is set as k, and when k is greater than or equal to 80, the risk level is judged to be the extremely high risk level; when k is less than 80 but greater than or equal to 60, determining the risk level as a high risk level; when k is less than 60 but greater than or equal to 30, determining the risk level as medium risk; when k is less than 30 but equal to or greater than 10, the risk level is determined to be a no risk level.
6. A computing chip test system, comprising:
the risk prediction module is used for acquiring the operation data of the target chip, calculating the risk probability according to the operation data, predicting the fault operation risk and generating corresponding prediction result data;
the test module is used for judging the corresponding risk grade of the target chip and determining a target test mode which is suitable for the risk grade if the target chip is judged to have the fault operation risk according to the obtained prediction result data;
and the repair suggestion module is used for acquiring test result data synchronously generated by the corresponding target chip in the target test mode and generating a corresponding repair decision according to the test result data.
7. The computing chip test system of claim 6, wherein the system further comprises a bad point record module, wherein:
and the dead pixel recording module is used for acquiring test result data and recording the position of a dead pixel according to the test result data.
8. The computing chip test system of claim 6, further comprising a decision classification module and a decision invocation module, wherein:
the decision classification module is used for carrying out data classification on the obtained repair decisions and carrying out partition storage on the obtained repair decisions according to data classification conditions, wherein the calculated performance parameters related to the corresponding repair decisions, the corresponding obtained risk probability values and the risk operation trends are synchronously cached in the storage process;
the decision calling module is used for calling and feeding back a target decision from the stored repair decisions based on at least one of the calculated performance parameters, the risk probability values and the risk operation trends acquired in real time, and triggering the repair suggestion module to generate a corresponding repair decision under the condition of failed matching.
9. A computing device, comprising:
a memory and a processor;
the memory is configured to store computer-executable instructions and the processor is configured to execute the computer-executable instructions, which when executed by the processor implement the steps of the computer chip testing method of any one of claims 1 to 5.
10. A computer-readable storage medium storing computer-executable instructions which, when executed by a processor, implement the steps of the computational chip testing method of any one of claims 1 to 5.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116302899A (en) * | 2023-05-18 | 2023-06-23 | 中诚华隆计算机技术有限公司 | Core particle fault diagnosis method and device |
| CN117316248A (en) * | 2023-10-13 | 2023-12-29 | 广东全芯半导体有限公司 | TF card operation intelligent detection system based on deep learning |
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2022
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116302899A (en) * | 2023-05-18 | 2023-06-23 | 中诚华隆计算机技术有限公司 | Core particle fault diagnosis method and device |
| CN116302899B (en) * | 2023-05-18 | 2023-07-28 | 中诚华隆计算机技术有限公司 | Core particle fault diagnosis method and device |
| CN117316248A (en) * | 2023-10-13 | 2023-12-29 | 广东全芯半导体有限公司 | TF card operation intelligent detection system based on deep learning |
| CN117316248B (en) * | 2023-10-13 | 2024-03-15 | 广东全芯半导体有限公司 | TF card operation intelligent detection system based on deep learning |
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