CN115658376B - Reset circuit, electronic equipment, surveillance camera and digital video recorder - Google Patents
Reset circuit, electronic equipment, surveillance camera and digital video recorder Download PDFInfo
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- CN115658376B CN115658376B CN202211688074.XA CN202211688074A CN115658376B CN 115658376 B CN115658376 B CN 115658376B CN 202211688074 A CN202211688074 A CN 202211688074A CN 115658376 B CN115658376 B CN 115658376B
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Abstract
The embodiment of the invention provides a reset circuit, electronic equipment, a monitoring camera and a hard disk video recorder, wherein the reset circuit comprises: the circuit comprises a watchdog circuit, a switch circuit and a pulse trigger circuit; the watchdog circuit is used for sending a reset signal to a reset input end of the main system circuit when the main system circuit is monitored to be abnormal, and the switch circuit is used for conducting under the condition that the main system circuit is abnormal when being electrified; the pulse trigger circuit is used for outputting a pulse trigger signal to the watchdog circuit under the condition that the switch circuit is conducted, so that the watchdog circuit sends a reset signal to the main system circuit through the output end after receiving the pulse trigger signal. And under the condition that the main system circuit is electrified abnormally, the switch circuit is conducted, so that the watchdog circuit outputs the pulse trigger signal, the watchdog circuit sends a reset signal to the main system circuit through the output end after receiving the pulse trigger signal, and the main system circuit is restarted.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a reset circuit, electronic equipment, a monitoring camera and a hard disk video recorder.
Background
In the related art, in order to ensure that the system works normally, the electronic device may be provided with a watchdog circuit on a circuit board of the electronic device. The watchdog circuit is electrically connected with a main system circuit of the electronic device.
Generally, after a main system circuit is powered on and normally started, a trigger signal is output to start a watchdog circuit, so that the watchdog circuit starts to count automatically, then a pulse signal, commonly called a 'dog feeding' signal, is output to the watchdog circuit, and the watchdog circuit clears counted numbers once at intervals. If the main system circuit works normally, the pulse signal is normally output, the watchdog circuit always operates normally, and if the main system circuit has a program error and does not output the pulse signal on time, the watchdog circuit sends a reset signal to the main system circuit for a certain time so as to reset and restart the main system circuit.
Therefore, the watchdog circuit can realize the reset function only after the main system circuit is powered on and normally started. If the main system circuit is abnormal when being electrified and is not normally started, the trigger signal cannot be input to the watchdog circuit, so that the watchdog circuit cannot be started, and the reset function of the watchdog circuit fails. In this case, the main system circuit can only be restarted manually.
In actual life, for various electronic devices installed in different scenes, the electronic devices are generally checked manually and periodically to determine whether the electronic devices are abnormal, and if the electronic devices are abnormal, the electronic devices are restarted manually, so that the abnormality of the electronic devices cannot be detected in time and cannot be restarted in time. Especially for monitoring equipment for real-time monitoring, such as a monitoring camera, a hard disk video recorder, a sound pick-up and the like, many of the monitoring equipment can be installed at a high place or some other extreme scenes, for example, a high place of a warehouse, a high place of a market, a high place of a telegraph pole and the like, if the monitoring equipment is detected to be abnormal, the monitoring equipment cannot work normally, the monitoring equipment at other extreme scenes such as the high place and the like needs to be restarted by manually utilizing a shelf or a ladder, a large amount of cost needs to be consumed, and potential safety hazards also exist.
Therefore, how to reset and restart the main system circuit in time under the condition that the main system circuit is abnormal when being electrified is a problem which needs to be solved urgently at present.
Disclosure of Invention
The embodiment of the invention aims to provide a reset circuit, electronic equipment, a monitoring camera and a hard disk video recorder so as to realize that a main system circuit can still be normally started when the main system circuit is abnormal during power-on. The specific technical scheme is as follows:
a first aspect of an embodiment of the present invention provides a reset circuit of an electronic device, where the electronic device includes a main system circuit, and the reset circuit includes: the circuit comprises a watchdog circuit, a switch circuit and a pulse trigger circuit;
the input end of the watchdog circuit is connected with the first output end of the main system circuit, the output end of the watchdog circuit is connected with the reset input end of the main system circuit, and the watchdog circuit is used for starting after receiving a starting signal sent by the main system circuit and sending a reset signal to the reset input end of the main system circuit when monitoring that the main system circuit is abnormal, so that the main system circuit is reset and restarted;
the control end of the switch circuit is connected with the second output end of the main system circuit, and the output end of the switch circuit is connected with the input end of the pulse trigger circuit and is used for conducting under the condition of abnormity when the main system circuit is electrified;
the output end of the pulse trigger circuit is connected with the reset input end of the watchdog circuit and used for outputting a pulse trigger signal to the watchdog circuit under the condition that the switch circuit is switched on, so that the watchdog circuit sends a reset signal to the main system circuit through the output end after receiving the pulse trigger signal.
Optionally, the switch circuit includes a PNP transistor,
the base electrode of the PNP triode is a control end; when the main system circuit is abnormal during power-on, the second output end outputs low level; the second output end outputs high level under the normal condition of the main system circuit during power-on; when the base electrode of the PNP triode receives a low level, the PNP triode is conducted; when the base electrode of the PNP triode receives a high level, the PNP triode is cut off;
the collector of the PNP triode is connected with a power supply end;
and the emitting electrode of the PNP triode is an output end.
Optionally, the pulse trigger circuit includes: the circuit comprises a timer, a first resistor, a second resistor and a capacitor;
a first end of the first resistor is connected with an output end of the switch circuit, a second end of the first resistor is connected with a first end of the second resistor and a discharge end of the timer, a second end of the second resistor is connected with a first end of the capacitor, a low trigger end of the timer and a high trigger end of the timer, a second end of the capacitor is grounded, and an output end of the timer is connected with a reset input end of the watchdog circuit;
the oscillation period of the pulse trigger signal is greater than the sum of the delay time of the watchdog circuit and the normal starting time of the main system circuit.
Optionally, the first resistor, the second resistor and the capacitor;
satisfies the following conditions: 1/f > T + td, f =1.44/[ (R1 +2R 2) × C ];
wherein 1/f is an oscillation period of the pulse trigger signal, f is an oscillation frequency of the pulse trigger signal, T is a time length of normal start of the main system circuit, td is a time delay time length of the watchdog circuit, R1 is a resistance value of the first resistor, R2 is a resistance value of the second resistor, and C is a capacitance value of the capacitor.
A second aspect of embodiments of the present invention provides an electronic apparatus including a main system circuit and the reset circuit described in any one of the above.
A third aspect of an embodiment of the present invention provides a monitoring camera, including a camera module, a main system circuit, and any one of the reset circuits described above.
A fourth aspect of the embodiments of the present invention provides a hard disk video recorder, including a video recording module, a main system circuit, and any one of the reset circuits described above.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a reset circuit, electronic equipment, a monitoring camera and a hard disk video recorder, wherein the reset circuit comprises: the circuit comprises a watchdog circuit, a switch circuit and a pulse trigger circuit; the input end of the watchdog circuit is connected with the first output end of the main system circuit, the output end of the watchdog circuit is connected with the reset input end of the main system circuit, and the watchdog circuit is used for starting after receiving a starting signal sent by the main system circuit and sending a reset signal to the reset input end of the main system circuit when monitoring that the main system circuit is abnormal, so that the main system circuit is reset and restarted; the control end of the switch circuit is connected with the second output end of the main system circuit, and the output end of the switch circuit is connected with the input end of the pulse trigger circuit and is used for conducting under the condition of abnormity when the main system circuit is electrified; the output end of the pulse trigger circuit is connected with the reset input end of the watchdog circuit, and the pulse trigger circuit is used for outputting a pulse trigger signal to the watchdog circuit under the condition that the switch circuit is switched on, so that the watchdog circuit sends a reset signal to the main system circuit through the output end after receiving the pulse trigger signal.
Therefore, by applying the reset circuit of the embodiment of the invention, the switch circuit can be turned on under the condition that the main system circuit is powered on abnormally, so that the watchdog circuit outputs the pulse trigger signal, the watchdog circuit sends the reset signal to the main system circuit through the output end after receiving the pulse trigger signal, the main system circuit is restarted, and the normal starting of the main system circuit can be realized even if the main system circuit is abnormal during the power-on.
In addition, the electronic equipment applying the reset circuit of the embodiment of the invention, especially for some electronic equipment installed in extreme scenes, such as a monitoring camera, a hard disk video recorder, a sound pick-up and the like, realizes automatic restart under the condition of power-on abnormity of a main system circuit, does not need to go to the site to manually restart, can be restarted in time, does not need to increase labor cost, and does not have potential safety hazard.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by referring to these drawings.
Fig. 1 is a schematic diagram of a first reset circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a second reset circuit according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a third reset circuit according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a fourth reset circuit according to an embodiment of the present invention;
FIG. 5a is a schematic diagram showing waveforms of an input terminal WDI and an output terminal/RESET of the watchdog after a sudden abnormality occurs during normal operation of the main system circuit;
FIG. 5b is a schematic waveform diagram of the manual RESET pin/MR and the output terminal/RESET of the watchdog after the main system circuit is abnormal in power-on;
FIG. 6 is a schematic diagram of an electronic device according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a surveillance camera provided in accordance with an embodiment of the present invention;
fig. 8 is a schematic diagram of a hard disk recorder according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived from the embodiments of the present invention by those skilled in the art based on the description, are within the scope of the present invention.
An embodiment of the present invention provides a reset circuit of an electronic device, where the electronic device includes a main system circuit 100, and referring to fig. 1, the reset circuit shown in fig. 1 may include: a watchdog circuit 101, a switch circuit 102, and a pulse trigger circuit 103;
an Input end WDI (watchdog Input) of the watchdog circuit 101 is connected to a first Output end GPIO1 (General Purpose Input and Output) of the main system circuit 100, and an Output end/RESET is connected to a RESET Input end NRST of the main system circuit 100, and is configured to be turned on after receiving a start signal sent by the main system circuit 100, and send a RESET signal to the RESET Input end NRST of the main system circuit 100 when monitoring that the main system circuit 100 is abnormal, so as to RESET and restart the main system circuit 100;
the control end of the switch circuit 102 is connected to a second output end GPIO2 of the main system circuit 100, and the output end is connected to the input end of the pulse trigger circuit 103, and is used for conducting when the main system circuit 100 is powered on and abnormal;
an output terminal of the pulse trigger circuit 103 is connected to a RESET input terminal/MR (manual RESET input) of the watchdog circuit 101, and is configured to output a pulse trigger signal to the watchdog circuit 101 when the switch circuit 102 is turned on, so that the watchdog circuit 101 sends a RESET signal to the main system circuit 100 through the output terminal/RESET after receiving the pulse trigger signal.
In an embodiment of the present invention, a reset circuit includes: the circuit comprises a watchdog circuit, a switch circuit and a pulse trigger circuit; the input end of the watchdog circuit is connected with the first output end of the main system circuit, the output end of the watchdog circuit is connected with the reset input end of the main system circuit, and the watchdog circuit is used for starting after receiving a starting signal sent by the main system circuit and sending a reset signal to the reset input end of the main system circuit when monitoring that the main system circuit is abnormal, so that the main system circuit is reset and restarted; the control end of the switching circuit is connected with the second output end of the main system circuit, and the output end of the switching circuit is connected with the input end of the pulse trigger circuit and is used for conducting under the condition that the main system circuit is abnormal when being electrified; the output end of the pulse trigger circuit is connected with the reset input end of the watchdog circuit and used for outputting a pulse trigger signal to the watchdog circuit under the condition that the switch circuit is switched on, so that the watchdog circuit sends a reset signal to the main system circuit through the output end after receiving the pulse trigger signal.
Therefore, by applying the reset circuit of the embodiment of the invention, the switch circuit can be turned on under the condition that the main system circuit is electrified abnormally, so that the watchdog circuit outputs the pulse trigger signal, the watchdog circuit sends the reset signal to the main system circuit through the output end after receiving the pulse trigger signal, the main system circuit is restarted, and the normal starting of the main system circuit can be realized even if the main system circuit is electrified abnormally.
In addition, the electronic equipment applying the reset circuit of the embodiment of the invention, especially for some electronic equipment installed in extreme scenes, such as a monitoring camera, a hard disk video recorder, a sound pick-up and the like, realizes automatic restart under the condition of abnormal power-on of a main system circuit, does not need to manually restart on site, can be restarted in time, does not need to increase labor cost, and does not have potential safety hazard.
In a possible implementation, referring to fig. 2, the switch circuit 102 may specifically include a PNP transistor Q, and a base of the PNP transistor Q is a control terminal; the collector of the PNP triode Q is connected with a circuit power supply end VCC (power supply voltage of the circuit); the emitter of the PNP triode Q is the output terminal. When the main system circuit 100 is abnormal during power-on, the second output terminal GPIO2 outputs a low level; under the normal condition of the main system circuit 100 during power-on, the second output terminal GPIO2 outputs a high level; when the base electrode of the PNP triode Q receives a low level, the PNP triode Q is conducted; when the base electrode of the PNP triode Q receives a high level, the PNP triode Q is cut off.
In the embodiment of the invention, the on-off of the switch circuit is realized through the PNP triode, and the second output end outputs the low level under the condition that the main system circuit is abnormal when being electrified, so that the base electrode of the PNP triode receives the low level conduction, the pulse trigger circuit can work normally, the pulse trigger signal is sent to the watchdog circuit, the watchdog circuit sends the reset signal to the main system circuit through the output end after receiving the pulse trigger signal, and the main system circuit is restarted.
In one possible implementation, referring to fig. 3, the pulse trigger circuit 103 may include: the timer U1, the first resistor R1, the second resistor R2 and the capacitor C; a first end of the first resistor R1 is connected to an output end of the switch circuit 102, a second end of the first resistor R1 is connected to a first end of the second resistor R2 and a discharge end DISCH (discharge) of the timer U1, a second end of the second resistor R2 is connected to a first end of the capacitor C, a low trigger end TRIG of the timer U1, and a high trigger end THRES of the timer U1, a second end of the capacitor C is grounded GND (Ground, which represents Ground), and an output end OUT of the timer U1 is connected to a reset input end/MR of the watchdog circuit; the oscillation period of the pulse trigger signal is greater than the sum of the delay time of the watchdog circuit 101 and the normal start time of the main system circuit 100.
In one example, the normal start-up time of the main system circuit is 10 seconds, the delay time of the watchdog circuit is 0.2 seconds, and the oscillation period of the pulse trigger signal needs to be greater than 10.2 seconds.
In one possible embodiment, the first resistor R1, the second resistor R2 and the capacitor C; satisfies the following conditions: 1/f > T + td, f =1.44/[ (R1 +2R 2) × C ]; wherein 1/f is the oscillation period of the pulse trigger signal, f is the oscillation frequency of the pulse trigger signal, T is the normal start time of the main system circuit, td is the delay time of the watchdog circuit, R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, and C is the capacitance value of the capacitor.
In the embodiment of the present invention, the oscillation period of the pulse trigger signal is determined by the first resistor, the second resistor and the capacitor, and the oscillation frequency can be changed by adjusting the resistance value of the first resistor, the resistance value of the second resistor and the capacitance value of the capacitor, wherein the larger the resistance value of the first resistor, the lower the oscillation frequency is, the longer the oscillation period is, and a circuit with a longer start duration of a main system circuit can be satisfied.
In an example, referring to fig. 4, the reset circuit is specifically described in the present embodiment, and the reset circuit shown in fig. 4 includes: the circuit comprises a watchdog circuit, a switch circuit and a pulse trigger circuit; the watchdog circuit includes: a monitor U3 with the model number of APX823-31W5G-7 and a capacitor C1, wherein the monitor is a watchdog.
The switching circuit includes: PNP triode Q1, resistance R3 and resistance R4; the pulse trigger circuit includes: the circuit comprises a timer U2 with the model number of NE555, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a resistor R1 and a resistor R2.
The second output end GPIO2 of the main system circuit is connected with a resistor R3 and the base electrode of the PNP triode Q1, and the other end of the resistor R3 is grounded GND.
The collector of the PNP triode Q1 is connected with the resistor R4 in series and then connected to a circuit power supply end VCC, and the emitter of the PNP triode Q1 is connected to the resistor R1; the other end of the resistor R1 is connected with the resistor R2 and a discharge end DISCH of the timer U2; the other end of the resistor R2 is connected with the capacitor C2, the low trigger end TRIG of the timer U2 and the high trigger end THRES of the timer U2; the other end of the capacitor C2 is grounded.
The power supply terminal VCC of the timer U2 is connected to the power supply terminal VCC of the circuit, the power supply terminal VCC of the circuit is connected with the capacitor C3 and the capacitor C4, the capacitor C3 is connected with the capacitor C4 in parallel, and the other end of the capacitor C3 is grounded; the voltage control end CONT of the timer U2 is connected with the capacitor C5, the other end of the capacitor C5 is grounded, the direct RESET end RESET of the timer U2 is connected to the circuit power supply end VCC, the output end OUT of the timer U2 is connected with the manual RESET input end/MR of the monitor U3, and the power supply ground end GND of the timer U2 is grounded.
The RESET output end/RESET of the monitor U3 is connected with the RESET input end NRST of the main system circuit; the power supply ground end GND of the monitor U3 is grounded; an input end WDI of the monitor U3 is connected with a first output end GPIO1 of the main system circuit; the power supply end of the monitor U3 is connected to a circuit power supply end VCC; the power supply end VCC of the circuit is connected with a capacitor C1, and the other end of the capacitor C1 is grounded.
The capacitance of the capacitor C1 is 100nF, the capacitance of the capacitor C2 is 10uF, the capacitance of the capacitor C3 is 100nF, the capacitance of the capacitor C4 is 1uF, the capacitance of the capacitor C5 is 100nF, the resistance of the resistor R1 is 500 Ω, the resistance of the resistor R2 is 200k Ω, the resistance of the resistor R3 is 100k Ω, and the resistance of the resistor R4 is 100 Ω.
In the embodiment of the invention, when the main system circuit on the electronic equipment is abnormal, the GPIO1 defaults to low level, no watchdog trigger signal is output, and the watchdog cannot be started. At this time, the second output terminal GPIO2 of the main system circuit outputs a low level to the PNP transistor Q1, so that the PNP transistor Q1 is turned on, the timer U2 outputs a pulse trigger signal to the manual reset input terminal/MR of the monitor, and the monitor U3 outputs a reset signal to reset the main system circuit, thereby implementing the reset function of the main system circuit.
In order to prevent the main system circuit from being started normally within a specified time, the timer may be set to continuously send out pulses every other period of time, so that the monitor resets the main system circuit again until the main system circuit is started normally.
When the main system circuit is normally started, the GPIO2 outputs high level, the PNP triode Q1 is cut off, the timer is closed, the GPIO1 outputs a watchdog trigger waveform to start the monitor U3 and output a pulse signal, which can also be called a 'dog feeding' waveform, so that the monitor U3 works normally, and the monitor is normally started to continuously detect the abnormal state of the main system circuit. Specifically, the setting of the oscillation period of the pulse trigger signal sent by the timer is realized by adjusting the capacitor C2, the resistor R1 and the resistor R2, so as to ensure that the main system circuit can be normally started.
For convenience of understanding, how the watchdog realizes the reset function when the main system circuit is normally running and is suddenly abnormal is described, referring to fig. 5a, after the main system circuit is normally started, an input terminal WDI of the watchdog receives a trigger signal, and the trigger signal is the three square waves near the front corresponding to the input terminal WDI of the watchdog. Of course, the first three square waves are only examples of the trigger signal, and the trigger signal may have other waveforms. After the main system circuit outputs the trigger signal, the main system circuit starts to output the pulse signal at intervals, so that the watchdog count is cleared once, if the watchdog still does not receive the pulse signal after exceeding the overflow period twd, at this time, the output end/RESET of the watchdog is changed from high level to low level corresponding to the condition that the input end WDI of the watchdog continues high level or low level, and then the output end/RESET is changed into high level after the delay time td of the watchdog, namely, a RESET signal is output to the main system circuit, so that the main system circuit is restarted, and the RESET function of the watchdog is realized.
In the prior art, if a main system circuit is abnormal when being powered on, such as system crash, program abnormality and the like, a trigger signal cannot be input to a watchdog, the watchdog cannot be started, and a reset function fails. The solution provided by the prior art is that a manual reset pin of a watchdog is connected with a button, and the watchdog outputs a reset signal to reset a main system circuit through pressing and lifting actions, namely, manual reset is performed manually.
However, in actual life, electronic devices are generally checked manually and periodically to determine whether they are abnormal, and if they are abnormal, the electronic devices are manually reset, so that the abnormality of the electronic devices cannot be detected in time, and the electronic devices cannot be restarted in time. For electronic equipment installed at a high place or in some other extreme scenes, such as monitoring equipment, communication equipment and the like, if the monitoring equipment is detected to be abnormal, the electronic equipment cannot work normally, the electronic equipment in other extreme scenes such as the high place and the like needs to be restarted manually by using a shelf or a ladder, a large amount of cost is consumed, and potential safety hazards also exist.
In the embodiment of the invention, the timer is arranged to send the pulse trigger signal to the manual reset pin/MR of the watchdog, so that the watchdog can automatically output the reset signal and reset the main system circuit after the main system circuit is abnormal during power-on, so that the main system circuit can be normally started. When the main system circuit is electrified and abnormal, the switch circuit is conducted, the timer sends out a pulse trigger signal, referring to fig. 5b, after the pulse trigger signal received by the manual RESET input end/MR of the watchdog, the output end/RESET of the watchdog is changed from high level to low level, and when the pulse trigger signal is changed from low level to high level, the output end/RESET is changed into high level after the delay time td of the watchdog, so that the output of a RESET signal is realized, the main system circuit is restarted, and the automatic RESET of the watchdog is realized.
By using the reset circuit provided by the embodiment of the invention, the abnormity of the main system circuit can be detected in time, the main system circuit can be reset and restarted in time, the electronic equipment installed in an extreme scene, such as monitoring equipment, communication equipment and the like, can be monitored in real time, the electronic equipment can be automatically restarted in time, the normal operation of the electronic equipment is ensured, the maintenance cost is reduced, and the potential safety hazard is also reduced.
An embodiment of the present invention further provides an electronic device, referring to fig. 6, where the electronic device shown in fig. 6 includes a main system circuit 10 and a reset circuit 11, and the reset circuit 11 may be any one of the reset circuits described above, where the main system circuit may be an MCU (micro programmed Control Unit), and a specific model of an MCU chip may be selected according to actual requirements. The electronic device may be any electronic device that requires automatic reset, such as a monitoring device, a communication device, etc.
Referring to fig. 7, the monitoring camera shown in fig. 7 includes a camera module 20, a main system circuit 21, and a reset circuit 22, where the reset circuit 22 may be any one of the reset circuits described above.
Referring to fig. 8, the hard disk recorder shown in fig. 8 includes a video recording module 30, a main system circuit 31, and a reset circuit 32, where the reset circuit 32 may be any one of the reset circuits described above.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A reset circuit for an electronic device, the electronic device comprising a main system circuit, the reset circuit comprising: the circuit comprises a watchdog circuit, a switch circuit and a pulse trigger circuit;
the input end of the watchdog circuit is connected with the first output end of the main system circuit, the output end of the watchdog circuit is connected with the reset input end of the main system circuit, and the watchdog circuit is used for starting after receiving a starting signal sent by the main system circuit and sending a reset signal to the reset input end of the main system circuit when monitoring that the main system circuit is abnormal, so that the main system circuit is reset and restarted;
the control end of the switch circuit is connected with the second output end of the main system circuit, the output end of the switch circuit is connected with the input end of the pulse trigger circuit, and the switch circuit is used for conducting under the condition that abnormality occurs when the main system circuit is electrified;
the output end of the pulse trigger circuit is connected with the reset input end of the watchdog circuit and used for outputting a pulse trigger signal to the watchdog circuit under the condition that the switch circuit is switched on, so that the watchdog circuit sends a reset signal to the main system circuit through the output end after receiving the pulse trigger signal.
2. The reset circuit of claim 1, wherein the switching circuit comprises a PNP transistor,
the base electrode of the PNP triode is a control end; when the main system circuit is abnormal during power-on, the second output end outputs low level; the second output end outputs high level under the normal condition of the main system circuit during power-on; when the base electrode of the PNP triode receives a low level, the PNP triode is conducted; when the base electrode of the PNP triode receives a high level, the PNP triode is cut off;
the collector of the PNP triode is connected with a power supply end;
and the emitting electrode of the PNP triode is an output end.
3. The reset circuit of claim 1, wherein the pulse trigger circuit comprises: the circuit comprises a timer, a first resistor, a second resistor and a capacitor;
a first end of the first resistor is connected with an output end of the switch circuit, a second end of the first resistor is connected with a first end of the second resistor and a discharge end of the timer, a second end of the second resistor is connected with a first end of the capacitor, a low trigger end of the timer and a high trigger end of the timer, a second end of the capacitor is grounded, and an output end of the timer is connected with a reset input end of the watchdog circuit;
the oscillation period of the pulse trigger signal is greater than the sum of the delay time of the watchdog circuit and the normal starting time of the main system circuit.
4. The reset circuit of claim 3, wherein the first resistor, the second resistor, and the capacitor;
satisfies the following conditions: 1/f > T + td, f =1.44/[ (R1 +2R 2) × C ];
wherein 1/f is an oscillation period of the pulse trigger signal, f is an oscillation frequency of the pulse trigger signal, T is a time length for normal starting of the main system circuit, td is a time delay time length of the watchdog circuit, R1 is a resistance value of the first resistor, R2 is a resistance value of the second resistor, and C is a capacitance value of the capacitor.
5. An electronic device comprising a main system circuit and a reset circuit as claimed in any one of claims 1 to 4.
6. A surveillance camera comprising a camera module, a main system circuit and a reset circuit as claimed in any one of claims 1 to 4.
7. A digital video recorder comprising a video recording module, a main system circuit and a reset circuit as claimed in any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211688074.XA CN115658376B (en) | 2022-12-28 | 2022-12-28 | Reset circuit, electronic equipment, surveillance camera and digital video recorder |
Applications Claiming Priority (1)
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| CN115658376A (en) | 2023-01-31 |
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