CN115621118A - Method for manufacturing semiconductor product and semiconductor processing equipment - Google Patents
Method for manufacturing semiconductor product and semiconductor processing equipment Download PDFInfo
- Publication number
- CN115621118A CN115621118A CN202211331514.6A CN202211331514A CN115621118A CN 115621118 A CN115621118 A CN 115621118A CN 202211331514 A CN202211331514 A CN 202211331514A CN 115621118 A CN115621118 A CN 115621118A
- Authority
- CN
- China
- Prior art keywords
- etching
- gas
- laminated structure
- etching gas
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 302
- 238000009826 distribution Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 70
- 230000008569 process Effects 0.000 claims description 48
- 238000010438 heat treatment Methods 0.000 claims description 40
- 230000005540 biological transmission Effects 0.000 claims description 31
- 239000000376 reactant Substances 0.000 claims description 28
- 239000003990 capacitor Substances 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 14
- 238000003860 storage Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 9
- 230000005684 electric field Effects 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 9
- 239000007789 gas Substances 0.000 description 210
- 235000012431 wafers Nutrition 0.000 description 15
- 238000009423 ventilation Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/305—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching
- H01J37/3053—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching for evaporating or etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
- H01J37/32449—Gas control, e.g. control of the gas flow
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present disclosure provides a method for manufacturing a semiconductor product and a semiconductor processing apparatus, the method for manufacturing a semiconductor product comprising: providing a substrate; forming a laminated structure on a substrate; and etching the laminated structure by using etching gas with a preset temperature to form etching holes so as to enable the gas distribution quantity of the etching gas with the preset temperature in the central area of the laminated structure and the edge area of the laminated structure to reach a preset proportion. In the method, the laminated structure is etched by using the etching gas with the preset temperature, so that the gas distribution quantity of the etching gas in the central area and the edge area of the laminated structure reaches the preset proportion, the etching gas which accords with the preset proportion distribution quantity has the expected etching effect on the laminated structure, and the performance and the yield of semiconductor products are improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor product and a semiconductor processing apparatus.
Background
In the field of semiconductor technology, etching processes are an important part of semiconductor processes.
The gas inlet assembly is usually arranged above the central area of the wafer, so that the distribution amounts of etching gas in the central area and the edge area of the wafer are different, and the etching uniformity of the etching gas to different areas of the wafer in the same time is not good, for example, short circuit, collapse and other situations occur due to poor etching hole profiles, which affects the performance and yield of semiconductor devices.
Disclosure of Invention
The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
The disclosure provides a manufacturing method of a semiconductor product and semiconductor processing equipment.
In a first aspect of the present disclosure, a method for manufacturing a semiconductor product is provided, the method comprising:
providing a substrate;
forming a stacked structure on the substrate;
and etching the laminated structure by using etching gas with a preset temperature to form etching holes, so that the gas distribution quantity of the etching gas with the preset temperature in the central area of the laminated structure and the edge area of the laminated structure reaches a preset proportion.
In some embodiments, the predetermined temperature of the etching gas is 40 ± 1 ℃;
the gas distribution quantity ratio of the central area to the edge area of the laminated structure is 1.
In some embodiments, the predetermined temperature of the etching gas is separately controlled by a plurality of heating nodes in the delivery line.
In some embodiments, the node temperatures of the plurality of heating nodes are the same or different;
the average value of the node temperatures of the plurality of heating nodes is equal to the preset temperature.
In some embodiments, the heating temperatures of the plurality of heating nodes are respectively selected from any value of 30 ℃ to 45 ℃.
In some embodiments, the etching the stacked structure with an etching gas at a predetermined temperature to form an etching hole further includes:
the etching rate of the central area of the laminated structure is basically the same as that of the edge area;
the deposition rate of the etching protection layer for etching the side wall of the hole in the central area of the laminated structure is basically the same as that of the etching protection layer for etching the side wall of the hole in the edge area of the laminated structure.
In some embodiments, the difference between the inner diameter of the etch hole and the target size is not more than 5% of the target size, the height of the etch hole is greater than 2000nm, and the aspect ratio of the etch hole is greater than 50.
In some embodiments, etching the stacked structure using an etching gas at a predetermined temperature to form an etching hole includes:
a part of the etching gas enters the process chamber in a manner of being vertical to the top surface of the laminated structure so as to etch the central area of the laminated structure;
and the other part of the etching gas and the top surface of the laminated structure form a preset included angle to enter the processing chamber so as to etch the edge area of the laminated structure.
In some embodiments, forming a stacked structure on the substrate comprises:
forming a first stacked structure on the substrate, the first stacked structure including sacrificial layers and support layers that are alternately stacked;
forming a second laminated structure on the first laminated structure, wherein the second laminated structure comprises a pattern transfer layer and a hard mask layer which are arranged in a stacked mode;
before etching the laminated structure by using etching gas with preset temperature to form an etching hole, the manufacturing method comprises the following steps:
patterning the hard mask layer, and removing the exposed hard mask layer;
etching the exposed pattern transfer layer by taking the residual hard mask layer as a mask;
and etching the first laminated structure by using the etching gas and taking the residual pattern transfer layer as a mask to form an etching hole.
In some embodiments, the substrate comprises: the device comprises a word line structure, a bit line structure and a capacitor plug;
the etching hole is arranged corresponding to the capacitor plug and used for forming a lower electrode plate of the capacitor structure.
In some embodiments, the etching gas comprises C 4 F 8 、C 4 F 6 、CH 2 F 2 Any one or more of them.
In a second aspect of the present disclosure, a semiconductor processing apparatus is provided, which includes a gas storage device and a process chamber, and a transmission pipeline communicating the gas storage device and the process chamber;
the gas storage device is used for providing etching gas;
the process chamber is used for introducing etching gas to prepare etching holes in the laminated structure on the surface of the substrate;
the transmission pipeline is used for heating the etching gas to a preset temperature and transmitting the etching gas at the preset temperature to the processing procedure chamber.
In some embodiments, the transfer line includes at least one heating node.
In some embodiments, the temperature of the etching gas in the transmission pipeline is detected, and if the temperature of the etching gas is lower than the preset temperature, the heating node heats the etching gas in the transmission pipeline.
In some embodiments, the process chamber has a plasma electric field therein, the etching gas is ionized by the plasma electric field and then maintained at a predetermined temperature, the etching gas includes a reactant and a non-reactant, the reactant is used for etching the stacked structure, and the non-reactant is used for depositing an etching protection layer on the surface of the sidewall of the etching hole.
According to the manufacturing method of the semiconductor product and the semiconductor processing equipment, the laminated structure is etched by using the etching gas with the preset temperature, so that the gas distribution amount of the etching gas in the central area and the edge area of the laminated structure reaches the preset proportion, the etching gas which accords with the preset proportion distribution amount has the same etching effect on the edge area and the central area of the laminated structure, the uniformity of the obtained etching holes is ensured, and the performance and the yield of the semiconductor product are improved.
Other aspects will be apparent upon reading and understanding the attached figures and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1 is a flow chart illustrating a method of processing a semiconductor product according to an exemplary embodiment.
Fig. 2 is a schematic diagram of a semiconductor product shown in accordance with an example embodiment.
Fig. 3 is a schematic diagram of a semiconductor product shown in accordance with an example embodiment.
Fig. 4 is a schematic diagram of a semiconductor product shown in accordance with an example embodiment.
Fig. 5 is a schematic diagram of a semiconductor product shown in accordance with an example embodiment.
Fig. 6 is a schematic illustration of a semiconductor product shown in accordance with an exemplary embodiment.
Fig. 7 is a schematic diagram of a semiconductor processing apparatus according to an exemplary embodiment.
FIG. 8 is a schematic diagram of a process chamber shown in accordance with one exemplary embodiment.
FIG. 9 is a schematic diagram of a gas cabinet shown in accordance with an exemplary embodiment.
FIG. 10 is a graph illustrating temperature of an etch gas versus etch hole short ratio in a stacked structure, according to an example embodiment.
Reference numerals:
100. a semiconductor product;
10. a substrate; 11. a capacitor plug; 20. a laminated structure; 21. a first stacked structure; 211. a sacrificial layer; 212. a support layer; 22. a second stacked structure; 221. a hard mask layer; 222. a pattern transfer layer; 23. a photoresist layer; 24. etching the hole; 241. etching the protective layer; 20a, a central region; 20b, edge area;
30. a capacitor; 31. an upper polar plate; 32. an insulating layer; 33. a lower polar plate;
200. a gas storage device;
300. a process chamber; 310. an air intake assembly; 311. a main air passage; 312. a first branch airway; 313. a second branch airway; 320. a base; 321. an electrode;
400. a transmission pipeline; 410. a valve distribution box; 420. a transport pipeline; 430. a gas holder; 431. and (4) a ventilation hole.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
In the field of semiconductor technology, etching processes are an important part of semiconductor processes.
The gas inlet assembly is usually arranged above a central area of a wafer, so that the distribution amount of etching gas in the central area and the distribution amount of etching gas in an edge area of the wafer are different, the etching uniformity of the etching gas in different areas of the wafer in the same time is poor, and particularly for capacitor holes with high depth-to-width ratios, the poor profile of the capacitor holes in the edge area is easily caused, so that the conditions of short circuit, collapse and the like are caused, and the performance and the yield of a semiconductor device are influenced.
In order to solve the problem that the gas distribution quantity of etching gas in different areas of a semiconductor product cannot reach a preset proportion, the disclosure provides a manufacturing method of the semiconductor product and semiconductor processing equipment, wherein the manufacturing method of the semiconductor product comprises the following steps: providing a substrate; forming a laminated structure on a substrate; and etching the laminated structure by using etching gas with a preset temperature to form etching holes so as to enable the gas distribution quantity of the etching gas with the preset temperature in the central area of the laminated structure and the edge area of the laminated structure to reach a preset proportion. In the method, the laminated structure is etched by using the etching gas with the preset temperature, so that the gas distribution quantity of the etching gas in the central area and the edge area of the laminated structure reaches the preset proportion, the etching gas which accords with the preset proportion distribution quantity has the expected etching effect on the laminated structure, the sizes of etching holes in different areas of a wafer are uniform, the hole diameter accords with the required size, and the performance and the yield of a semiconductor product are improved.
According to an exemplary embodiment of the present disclosure, as shown in fig. 1, an embodiment of the present disclosure provides a method for manufacturing a semiconductor product, the method for manufacturing the semiconductor product including the steps of:
and step S100, providing a substrate.
In this step, as shown in fig. 2, the base includes a substrate 10 and devices provided in the substrate 10.
Referring to fig. 2, the substrate 10 is made of a material such as Si, ge, siGe, SOI (Silicon On Insulator) or GOI (Germanium On Insulator) or the like. In other embodiments, the substrate 10 may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, inP, siC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like.
Referring to fig. 2, a plurality of active regions (not shown) and a plurality of shallow trench isolation structures (not shown) may be formed in the substrate 10, the plurality of shallow trench isolation structures and the plurality of active regions are alternately arranged, the shallow trench isolation structures separate adjacent active regions, and the plurality of active regions may be doped to form a plurality of independent transistors.
Referring to fig. 2, a word line (word line) structure (not shown) such as a buried word line (buried word line) may also be formed in the substrate 10. A bit line (bit line) structure, a capacitor plug 11, and the like may be further formed in the substrate 10, and a material of the capacitor plug 11 includes a metal such as any one or more of copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), and tantalum (Ta), or a metal nitride such as any one or more of tantalum nitride (TaN) and titanium nitride (TiN). An etching hole 24 (refer to fig. 5) formed in a subsequent process is provided corresponding to the capacitor plug 11.
Step S200, forming a laminated structure on the substrate.
In this step, as shown in fig. 2, a deposition process, an epitaxial growth process, or the like may be used to form the stacked structure 20 on the substrate.
Referring to fig. 2, 5 and 6, the stacked structure 20 has a large height in a vertical direction (a z direction shown in fig. 2), and a capacitor 30 (capacitor) may be formed in the stacked structure 20. For example, the height of some of the stacked structures 20 may even exceed 2000nm, so that etch holes 24 having a height exceeding 2000nm may be formed in the stacked structures 20, and capacitors 30 may be formed in the etch holes 24.
It should be noted that, referring to fig. 6, the capacitors 30 formed in this step may be referred to as vertical capacitors, each of which extends in a vertical direction (z direction shown in fig. 2), and each of which includes an upper plate 31 and a lower plate 33, and an insulating layer 32 disposed between the upper plate 31 and the lower plate 33. The plurality of vertical capacitors are arranged in a horizontal direction (refer to the x direction shown in fig. 2). After the height of the vertical capacitor is increased, the upper plate 31 and the lower plate 33 of the vertical capacitor have larger relative areas, so that the vertical capacitor can store more charges, and the performance of the memory is improved.
Step S300, etching the laminated structure by using etching gas with a preset temperature to form etching holes, so that the gas distribution quantity of the etching gas with the preset temperature in the central area of the laminated structure and the edge area of the laminated structure reaches a preset proportion.
In this step, the etching gas may be C 4 F 8 、C 4 F 6 、CH 2 F 2 The etching gas is ionized in the process chamber 300 (see fig. 7) to form a reactant for etching the stacked structure 20 to form the etching hole 24, such as fluorine plasma, and a non-reactant for depositing on the sidewall surface of the etching hole 24 to form the etching protection layer 241, such as carbon-containing polymer.
It should be noted that gases with different temperatures have different kinetic energies, for example, a high-temperature gas has a high kinetic energy, and a gas with a high kinetic energy is easier to diffuse. Therefore, the temperature of the etching gas is adjusted to a preset temperature, so that the etching gas has a preset kinetic energy, and the diffusion range of the etching gas is controlled, so that the gas distribution amount of the etching gas in the central region and the edge region of the laminated structure can reach a preset ratio (for example, the gas distribution amount in the central region and the edge region is 1. The ratio of the amount of the etching gas in the central region and the edge region of the stacked structure is not limited thereto, and the predetermined ratio may be any value from 1.
Referring to fig. 8, the central region 20a of the stacked structure 20 is a region of the stacked structure 20 close to the wafer axis L3, and the edge region 20b of the stacked structure 20 is a region of the stacked structure 20 away from the wafer axis L3. Wherein, the center area takes the center of the wafer as the center of the area, and the area of the center area is 1/2-1/3 of the area of the wafer.
In order to determine the preset temperature of the etching gas, the short-circuit proportion of the etching holes of the edge region and the central region at a plurality of temperatures is measured and recorded, and the temperature when the short-circuit proportion of the etching holes of the edge region and the central region is consistent is determined to be the preset temperature of the etching gas, and the obtained result is shown in fig. 10, which shows a schematic diagram of the relationship between the temperature of the etching gas and the short-circuit proportion of the etching holes, wherein the abscissa represents the temperature (unit:. Degree. C.) of the etching gas, the ordinate represents the short-circuit proportion (unit:%) of the etching holes in the laminated structure, L4 is a fitting curve of the short-circuit proportion of the etching holes in the central region changing with the temperature of the etching gas, and L5 is a fitting curve of the short-circuit proportion of the etching holes in the edge region changing with the temperature of the etching gas. As can be seen from fig. 10, when the temperature of the etching gas is 30 ℃, the short-circuiting ratio of the etching holes in the central region is about 8%, the short-circuiting ratio of the etching holes in the edge region is about 20%, and when the temperature of the etching gas is increased to 50 ℃, the short-circuiting ratio of the etching holes in the central region is about 18%, and the short-circuiting ratio of the etching holes in the edge region is about 10%.
According to the change curve of the etching hole short-circuit proportion at multiple temperatures, the etching hole short-circuit proportion of the central area is gradually increased along with the increase of the temperature, the etching hole short-circuit proportion of the edge area is gradually decreased along with the increase of the temperature, and when the temperature is about 40 ℃, the etching hole short-circuit proportion of the central area and the etching hole short-circuit proportion of the edge area of the laminated structure are the same, namely the etching effect of each area on the laminated structure is the same.
By controlling the preset temperature of the etching gas within the range of 40 +/-1 ℃, the gas distribution amount of the etching gas in the central region 20a and the edge region 20b of the laminated structure is 1-1.2, the desired etching effect can be achieved, for example, an etching hole 24 with the height exceeding 2000nm and the height-to-depth ratio exceeding 50 can be manufactured, and the difference between the inner diameter of the etching hole 24 and the target size is not more than 5% of the target size.
It should be noted that the temperature of the wafer processing plant (i.e., room temperature, such as 23 ℃) is usually lower than the preset temperature of the etching gas, so that when the etching gas is transported in the transport pipe 400 (described in detail later), heat exchange exists between the inside and the outside of the transport pipe 400, which causes the temperature of the etching gas to decrease and thus the etching gas cannot reach the preset temperature. Therefore, a temperature sensing unit can be disposed on the transmission pipeline 400 to detect the temperature of the etching gas, and a heating device is disposed to raise the temperature of the etching gas, so that the etching gas reaches a preset temperature, and the gas distribution amount in different regions of the laminated structure reaches a preset proportion. In some possible cases, the temperature of the etching gas may far exceed 40 ℃, and in this case, the temperature of the transmission pipeline may be reduced, so as to avoid an increase in short-circuit ratio of the etching hole in the central region due to an excessively high temperature of the etching gas, and the temperature reduction may accelerate the flow speed of the low-temperature gas near the transmission pipeline 400.
In the embodiment of the disclosure, the laminated structure is etched by using the etching gas with the preset temperature, so that the gas distribution amounts of the etching gas in the central area and the edge area of the laminated structure reach the preset proportion, the etching gas which accords with the preset proportion distribution amount has an expected etching effect on the laminated structure, and the performance and the yield of a semiconductor product are improved.
In an exemplary embodiment, this embodiment is further described with respect to step S300 in the above embodiment, and when etching the stacked structure by using the etching gas with the preset temperature, controlling the temperature of the etching gas at the preset temperature may include the following steps:
step S310, the preset temperature of the etching gas is respectively controlled through a plurality of heating nodes in the transmission pipeline.
In this step, as shown in fig. 7, a plurality of heating nodes may be arranged according to the gas transmission direction, and the plurality of heating nodes are arranged to heat the etching gas, so that the temperature of the etching gas at each position in the transmission pipeline is close to that of the etching gas at different positions in the transmission pipeline, and thus the etching gas at different positions in the transmission pipeline has temperature consistency, which ensures the stability of gas flow in the transmission process, and avoids the over-high or over-low temperature, and the large gas flow fluctuation during heat exchange is very easy to cause explosion danger in a narrow space.
In one example, as shown in fig. 7, a Valve distribution Box 410 (VMB), a transport pipeline 420, a GAS Box 430 (GAS Box), etc. may be disposed on the transport pipeline 400, and heating nodes may be disposed in the Valve distribution Box 410, the transport pipeline 420, and the GAS Box 430, respectively. The valve distribution box 410 is used for distributing gas, and the gas holder 430 can monitor and control the gas flow, pressure and the like in the transmission pipeline 400.
In one embodiment, as shown in FIG. 7, the temperatures of the plurality of heating nodes may be the same or different.
When the temperatures of the plurality of heating nodes are the same, the temperature of each heating node needs to be maintained within 40 + -1 deg.C, so that the temperature of the etching gas entering the process chamber 300 is within 40 + -1 deg.C.
When the temperatures of the plurality of heating nodes are different, the temperature of each heating node can be any value between 30 ℃ and 45 ℃, and the average value of the temperatures of the plurality of heating nodes is equal to the preset temperature. For example, when the node temperature at the valve distribution box 410 is 35 ℃, the node temperature of the gas holder 430 may be 45 ℃, and when the node temperature at the valve distribution box 410 is 45 ℃, the node temperature of the gas holder 430 may be 35 ℃, so that the etching gas may reach a predetermined temperature (40 ± 1 ℃) when entering the process chamber 300.
In an exemplary embodiment, the present embodiment is further described with respect to step S300 in the foregoing embodiment, and the etching the stacked structure with an etching gas at a predetermined temperature to form an etching hole may include the following steps:
step S320, the etching rate of the central region of the stacked structure is substantially the same as the etching rate of the edge region.
In this step, as shown in fig. 8, after the etching gas is introduced into the process chamber 300, the etching gas is ionized in the process chamber 300 to form a reactant, such as Plasma (Plasma), which can etch the stacked structure 20 to form the etching holes 24 (see fig. 7).
By controlling the temperature of the etching gas, the gas distribution amounts of the etching gas in the central region 20a and the edge region 20b of the stacked structure 20 reach a preset ratio (such as 1.
The etching gas with the same gas distribution amount also has the same etching rate in the horizontal direction (the x direction shown in fig. 8), so that the etching degree of the reactant on the side wall of the etching hole 24 is the same, and the phenomenon that the reactant excessively etches the side wall of the etching hole 24 to cause the short circuit of the adjacent etching hole 24 with too large hole diameter is avoided. Step S330, the deposition rate of the etching protection layer for etching the side wall of the hole in the central area of the laminated structure is basically the same as that of the etching protection layer for etching the side wall of the hole in the edge area of the laminated structure.
In this step, as shown in FIG. 8, after the etching gas is introduced into the process chamber 300, the etching gas is ionized in the process chamber 300 to form a non-reactant, such as a carbon-containing Polymer (Polymer), for depositing an etching protection layer 241 on the sidewall surface of the etching hole 24.
The non-reactant generated by the etching gas with the same gas distribution amount is equal, so that the deposition rate of the non-reactant on the sidewall of the etching hole 24 is the same, the etching protection layer 241 with the same thickness (shown in the x direction in fig. 2) can be generated, the protection effect of the etching protection layer 241 with the same thickness on the etching hole 24 is the same, the reactant is prevented from further etching the sidewall of the etching hole 24, and the regular etching hole can be formed finally.
For a single via 24, the non-reactant sidewall deposition rate and the reactant etch rate together constitute the etch rate of the etch gas during etching, and the non-reactant sidewall deposition rate may be lower than the reactant etch rate. If the etching gas stays at one position of the etching hole 24 for a long time, the reactant reacts with the sidewall of the etching hole 24 quickly, and the carbon-containing polymer cannot form a protective layer with a sufficient area on the sidewall surface of the etching hole 24, so that the aperture of the etching hole 24 at the position exceeds the target size, and finally, the adjacent etching hole 24 is short-circuited at the position. According to the scheme, the temperature of the introduced etching gas is increased, and the etching gas diffused in the edge region and the etching gas diffused in the central region have basically the same temperature, so that the etching gas at each position on the surface of the wafer has enough kinetic energy to penetrate into the bottom of the etching hole 24, the etching gas can be further diffused downwards in the vertical direction (the z direction shown in fig. 2) to react with the residual laminated structure at the bottom of the etching hole 24, and the etching gas is prevented from staying at a certain position of the etching hole 24 along with the increase of the depth of the etching hole 24. Meanwhile, in the etching process, the carbon-containing polymer can be uniformly deposited on the side wall of the etching hole 24 along with the penetration of etching gas, so that the same etching rates of the upper end and the lower end of the laminated structure are ensured, the problems of undersize of the bottom aperture of the etching hole 24, oversize of the middle aperture and the like are avoided, the profile of the etching hole 24 is more uniform, and the profile of the etching hole 24 in the edge region and the middle new region of the wafer is basically consistent.
In an exemplary embodiment, the present embodiment is further described with respect to step S300 in the foregoing embodiment, and the etching the stacked structure with an etching gas at a predetermined temperature to form an etching hole may include the following steps:
in step S340, a portion of the etching gas enters the process chamber perpendicular to the top surface of the stacked structure to etch the central region of the stacked structure.
Step S350, the other part of the etching gas enters the process chamber at a predetermined included angle with the top surface of the stacked structure to etch the edge region of the stacked structure.
In this step, referring to fig. 8, which is a schematic cross-sectional view of the process chamber 300, the process chamber 300 is provided with a gas inlet assembly 310, the gas inlet assembly 310 communicates with the external space and the internal space of the process chamber 300, the gas inlet assembly 310 communicates with the transfer pipe 400, and the etching gas in the transfer pipe 400 can enter the process chamber 300 through the gas inlet assembly 310. Wherein the air intake assembly 310 is generally disposed directly above the central region 20a of the laminate structure 20.
Referring to fig. 7 and 8, the gas inlet assembly 310 includes a main gas passage 311 and a plurality of branch gas passages communicated with the main gas passage 311, the main gas passage 311 is communicated with the delivery pipe, and different branch gas passages can deliver etching gas to the laminated structure at different angles to etch different regions of the laminated structure. For example, referring to fig. 8, the first branch gas channel 312 is perpendicular to the top surface of the stacked structure 20, so that the etching gas in the first branch gas channel 312 can enter the process chamber (refer to L1 shown in fig. 8) perpendicular to the top surface of the stacked structure to etch the central region 20a of the stacked structure 20. For another example, the second branch gas channel 313 is obliquely disposed and a plurality of branch gas channels are disposed around the first branch gas channel 312, so that the etching gas in the second branch gas channel 313 can enter the process chamber 300 at a predetermined angle with respect to the top surface of the stacked structure 20, and thus the etching gas can move to the edge region 20b (refer to L2 shown in fig. 8) of the stacked structure 20.
In an exemplary embodiment, the present embodiment is further described with respect to step S200 in the above embodiment, and the forming of the stacked structure on the substrate may include the following steps:
step S210, a first stacked structure is formed on a substrate, where the first stacked structure includes sacrificial layers and support layers that are alternately stacked.
In this step, as shown in fig. 2, a first stacked structure 21 may be formed on the top surface of the substrate by deposition, epitaxial growth, or the like, where the first stacked structure 21 includes sacrificial layers 211 and a support layer 212 that are alternately stacked, the material of the support layer 212 is, for example, siN, and the material of the sacrificial layer 211 may be an oxide.
Step S220, a second stacked structure is formed on the first stacked structure, and the second stacked structure includes a pattern transfer layer and a hard mask layer which are stacked.
In this step, as shown in fig. 2, a second stacked structure 22 may be formed on the top surface of the first stacked structure 21 by deposition, epitaxial growth, or the like, where the second stacked structure 22 includes a pattern transfer layer 222 and a hard mask layer 221 stacked together, and the pattern transfer layer 222 is made of a material such as silicon dioxide.
Step S230, patterning the hard mask layer, and removing the exposed hard mask layer.
In this step, as shown in fig. 2 and 3, a photoresist layer 23 may be formed on the hard mask layer, the photoresist layer 23 covers a part of the top surface of the hard mask layer, and the photoresist layer 23 is used as a mask to remove the exposed region of the hard mask layer 221 by an etching process, so as to expose the to-be-etched region of the pattern transfer layer 222.
And step S240, etching the exposed pattern transfer layer by taking the residual hard mask layer as a mask.
In this step, as shown in fig. 3 and 4, after removing a portion of the hard mask layer 221, a portion of the top surface of the pattern transfer layer 222 is exposed, and an etching process may be used to remove the exposed pattern transfer layer 222, so as to form an initial etching hole in the pattern transfer layer 222.
It will be appreciated that the height (z direction shown in fig. 2) of the pattern-transfer layer is low, so that regular initial etch holes can be formed in the pattern-transfer layer, such as uniform depth, uniform aperture size, vertical sidewalls, uniform hole-to-hole spacing thickness, and the like.
And step S250, etching the first laminated structure by using etching gas and taking the residual pattern transfer layer as a mask to form an etching hole.
In this step, as shown in fig. 4 and fig. 5, after removing part of the pattern transfer layer 222, part of the top surface of the first stacked structure 21 is exposed, and part of the structure of the first stacked structure 21 is removed by using the remaining pattern transfer layer 222 as a mask, so as to form an etching hole 24 in the first stacked structure 21, where the etching hole 24 is used to form the lower plate 33 of the capacitor structure.
It can be understood that regular etching holes are formed in the pattern transfer layer, and the pattern transfer layer is used as a mask to ensure that etching holes with perfect contours are formed in the first laminated structure and the exposed laminated structures have the same size, so that the performance and yield of the manufactured semiconductor product are improved.
It should be noted that steps S210 to S250 are executed before step S300.
According to an exemplary embodiment of the present disclosure, as illustrated in fig. 7 to 9, an embodiment of the present disclosure provides a semiconductor processing apparatus including a gas storage device 200, a process chamber 300, and a transfer line 400.
In this embodiment, as shown in FIG. 7, the gas storage device 200 is used to store an etching gas, such as C 4 F 8 、C 4 F 6 、CH 2 F 2 Any one or more of them.
In the present embodiment, as shown in fig. 7 and 8, the process chamber 300 is used for processing semiconductor products (e.g., wafers), such as deposition, photolithography, etching, and the like. The process chamber 300 of the present embodiment may be used to etch the semiconductor product 100 to form the etching hole 24 (see fig. 5), and the capacitor 30 may be formed in the etching hole 24 (see fig. 6).
In the embodiment, as shown in fig. 7, the transmission pipeline 400 is connected to the gas storage device 200 and the process chamber 300, and the etching gas in the gas storage device 200 can be transmitted to the process chamber 300 through the transmission pipeline 400 to etch the semiconductor product 100 in the process chamber 300.
Referring to fig. 7, the transmission pipeline 400 includes a Valve distribution Box 410 (VMB, valve modified Box), a transmission pipeline 420, a GAS tank 430 (GAS Box), and the like, and the Valve distribution Box 410, the transmission pipeline 420, and the GAS tank 430 are sequentially disposed in a transmission direction of the etching GAS. The valve distribution box 410 is connected to the gas storage device 200, the valve distribution box 410 is capable of controlling the delivery direction of the etching gas, the gas holder 430 is connected to the process chamber 300, and the gas holder 430 is capable of controlling the flow of the gas. Wherein the valve distribution box 410, the transmission pipeline 420 and the gas holder 430 have a function of heating the etching gas.
In the embodiment of the disclosure, the transmission pipeline can heat the etching gas to the preset temperature, when the etching gas with the preset temperature is used for etching the laminated structure, the gas distribution amount of the etching gas in the central area and the edge area of the laminated structure reaches the preset proportion, the etching gas which accords with the preset proportion distribution amount has the expected etching effect on the laminated structure, and the performance and the yield of a semiconductor product are improved.
In one embodiment, as shown in FIG. 7, the transfer line 400 includes at least one heating node therein at which the etching gas in the transfer line 400 can be heated such that the etching gas reaches a predetermined temperature. Heating nodes may be located, for example, in the valve distribution box 410, the transfer piping 420, and the gas cabinet 430.
When a plurality of heating nodes are provided, the node temperatures of the plurality of heating nodes may be the same or different. When the temperatures of a plurality of heating nodes are the same, the temperature of each heating node needs to be guaranteed to be within 40 +/-1 ℃. When the temperatures of the plurality of heating nodes are different, the temperature of each heating node can be any value between 30 ℃ and 45 ℃, and the average value of the temperatures of the plurality of heating nodes is equal to the preset temperature.
It can be understood that the transmission pipeline 400 of the etching gas is generally long, so that the etching gas has heat loss in the transmission process, therefore, temperature sensors and heating units (such as heating wires) can be arranged at different positions of the transmission pipeline, the temperature sensors can monitor the temperature of the etching gas, the average temperature of different positions in the transmission pipeline is calculated, and the heating units are controlled to control the temperature of the transmission pipeline according to the average temperature, so that the etching gas is in the preset temperature range.
In an alternative embodiment, as shown in fig. 7 and 9, a plurality of ventilation holes 431 are generally formed in the gas holder 430, and when the number of the ventilation holes 431 is large, room temperature gas entering the gas holder 430 through the ventilation holes 431 is increased, so that interference is generated on the etching gas, the temperature of the etching gas fluctuates, and the temperature cannot be stabilized within a preset temperature range, thereby affecting the etching effect. In this embodiment, as shown in fig. 9, the number of the ventilation holes 431 may be reduced to reduce the interference of the room temperature gas, and the number of the ventilation holes 431 may be reduced by, for example, plugging the ventilation holes with an adhesive tape. When the partial ventilation holes 431 are blocked, the lower ventilation holes 431 may be selected to be blocked preferentially (see the a region shown in fig. 9). It will be appreciated that the process of reducing the number of transfer ports may be performed in other equipment where transfer lines 400 have transfer ports, such as transfer lines 420.
In one embodiment, as shown in FIG. 8, the process chamber 300 includes a gas inlet assembly 310, the gas inlet assembly 310 includes a main gas passage 311 and a plurality of branch gas passages communicating with the main gas passage 311, the main gas passage 311 communicates with a delivery conduit 400 (see FIG. 7), and different branch gas passages can deliver etching gas to the stack 20 at different angles so that the etching gas reaches different regions of the stack 20 to etch different regions of the stack 20. For example, the first branch gas channel 312 is perpendicular to the top surface of the stacked structure 20, so that the etching gas in the first branch gas channel 312 can enter the process chamber perpendicular to the top surface of the stacked structure 20 to etch the central region 20a of the stacked structure 20. For another example, the second branch gas channel 313 is disposed obliquely, so that the etching gas in the second branch gas channel 313 can enter the process chamber 300 at a predetermined angle with respect to the top surface of the stacked structure 20, and thus the etching gas can move to the edge region 20b of the stacked structure 20.
In one embodiment, as shown in FIG. 8, the process chamber 300 further includes a pedestal 320, the pedestal 320 having an electrode 321 embedded therein, the pedestal 320 supporting the semiconductor product 100, the electrode 321 in the pedestal 320 being capable of generating a plasma electric field to plasma process the etching gas in the process chamber 300.
The etching gas is still at a preset temperature after being ionized by the plasma electric field, the etching gas comprises reactants and non-reactants, the reactants are used for etching the laminated structure and forming an etching hole in the laminated structure, the reactants are plasma, the non-reactants are used for depositing on the side wall surface of the etching hole to form an etching protection layer, the non-reactants are polymer, and the etching protection layer can prevent the plasma from excessively etching the side wall of the etching hole so as to prevent the diameter of the etching hole from being too large and short-circuit from occurring.
The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the description herein, references to the description of the terms "embodiment," "exemplary embodiment," "some embodiments," "exemplary embodiment," "example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure.
In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus, should not be construed as limiting the present disclosure.
It will be understood that, as used in this disclosure, the terms "first," "second," etc. may be used in this disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
Like elements in one or more of the drawings are represented by like reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Numerous specific details of the present disclosure, such as structures, materials, dimensions, processing techniques and techniques of the devices, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.
Claims (15)
1. A method of fabricating a semiconductor product, the method comprising:
providing a substrate;
forming a stacked structure on the substrate;
and etching the laminated structure by using etching gas with a preset temperature to form etching holes so as to enable the gas distribution quantity of the etching gas with the preset temperature in the central area of the laminated structure and the edge area of the laminated structure to reach a preset proportion.
2. The method of claim 1, wherein the predetermined temperature of the etching gas is 40 ± 1 ℃;
the gas distribution quantity ratio of the central area to the edge area of the laminated structure is 1-1.
3. A method of manufacturing a semiconductor product according to claim 2, wherein the predetermined temperature of the etching gas is controlled individually by a plurality of heating nodes in the transfer line.
4. A method of manufacturing a semiconductor product according to claim 3, wherein the node temperatures of the plurality of heating nodes are the same or different;
the average value of the node temperatures of the plurality of heating nodes is equal to the preset temperature.
5. The method of claim 4, wherein the heating temperatures of the plurality of heating nodes are selected from any value of 30 ℃ to 45 ℃.
6. The method of claim 1, wherein the etching the stacked structure with an etching gas at a predetermined temperature to form an etching hole further comprises:
the etching rate of the central area of the laminated structure is basically the same as that of the edge area;
the deposition rate of the etching protective layer for etching the side wall of the hole in the central area of the laminated structure is basically the same as that of the etching protective layer for etching the side wall of the hole in the edge area of the laminated structure.
7. The method as claimed in claim 1, wherein the difference between the inner diameter of the via and the target dimension is no more than 5% of the target dimension, the height of the via is greater than 2000nm, and the aspect ratio of the via is greater than 50.
8. The method for manufacturing a semiconductor product according to claim 1, wherein the step of forming the etching hole by etching the laminated structure using an etching gas having a predetermined temperature comprises:
a part of the etching gas enters the process chamber in a manner of being vertical to the top surface of the laminated structure so as to etch the central area of the laminated structure;
and the other part of the etching gas and the top surface of the laminated structure form a preset included angle to enter the processing chamber so as to etch the edge area of the laminated structure.
9. A method of fabricating a semiconductor product according to claim 1, wherein forming a stacked structure on the substrate comprises:
forming a first stacked structure on the substrate, the first stacked structure including sacrificial layers and support layers alternately stacked;
forming a second laminated structure on the first laminated structure, wherein the second laminated structure comprises a pattern transfer layer and a hard mask layer which are arranged in a stacked mode;
before etching the laminated structure by using etching gas with preset temperature to form an etching hole, the manufacturing method comprises the following steps:
patterning the hard mask layer, and removing the exposed hard mask layer;
etching the exposed pattern transfer layer by taking the residual hard mask layer as a mask;
and etching the first laminated structure by using the etching gas and taking the residual pattern transfer layer as a mask to form an etching hole.
10. A method of fabricating a semiconductor product according to claim 1, wherein the substrate comprises: the memory comprises a word line structure, a bit line structure and a capacitor plug;
the etching hole is arranged corresponding to the capacitor plug and used for forming a lower electrode plate of the capacitor structure.
11. A method of manufacturing a semiconductor product according to claim 1, wherein the etching gas comprises C 4 F 8 、C 4 F 6 、CH 2 F 2 Any one or more of them.
12. The semiconductor processing equipment is characterized by comprising a gas storage device, a processing chamber and a transmission pipeline, wherein the transmission pipeline is communicated with the gas storage device and the processing chamber;
the gas storage device is used for providing etching gas;
the process chamber is used for introducing etching gas to prepare etching holes in the laminated structure on the surface of the substrate;
the transmission pipeline is used for heating the etching gas to a preset temperature and transmitting the etching gas at the preset temperature to the processing procedure chamber.
13. The semiconductor processing apparatus of claim 12, wherein the transfer line includes at least one heating node.
14. The semiconductor processing apparatus of claim 13, wherein the temperature of the etching gas in the transport line is detected, and the heating node heats the etching gas in the transport line if the temperature of the etching gas is lower than the predetermined temperature.
15. The semiconductor processing apparatus of claim 12, wherein the process chamber has a plasma electric field therein, the etching gas is ionized by the plasma electric field and maintained at a predetermined temperature, the etching gas comprises a reactant and a non-reactant, the reactant is used for etching the stacked structure, and the non-reactant is used for depositing an etching protection layer on the sidewall surface of the etching hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211331514.6A CN115621118A (en) | 2022-10-28 | 2022-10-28 | Method for manufacturing semiconductor product and semiconductor processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211331514.6A CN115621118A (en) | 2022-10-28 | 2022-10-28 | Method for manufacturing semiconductor product and semiconductor processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115621118A true CN115621118A (en) | 2023-01-17 |
Family
ID=84875787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211331514.6A Pending CN115621118A (en) | 2022-10-28 | 2022-10-28 | Method for manufacturing semiconductor product and semiconductor processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115621118A (en) |
-
2022
- 2022-10-28 CN CN202211331514.6A patent/CN115621118A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11621277B2 (en) | Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof | |
| US10468267B2 (en) | Water-free etching methods | |
| US10325923B2 (en) | Accommodating imperfectly aligned memory holes | |
| US9406683B2 (en) | Wet bottling process for small diameter deep trench capacitors | |
| CN111549333B (en) | Thin film deposition apparatus and method of manufacturing 3D memory device | |
| US10658377B2 (en) | Three-dimensional memory device with reduced etch damage to memory films and methods of making the same | |
| US10847376B2 (en) | In-situ deposition and etch process and apparatus for precision patterning of semiconductor devices | |
| US20070264842A1 (en) | Insulation film deposition method for a semiconductor device | |
| KR20180117714A (en) | Methods for gap filling in high aspect ratio structures | |
| US20160276267A1 (en) | Methods of forming wiring structures in a semiconductor device | |
| US20120049262A1 (en) | A dram cell structure with extended trench and a manufacturing method thereof | |
| WO2021015895A1 (en) | Vertical transistor fabrication for memory applications | |
| KR102152706B1 (en) | Layer deposition systems and methods of forming conductive patterns using the same | |
| CN115621118A (en) | Method for manufacturing semiconductor product and semiconductor processing equipment | |
| US9812354B2 (en) | Process of forming an electronic device including a material defining a void | |
| US7402487B2 (en) | Process for fabricating a semiconductor device having deep trench structures | |
| JP4322150B2 (en) | Manufacturing method of semiconductor device | |
| US20220127718A1 (en) | Hdp sacrificial carbon gapfill | |
| KR100524800B1 (en) | Method for making contact plug having double doping distribution in semiconductor device | |
| US20240090213A1 (en) | Sacrificial layer for forming merged high aspect ratio contacts in 3d nand memory device | |
| US20070197034A1 (en) | Semiconductor device having a sac through-hole | |
| US6204127B1 (en) | Method of manufacturing bit lines in memory | |
| US7855113B2 (en) | Method for fabricating semiconductor memory device | |
| CN112951834A (en) | Three-dimensional memory and preparation method thereof | |
| CN114068546A (en) | Semiconductor structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |