CN115620761A

CN115620761A - Sense amplifier, memory and operating method thereof

Info

Publication number: CN115620761A
Application number: CN202211293458.1A
Authority: CN
Inventors: 罗怡菲
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2023-01-17

Abstract

The embodiment of the disclosure discloses a sensitive amplifier, a memory and an operation method thereof, wherein the sensitive amplifier comprises: the amplification module and the power supply module; the amplifying module is used for amplifying the voltage difference between the bit line and the complementary bit line under the drive of the voltage provided by the power supply module; the power supply module comprises a pull-up driving unit, the pull-up driving unit is connected with a first voltage end of the amplification module and used for providing a first pull-up voltage and a second pull-up voltage for the amplification module in a sensing stage time sharing mode, and the first pull-up voltage is smaller than the second pull-up voltage.

Description

Sense amplifier, memory and operating method thereof

Technical Field

The disclosed embodiments relate to the field of semiconductor technology, and relate to, but are not limited to, a sense amplifier, a memory, and an operating method thereof.

Background

With the popularization of electronic devices such as mobile phones, tablet computers, and personal computers, semiconductor memory technology has also been rapidly developed. Such as DRAM (Dynamic Random Access Memory), has been widely used in various electronic devices due to its advantages of high density, low power consumption, low price, etc.

A Sense Amplifier (SA) is an important component of a semiconductor memory, and mainly plays a role of amplifying a small signal on a bit line to perform a read or write operation.

The sensing (Sense) speed and the Write-back (Restore)/Write-back (Write Recovery) speed of the Sense amplifier are used as an important index for evaluating the performance of the Sense amplifier, and the application scenario of the memory is directly influenced. How to increase the sensing speed and the write-back/write-in speed of the sense amplifier becomes a problem to be solved urgently.

Disclosure of Invention

Embodiments of the present disclosure provide a sense amplifier, a memory and an operating method of the memory.

In a first aspect, an embodiment of the present disclosure provides a sense amplifier, including: the amplification module and the power supply module;

the amplifying module is used for amplifying the voltage difference between the bit line and the complementary bit line under the drive of the voltage provided by the power supply module;

the power supply module comprises a pull-up driving unit, the pull-up driving unit is connected with a first voltage end of the amplification module and used for providing a first pull-up voltage and a second pull-up voltage for the amplification module in a sensing stage time sharing mode, and the first pull-up voltage is smaller than the second pull-up voltage.

In some embodiments, the power module includes a control unit for providing a control signal to the pull-up driving unit;

the pull-up driving unit comprises a first voltage source input end, a second voltage source input end and a control end, and is used for providing the first pull-up voltage to the amplification module based on the first voltage source according to the control signal in a first preset time period of a sensing stage, and providing the second pull-up voltage to the amplification module based on the first voltage source and the second voltage source according to the control signal in a second preset time period of the sensing stage;

the first voltage source supply voltage is less than the second voltage source supply voltage.

In some embodiments, the sense amplifier further comprises a column selection module, configured to transmit data on the bit lines to a data output terminal in a read operation and transmit input data on a data input terminal to the bit lines in a write operation under the control of a column selection signal;

the pull-up driving unit is used for providing the second pull-up voltage to the amplifying module based on the first voltage source and the second voltage source according to the control signal within a third preset time period; the third preset time period is from a first preset time when the column selection signal is at an active level to a second preset time after the column selection signal is inverted to an inactive level.

In some embodiments, the control unit comprises a first control signal output and a second control signal output;

the pull-up driving unit includes a first transistor and a second transistor; the first transistor is connected between the first voltage source input end and the second voltage source input end, and the control end of the first transistor is connected with the output end of the first control signal; the second transistor is connected between the second voltage source input end and the first voltage end of the amplification module, and the control end of the second transistor is connected with the second control signal output end;

the control unit outputs a first voltage through the first control signal output end in the first preset time period of the sensing stage so as to enable the first transistor to be closed, and outputs a second voltage through the second control signal output end so as to enable the second transistor to be conducted; the control unit outputs a third voltage through the first control signal output end in the second preset time period of the sensing stage so as to enable the first transistor to be conducted, and outputs a fourth voltage through the second control signal output end so as to enable the second transistor to be conducted.

In some embodiments, during the third preset time period, a third voltage is output through the first control signal output terminal to turn on the first transistor, and a second voltage is output through the second control signal output terminal to turn on the second transistor.

In some embodiments, the first transistor and the second transistor are both P-type transistors.

In some embodiments, the control unit includes an activate command input, a first control signal generating circuit and a second control signal generating circuit;

the first control signal generating circuit comprises a first inverter, a first NOR gate, a second inverter, an AND gate and a second NOR gate;

the input end of the first inverter is connected with the activation command input end, and the output end of the first inverter is connected with the first input end of the first NOR gate;

a second input of the first NOR gate is connected to the activate command input, and an output of the first NOR gate is connected to a first input of the second NOR gate;

the input end of the second inverter is connected with the second control signal output end, and the output end of the second inverter is connected with the first input end of the AND gate;

the second input end of the AND gate is connected with the second control signal output end, and the output end of the AND gate is connected with the second input end of the second NOR gate;

the output end of the second NOR gate is connected with the first control signal output end;

the second control signal generating circuit comprises a delay circuit connected between the activation command input terminal and the second control signal output terminal; the delay circuit has a first delay time.

In some embodiments, the first inverter has a second delay time and the second inverter has a third delay time.

In a second aspect, embodiments of the present disclosure provide a memory including a sense amplifier as described in any one of the above embodiments.

In a second aspect, embodiments of the present disclosure provide a method of operating a memory, the memory including the sense amplifier of claim 1; the method comprises the following steps: in a sensing phase of a reading operation and/or a writing operation, the pull-up driving unit supplies a first pull-up voltage and a second pull-up voltage to the amplifying module in a time sharing mode, and the first pull-up voltage is smaller than the second pull-up voltage.

In some embodiments, the power module includes a control unit for providing a control signal to the pull-up driving unit; the pull-up driving unit comprises a first voltage source input end, a second voltage source input end and a control end; the sensitive amplifier also comprises a column selection module, a data output end and a data output end, wherein the column selection module is used for transmitting data on the bit line to the data output end in the read operation under the control of a column selection signal; the time-sharing supplying of the first pull-up voltage and the second pull-up voltage to the amplifying module by the pull-up driving unit in the sensing phase of the read operation and/or the write operation includes: the first pull-up voltage is provided to the amplification module based on a first voltage source according to the control signal for a first preset time period of a sensing phase of the read or write operation, and the second pull-up voltage is provided to the amplification module based on the first voltage source and the second voltage source according to the control signal for a second preset time period of the sensing phase.

In some embodiments, the method further comprises:

providing the second pull-up voltage to the amplifying module based on the first voltage source and the second voltage source according to the control signal within a third preset time period of a write-back stage of the read operation and/or a write-in stage of the write operation; the third preset time period is from a first preset time when the column selection signal is at an active level to a second preset time after the column selection signal is inverted to an inactive level;

In some embodiments, the third preset time period is 5ns.

the control unit generates a first control signal and a second control signal according to an activation command during a sensing phase of the read operation and/or the write operation.

In some embodiments, the first transistor and the second transistor are both P-type transistors; the control unit comprises an activation command input end, a first control signal generation circuit and a second control signal generation circuit;

the input end of the first phase inverter is connected with the activation command input end, and the input end of the first phase inverter is connected with the first input end of the first NOR gate;

the second control signal generating circuit comprises a delay circuit connected between the activation command input terminal and the second control signal output terminal;

the first inverter has a second delay time and the second inverter has a third delay time.

In some embodiments, the second preset time period is 2ns.

The pull-up driving unit in the embodiment of the present disclosure may provide at least two voltages different from the GND voltage to the first voltage terminal PCS of the amplification block. The first pull-up voltage VBLH is smaller than the second pull-up voltage VCC, and when the voltage supplied to the first voltage terminal PCS is the second pull-up voltage VCC, the sensing time thereof is shorter than that when the voltage supplied to the first voltage terminal PCS is the first pull-up voltage VBLH. However, the first voltage terminal of the amplifying module cannot be at an excessively high voltage level for a long time, and when the first voltage terminal is in an overvoltage state for a long time, the reliability of data stored in the memory cell is affected.

The embodiment of the disclosure provides different first pull-up voltage VBLH and second pull-up voltage in a sensing stage by time-sharing the first voltage end PCS, so that the sense amplifier is not easy to influence the storage data of the storage unit while shortening the sensing time.

Drawings

FIG. 1 is a schematic diagram of a sense amplifier in some embodiments;

FIG. 2a is a waveform diagram illustrating stages of a sense amplifier read operation in some embodiments;

FIG. 2b is a waveform diagram of stages of a sense amplifier write operation in some embodiments;

FIG. 3 is a schematic diagram of a sense amplifier in an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a sense amplifier including a power supply module in an embodiment of the disclosure;

FIG. 5 is a schematic diagram of another sense amplifier included in an embodiment of the present disclosure;

FIG. 6 is a waveform diagram illustrating the voltages on the PCS terminal, the NCS terminal, the bit line Bla, the complementary bit line BLb, the memory CELL and the word line WL versus time during the sensing phase of the sense amplifier according to the embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a column selection module and a data input module provided in an embodiment of the disclosure;

FIG. 8 is a waveform diagram illustrating the PCS terminal, NCS terminal, bit line Bla, complementary bit line BLb, column select signal CSL, and voltage-time on word line WL provided to the sense amplifier during a write-back phase or a write-in phase according to an embodiment of the present disclosure;

FIG. 9 is a waveform diagram of voltages on PCS terminal, NCS terminal, bit line Bla, complementary bit line BLb, memory CELL, and word line WL provided during a sense phase including provided in some embodiments;

FIG. 10 is a schematic diagram of a control module provided in an embodiment of the present disclosure;

FIG. 11 is a diagram of V-T waveforms of an activate command, first control signals, second control signals, and PCS terminal;

FIG. 12 is a schematic diagram of a memory according to an embodiment of the disclosure;

fig. 13 to 17 are flowcharts illustrating an operation method of a sense amplifier according to an embodiment of the present disclosure.

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In some embodiments, as shown in FIG. 1, sense amplifier 100 includes an amplification module and a power supply module. A sense amplifier may be connected between the target bit line BLa and the complementary bit line BLb for converting the storage information of the memory cell to which the target bit line BLa is connected into a voltage corresponding to a logic "1" or "0", for example, a logic "1" may correspond to a high level and a logic "0" may correspond to a low level. And the voltage value can be presented on the bit line, and the stored information can be known by reading the bit line information. After completing one read operation of the memory data, the memory data in the memory cell can also be restored to the state before the read through the bit line.

The amplifying module includes a first P-type transistor m1, a second P-type transistor m3, a first N-type transistor m2, and a second N-type transistor m4.

The control end of the first P-type transistor m1 is connected with the control end of the first N-type transistor m2, the control end of the second P-type transistor m3 is connected with the control end of the second N-type transistor m4, the first end of the first P-type transistor m1 is connected with the first end of the first N-type transistor m2, the first end of the second P-type transistor m3 is connected with the first end of the second N-type transistor m4, the second end of the first P-type transistor m1 is connected with the second end of the second P-type transistor m3, the second end of the first N-type transistor m2 is connected with the second end of the second N-type transistor m4, the control end of the first P-type transistor is connected with the first end of the second P-type transistor, and the control end of the second P-type transistor is connected with the first end of the first P-type transistor.

The power module comprises a high power module and a low power module. The voltage provided by the high power module is higher than the voltage provided by the low power module. In some embodiments, the high voltage provided by the high power module is VBLH. The voltage provided by the low power module is VSS. The high power supply module provides a high voltage to the first input terminal of the amplification module. The first input terminal is a second terminal of the first P-type transistor, i.e., a second terminal of the second P-type transistor. The low power module provides a low voltage to the second input terminal of the amplification module. The second input terminal is a second terminal of the first N-type transistor, i.e., a second terminal of the second N-type transistor.

In some embodiments, the memory cell to which the bit line is connected may be a storage capacitor, and in some embodiments, the memory cell may be a storage capacitor and a selection transistor.

The sense amplifier can be used for carrying out various operations including reading operation and writing operation on the memory cell. As shown in fig. 2a, the read operation includes a Precharge phase (Precharge), a read phase (Access), a Sense phase (Sense), and a writeback phase (Restore). Fig. 2a also shows voltage-time waveforms of PCS terminal, NCS terminal, column select signal CSL, bit line Bla, complementary bit line BLb and word line WL during the respective phases. As shown in FIG. 2b, the Write operation includes a Precharge phase (Precharge), a read phase (Access), a Sense phase (Sense), a Write phase (Write Recovery), and a Write back phase (Restore). FIG. 2b also shows voltage-time waveforms of the PCS terminal, the NCS terminal, the column selection signal CSL, the bit line Bla and the word line WL at various stages. tSENSE represents the total time of the sense phase and tRAS represents the total time of the read phase, the sense phase and the writeback phase.

The following explains the read operation:

first, the bit line and the complementary bit line are precharged in a precharge phase so that the voltages of the bit line and the complementary bit line are the same, which may be denoted as Vref, which may be 0.5Vcc, for example.

Then, in the reading stage, the transistor in the memory cell is turned on by controlling the word line signal where the memory cell to be read is located. If the data stored in the storage capacitor is "1", the positive charge stored in the storage capacitor will flow to the bit line Bla connected thereto and further pull up the voltage of the bit line Bla to Vref +. If the data stored in the storage capacitor is "0", the bit line Bla charges the storage capacitor and lowers the voltage of the bit line Bla to Vref-.

Then, in the sensing phase, the data stored in the memory cell is "1", and the voltage of the bit line Bla is raised to Vref +, which is because the voltage of the bit line Bla is greater than the voltage of the complementary bit line Blb. The second N-type transistor m4 is more conductive than the first N-type transistor m2, and the first P-type transistor m1 is more conductive than the second P-type transistor m 3.

And at this time, the second terminal of the first P-type transistor m1 receives the high level VBLH from the high power module output. The second terminal of the first N-type transistor m2 receives the low level Vss from the low power module output.

In some embodiments, the high power supply module comprises a high power supply input end, a high power supply output end and a transistor m5 located between the high power supply input end and the high power supply output end, the transistor can be a P-type transistor or an N-type transistor, a control end of the transistor is used for receiving a first signal sig1, and the first signal sig1 is used for controlling the transistor m5 to be switched on and off. For example, in the sensing phase, the transistor m5 is turned on by the first signal sig1, so that the first input terminal PCS of the amplifying block receives the high level VBLH from the high voltage block.

In some embodiments, the low power supply module comprises a low power supply input terminal, a low power supply output terminal and a transistor m6 located between the low power supply input terminal and the low power supply output terminal, wherein the transistor can be a P-type transistor or an N-type transistor, a control terminal of the transistor is used for receiving the second signal sig2, and the second signal sig2 is used for controlling the transistor m6 to be switched on and off. For example, in the sensing phase, the transistor m6 is turned on by the second signal sig2, so that the second input terminal NCS of the amplifying block receives the low level GND from the low voltage block.

Since the second N-type transistor m4 is more conductive than the first N-type transistor m2, and the first P-type transistor m1 is more conductive than the second P-type transistor m3, the voltage of the bit line Bla is pulled up to the high level VBLH, and the voltage of the non-complementary bit line BLb is pulled down to GND. In this manner, the voltage difference between bit line Bla and complementary bit line BLb is amplified.

Then, a write-back stage is performed, and since the voltage of the bit line Bla is at the voltage VBLH corresponding to logic "1", the bit line Bla can charge the memory cell, and after a certain time, the charge amount in the memory cell can be restored to the state between the reading operations.

The following explains the write operation:

the precharge phase, read phase, and sense phase of the write operation may be referred to as the read operation described above. In contrast, a write operation will follow the sense phase with a write phase.

In the write phase, by controlling the column selection signal, the write circuit pulls the voltage of the bit line Bla and the voltage of the complementary bit line BLb according to the voltage corresponding to the target logic value, in some embodiments, if a logic "0" needs to be written into the memory cell, the voltage of the bit line Bla may be pulled downward, and the voltage of the complementary bit line BLb may be pulled upward, so that the voltage of the bit line Bla is smaller than the voltage of the complementary bit line BLb, for example, the voltage of the bit line Bla is GND, and the voltage of the complementary bit line BLb is VBLH.

Then, in the write back stage, since the voltage of the bit line Bla at this time is GND, a current flows from the memory cell to the bit line Bla, and after a certain time, the memory cell writes data "0". And finally, turning off the transistor in the memory cell to finish the writing operation of the logic data 0 to the memory cell.

How to reduce the sensing time of the read operation and the write operation, how to reduce the write-back time of the read operation, and how to reduce the write time of the write operation become problems to be solved.

An embodiment of the present disclosure provides a sense amplifier, as shown in fig. 3, the sense amplifier 1000 includes: an amplification module 100 and a power supply module;

the amplifying module 100 is used for amplifying a voltage difference between the bit line BLa and the complementary bit line BLb under the driving of the voltage provided by the power supply module;

the power supply module includes a pull-up driving unit 210, and the pull-up driving unit 210 is connected to the first voltage terminal PCS of the amplification module 100 and configured to provide a first pull-up voltage VBLH and a second pull-up voltage VCC to the amplification module 100 during a sensing phase, where the first pull-up voltage VBLH is less than the second pull-up voltage VCC.

The pull-up driving unit in the embodiment of the present disclosure may provide at least two voltages different from the GND voltage to the first voltage terminal PCS of the amplification block. The first pull-up voltage VBLH is smaller than the second pull-up voltage VCC, and when the voltage supplied to the first voltage terminal PCS is the second pull-up voltage VCC, the sensing time thereof is shorter than that when the voltage supplied to the first voltage terminal PCS is the first pull-up voltage VBLH. However, the first voltage terminal of the amplifying module cannot be at an excessively high voltage level for a long time, and when the first voltage terminal is in an overvoltage state for a long time, reliability of data stored in the memory cell is affected.

In the sensing stage, the first voltage end PCS is provided with the first pull-up voltage VBLH and the second pull-up voltage in a time-sharing mode, so that the sense amplifier is not easy to influence storage data of the storage unit while the sensing time is shortened.

In some embodiments, as shown in fig. 4, the power supply module includes a control unit 230 for providing a control signal to the pull-up driving unit 210;

the pull-up driving unit 210 includes a first voltage source input terminal VBLH, a second voltage source input terminal VCC, and a control terminal 211, for providing the first pull-up voltage to the amplification module based on the first voltage source VBLH according to the control signal for a first preset time period of a sensing phase, and for providing the second pull-up voltage VCC to the amplification module 100 based on the first voltage source VBLH and the second voltage source VCC according to the control signal for a second preset time period of the sensing phase;

the first voltage source VBLH supply voltage is smaller than the second voltage source VCC supply voltage.

In the embodiment of the disclosure, in a first preset time period of the sensing stage, the pull-up driving unit provides the first pull-up voltage to the amplifying module under the action of the control signal, and in a second preset time period of the sensing stage, the pull-up driving unit provides the second pull-up voltage VCC to the amplifying module under the action of the control signal. The first pull-up voltage may be generated based on the first voltage source VBLH, and the second pull-up voltage may be generated based on the first voltage source VBLH and the second voltage source VCC.

In some embodiments, as shown in fig. 5, the first pull-up voltage may be generated based on a first voltage source VBLH, and the second pull-up voltage may be generated based on a second voltage source VCC.

As shown in fig. 6, tSENSE in fig. 6 is the time elapsed for the sense phase. t2 is a second preset time period for starting to apply the second pull-up voltage VCC to the PCS terminal, so the first preset time period is the remaining time of the tSENSE excluding the second preset time period.

As shown in fig. 6, the voltage at the PCS terminal reaches the second pull-up voltage VCC for a second preset time period of the sensing phase and is maintained for a certain time period, so that the voltage of the bit line Bla quickly reaches the target voltage value, e.g., VBLH, at the end of the sensing phase. When the voltage on bit line Bla reaches the target voltage value, a write back operation may be performed. This is because the charge stored in the memory cell shares Bla with the bit line when the transistor in the memory cell is turned on, so that the charge stored in the memory cell becomes less and thus the charge needs to be stored in the memory cell again. Rapidly raising the voltage of the bit line Bla to the target voltage saves the time of the sensing phase on the one hand and facilitates the fast recovery of the data in the memory cell to logic "1" in the write-back phase of the read operation on the other hand. This not only ensures the stability of the data in the memory cell, but also shortens the time of tRAS (total time of read phase (Access), sense phase (Sense) and write back phase (Restore)), and increases the write back speed.

In some embodiments, the sense amplifier further includes a column selection module 300 shown in fig. 7, for transmitting data on the bit line Bla and/or the complementary bit line BLb to the data OUTPUT terminal OUTPUT1 and/or OUTPUT2 in a read operation and transmitting data INPUT from the INPUT terminal INPUT1 and/or INPUT2 of the data INPUT module 400 to the bit line Bla and/or the complementary bit line BLb in a write operation under the control of the column selection signal CSL;

the pull-up driving unit is configured to provide the second pull-up voltage to the amplifying module based on the first voltage source and the second voltage source according to the control signal within a third preset time period t3 shown in fig. 8; the third preset time period is from a first preset time when the column selection signal is at an active level to a second preset time after the column selection signal is inverted to an inactive level.

In the write-back stage, the bit line can perform a charging operation on the memory cell, or the memory cell discharges charge onto the bit line to restore the charge in the memory cell to that before the read operation. After the charge recovery in the memory cell is completed, the transistor Tc1 and the transistor Tc2 may be turned on by the column selection signal CSL, and the stored data may be OUTPUT through the data OUTPUT terminal OUTPUT1 and/or OUTPUT 2.

Taking the example of writing back logic "1" to the memory unit as follows:

before the data write-back is performed, the voltage of the bit line Bla needs to be pulled up to the target voltage value, e.g., a high level voltage, quickly in the time that the CSL is active. This allows the stored data to be obtained using the bit line voltage during the time that the CSL is active.

FIG. 9 is a diagram of the voltage of Bla during the write back stage in some embodiments. Since the PCS terminal always provides the voltage VBLH, the voltage of Bla does not reach the target voltage value when CSL is active, so that the data in the memory data cell in the memory cell does not completely rise to logic "1".

As shown in fig. 8, by providing the second pull-up voltage VCC to the PCS terminal of the amplification module at the first preset time T1 when the column selection signal CSL is active, wherein the second pull-up voltage VCC is greater than the first pull-up voltage VBLH, the voltage of the bit line Bla may rapidly rise to a target voltage, for example, a high level voltage, when the CSL is active. Further, the storage data in the storage unit is rapidly raised to logic '1', which ensures the stability of the data, shortens tRAS time, increases the speed of the Sense amplifier, and also helps to improve the sensing Margin (Sense Margin).

As shown in fig. 8, the waveform diagram may also correspond to the write phase of the write operation. Taking the example of writing logic "1", during the writing phase, tw1 and Tw2 are turned on by controlling the WE (Write Enable) signal of the data INPUT module 400 in fig. 7, and Tc1 and Tc2 are turned on by controlling the column selection signal CSL, and the bit line Bla is pulled to logic "1" by the high voltage INPUT from the data INPUT terminal INPUT 1. The bit line BLb is pulled to logic "0" by the low voltage INPUT at the data INPUT terminal INPUT 2.

However, in the waveform diagram shown in fig. 9, after the CSL is turned off, the charge in the memory cell is not fully charged to logic "1", which may cause inaccuracy in the data written into the memory cell.

In the embodiment of the disclosure, by providing the second pull-up voltage VCC to the PCS terminal of the amplification module at the first preset time T1 when the column selection signal CSL is at the active level, where the second pull-up voltage VCC is greater than the first pull-up voltage VBLH, the voltage of the bit line Bla may rapidly rise to a target voltage, for example, a high level voltage, when the CSL is active. Further, the charge in the memory cell is fully charged to logic "1", i.e. data "1" is written fast, which ensures data stability, shortens the tRAS time, and increases the speed, thus ensuring that the voltage of the memory cell reaches a higher level in a shorter time, which also helps to improve the sensing margin. The writing of a logic "1" can then be accomplished by controlling the word line to which the transistor in the memory cell is connected to turn off the transistor in the memory cell.

In some embodiments, the control unit 230 in fig. 4 includes a first control signal output terminal 211a and a second control signal output terminal 211b;

the pull-up driving unit 210 includes a first transistor M6 and a second transistor M5; the first transistor M6 is connected between the first voltage source input terminal VCC and the second voltage source input terminal VBLH, and the control terminal SAP _ OD of the first transistor M6 is connected to the first control signal output terminal 211 a; the second transistor M5 is connected between the second voltage source input terminal VBLH and the first voltage terminal PCS of the amplification module 100, and the control terminal SAP of the second transistor M5 is connected to the second control signal output terminal 211b;

the control unit 230 outputs a first voltage V1 through the first control signal output terminal 211a to turn off the first transistor M6, and outputs a second voltage V2 through the second control signal output terminal 211b to turn on the second transistor M5 in the first preset time period T1 of the sensing phase; the control unit 230 outputs a third voltage V3 through the first control signal output terminal 211a during the second preset time period T2 of the sensing phase, so as to turn on the first transistor M6, and outputs a fourth voltage V4 through the second control signal output terminal 211b, so as to turn on the second transistor.

In the embodiment of the present disclosure, the pull-up driving unit 210 includes a first transistor M6 and a second transistor M5 connected in series, and the first transistor M6 may be a PMOS transistor or an NMOS transistor. The second transistor M5 may be a PMOS transistor or an NMOS transistor.

In some embodiments, the first transistor M6 is a PMOS transistor, and the second transistor M5 is a PMOS transistor.

A first terminal of the first transistor M6 is connected to a second terminal of the second transistor M5. The second terminal of the first transistor M6 is connected to the first voltage source input terminal VCC, and the first terminal of the first transistor M6 is further connected to the second voltage source input terminal VBLH. The control terminal of the first transistor M6 is connected to the first control signal output terminal 211a via SAP _ OD, and receives the voltage outputted from the first control signal output terminal 211 a. When the output voltage is greater than the threshold voltage of the first transistor M6, for example, the first voltage V1, the first transistor M6 is turned off. When the output voltage is less than the threshold voltage of the first transistor M6, for example, the second voltage V2, the first transistor M6 is turned on. The control terminal connection SAP of the second transistor M5 is connected to the second control signal output terminal 211b, and receives the voltage output by the second control signal output terminal 211 b. When the output voltage is greater than the threshold voltage of the second transistor M5, for example, the third voltage V3, the second transistor M5 is turned off. When the output voltage is less than the threshold voltage of the second transistor M5, for example, the fourth voltage V4, the first transistor M6 is turned on.

The size and model of the first transistor M6 and the size and model of the second transistor M5 may be the same. The value of the first voltage V1 is now equal to the value of the third voltage V3 and the value of the second voltage V2 is equal to the value of the fourth voltage V4. The size and model of the first transistor M6 and the size and model of the second transistor M5 may be different. At this time, the value of the first voltage V1 may not be equal to the value of the third voltage V3, and the value of the second voltage V2 may not be equal to the value of the fourth voltage V4.

The control unit 230 may control when the first voltage V1 is applied to the control terminal of the first transistor M6 and when the second voltage V2 is applied to the control terminal of the first transistor M6. That is, the control unit may control when the first transistor M6 is turned off and when it is turned on.

The control unit 230 may also control when the third voltage V3 is applied to the control terminal of the second transistor M5 and when the fourth voltage V4 is applied to the control terminal of the second transistor M5. That is, the control unit may control when the second transistor M5 is turned off and when it is turned on.

In the embodiment of the present disclosure, the control unit 230 outputs a first voltage V1 to the control terminal of the first transistor M6 through the first control signal output terminal 211a during a first preset time period T1 of the sensing stage as shown in fig. 6, so as to turn off the first transistor M6, and outputs a fourth voltage V4 to the control terminal of the second transistor M5 through the second control signal output terminal 211b, so as to turn on the second transistor M5. Thus, the voltage of the second voltage source input terminal VBLH can be input to the first input terminal PCS of the amplifying module 100. During a first preset period T1 before the second preset period T2, the voltage of the PCS terminal is increased to VBLH.

The control unit 230 outputs a second voltage V2 to the control terminal of the first transistor M6 through the first control signal output terminal 211a to turn on the first transistor M6, and outputs a fourth voltage V4 to the control terminal of the second transistor M5 through the second control signal output terminal 211b to turn on the second transistor M5 in a second preset time period T2 of the sensing phase shown in fig. 6. Thus, the voltage of the first voltage source VCC can be inputted to the first input PCS of the amplifying module 100. During the second preset time period T2, the voltage at the PCS terminal is increased from VBLH to VCC and is maintained for a certain time.

In a first preset time period T1 after the second preset time period T2, the voltage at the PCS terminal decreases from VCC to VBLH.

The third preset time period T3 is from a first preset time T1 when the column selection signal CSL is at an active level to a second preset time T2 after the column selection signal CSL is inverted to an inactive level.

At the first preset time T1, the voltage of the PCS terminal may start to increase from the first pull-up voltage VBLH to reach the second pull-up voltage VCC within the third preset time period T3. Therefore, at the first preset time t1, the second pull-up voltage VCC may be provided to the PCS terminal through the pull-up driving module.

At a second preset time t2, the voltage of the PCS terminal may start to decrease from the second pull-up voltage VCC, so that the voltage of the PCS terminal is restored to the first pull-up voltage VBLH.

Therefore, in the third preset time period T3, the stable second pull-up voltage VCC may be provided to the PCS terminal through the pull-up driving module.

Specifically, the first transistor M6 and the second transistor M5 may be turned on by the control module 230 at this time. In some embodiments, the second voltage may be output to the control terminal of the first transistor M6 through the first control signal output terminal 211a to turn on the first transistor M6, and the fourth voltage may be output through the second control signal output terminal 211b to turn on the second transistor M5, so that the stable second pull-up voltage VCC may be provided to the PCS terminal through the pull-up driving module during the third preset time period T3.

In some embodiments, as shown in fig. 10, the control unit 230 includes an activation command input terminal 211c, a first control signal generation circuit and a second control signal generation circuit;

the first control signal generating circuit comprises a first inverter 401, a first nor gate 402, a second inverter 403, an and gate 404 and a second nor gate 405;

an input terminal of the first inverter 401 is connected to the activation command input terminal 211c, and an output terminal of the first inverter 401 is connected to a first input terminal of the first nor gate 402;

a second input of the first nor gate 402 is connected to the activate command input, and an output of the first nor gate 402 is connected to a first input of the second nor gate 405;

the input end of the second inverter 403 is connected to the second control signal output end, and the output end of the second inverter 403 is connected to the first input end of the and gate 404;

a second input end of the and gate 404 is connected to the second control signal output end, and an output end of the and gate 404 is connected to a second input end of the second nor gate 405;

the output of the second nor gate 405 is connected to the first control signal output;

the second control signal generation circuit including a delay circuit (delay) 406 connected between the activation command input terminal 211c and the second control signal output terminal 211b; the delay circuit 406 has a first delay time.

In the embodiment of the present disclosure, the control unit 230 includes an activate command input end 211c, where the activate command input end 211c is configured to receive an activate command ACTIVE, and the activate command is configured to open a row address, and in the embodiment of the present disclosure, the activate command is further configured to activate the control unit 230.

The control unit 230 includes a first control signal generating circuit and a second control signal generating circuit, wherein an input terminal of the second control signal generating circuit is the activation command input terminal 211c, and an output terminal of the second control signal generating circuit is the second control signal output terminal. The second control signal generating circuit includes a delay circuit 406, which is provided between the activate command input terminal 211c and the second control signal output terminal, and outputs the delayed activate command. The input terminal of the first control signal generating circuit is the activation command input terminal 211c, and the output terminal of the first control signal generating circuit is the first control signal output terminal. The first control signal generation circuit includes a first inverter 401, a first nor gate 402, a second inverter 403, an and gate 404, and a second nor gate 405.

The V-t (voltage-time) waveforms of the activate command, the first control signal, and the second control signal are shown in fig. 11.

FIG. 11 also shows a V-t waveform diagram at the PCS terminal, under the influence of the first control signal and the second control signal.

In the embodiment of the present disclosure, the delay circuit 406 in fig. 10 has a first delay time, the first inverter 401 has a second delay time, and the second inverter 403 has a third delay time.

When the first transistor M6 is a PMOS transistor and the second transistor M5 is a PMOS transistor, the first transistor M6 is turned on when the first control signal output terminal SAP outputs the third voltage, i.e., the low level voltage, in the second preset period T2 of the sensing time. When the second control signal output terminal SAP _ OD outputs the fourth voltage, i.e., the low level voltage, the second transistor M5 is turned on. So that the PCS terminal receives the second pull-up voltage VCC provided from the first voltage source and the second voltage source. That is, in the second preset period T2, the voltage at the PCS terminal is pulled up to VCC from the initial voltage V0 (V0 may be Vref), and is maintained for a certain time.

When the first control signal output terminal 211a outputs the first voltage, i.e., the high level voltage, in the first preset period T1 of the sensing time, the first transistor M6 is turned off. When the second control signal output terminal 211b outputs the fourth voltage, i.e., the low level voltage, the second transistor M5 is turned on. So that the PCS terminal receives the first pull-up voltage VBLH supplied from the first voltage source.

That is, in the first preset period T1, the voltage at the PCS terminal drops from VCC to VBLH and is maintained for a certain time.

When the first control signal output end SAP outputs the third voltage, i.e., the low level voltage, at the first preset time t1 of the write-back stage of the read operation and/or the write-in stage of the write operation, the first transistor M6 is turned on. When the second control signal output terminal SAP _ OD outputs the fourth voltage, i.e., the low level voltage, the second transistor M5 is turned on. So that the PCS terminal receives the second pull-up voltage VCC supplied from the first voltage source and the second voltage source. When the first control signal output end SAP outputs the third voltage, i.e., the high level voltage, at the second preset time t2 in the write-back stage of the read operation and/or the write-in stage of the write operation, the first transistor M6 is turned off. When the second control signal output terminal SAP _ OD outputs the second voltage, i.e., the high level voltage, the second transistor M5 is turned off. So that the voltage at the PCS terminal drops from VCC to the initial voltage.

That is, the voltage at the PCS terminal is pulled up from VBLH to VCC at an initial time of the third preset period T3, and then VCC is maintained for a period of time. At the final time of T3, the voltage at the PCS terminal drops from VCC to the initial voltage.

The embodiment of the present disclosure further provides a memory 1100, as shown in fig. 12, including the sense amplifier 1000 according to any one of the above embodiments.

In some embodiments, memory 1100 includes sense amplifier 1000 and a memory array. The memory array includes at least a first memory string 1201 and a second memory string 1202, where each memory string in turn includes a plurality of memory cells 1301. The memory cells 1301 of the first memory string 1201 are connected together to a bit line BLa, and the memory cells 1301 of the second memory string 1202 are connected together to a complementary bit line BLb.

The memory cell may include a storage capacitor C and an access transistor T. The first end of the storage capacitor C is connected with the reference voltage Vref, the second end of the storage capacitor C is connected with the first end of the access transistor T, the second end of the access transistor T is connected with the bit line BL, and the control end of the access transistor T is connected with the word line. The access transistor T is used to control whether to permit or prohibit reading or rewriting of information stored in the storage capacitor C.

The embodiment of the present disclosure further provides an operating method of a memory, where the memory includes the sense amplifier described in any of the above embodiments; the method as shown in fig. 13 includes: step S101, in a sensing phase of a read operation and/or a write operation, the pull-up driving unit time-divisionally provides a first pull-up voltage and a second pull-up voltage to the amplifying module, where the first pull-up voltage is smaller than the second pull-up voltage.

The sense amplifier in the disclosed embodiment includes a pull-up driving unit and an amplifying module.

In step S101, the voltage of the target bit line is quickly pulled up to the target voltage in the sensing phase by providing the first pull-up voltage and the second pull-up voltage to the amplifying module by using the pull-up driving unit of the sense amplifier at different periods of the sensing phase.

When the data in the memory cell connected to the bit line Bla in fig. 3 is logic "0", if the data in the memory cell is to be read, the target bit line is the complementary bit line BLb, and the voltage of the complementary bit line BLb needs to be rapidly pulled up to the target voltage, i.e. the first pull-up voltage and the second pull-up voltage, in the sensing phase.

When the data in the memory cell connected to the bit line Bla in fig. 3 is logic "1", if the data in the memory cell needs to be read, the target bit line is the bit line Bla, and the voltage of the bit line Bla needs to be quickly pulled up to the target voltages, i.e., the first pull-up voltage and the second pull-up voltage, in the sensing phase.

In some embodiments, the power module includes a control unit for providing a control signal to the pull-up driving unit; the pull-up driving unit comprises a first voltage source input end, a second voltage source input end and a control end; the sense amplifier also comprises a column selection module, a data output end and a data output end, wherein the column selection module is used for transmitting data on the bit line to the data output end in a read operation under the control of a column selection signal; in step S101, the time-sharing supplying, by the pull-up driving unit, the first pull-up voltage and the second pull-up voltage to the amplifying module in the sensing phase of the read operation and/or the write operation includes:

as shown in fig. 14, in step S201, the first pull-up voltage is provided to the amplification module based on the first voltage source according to the control signal for a first preset time period in a sensing phase of the read or write operation, and the second pull-up voltage is provided to the amplification module based on the first voltage source and the second voltage source according to the control signal for a second preset time period in the sensing phase.

In some embodiments, step S101 may be replaced with step S201.

First, in a second preset time period T2 of the sensing node as shown in fig. 6, the second pull-up voltage VCC is provided to the amplifying module based on the first voltage source and the second voltage source according to the control signal generated by the control module. The voltage at the PCS terminal is pulled up from the initial voltage to VCC and is maintained for a certain time.

Then, the first pull-up voltage VBLH is supplied to the amplification block based on the first voltage source according to the control signal generated by the control block for a first preset time period T1 of the sensing node as shown in fig. 6. The voltage at the PCS terminal is reduced from VCC to VBLH and is kept for a certain time.

The sum of the second preset time period T2 and the first preset time period T1 is the total time period used for the sensing phase.

In some embodiments, as shown in fig. 15, the method further comprises: step S301, in a third preset time period of the write-back phase of the read operation and/or the write-in phase of the write operation, providing the second pull-up voltage to the amplifying module based on the first voltage source and the second voltage source according to the control signal; the third preset time period is from a first preset moment when the column selection signal is at an effective level to a second preset moment after the column selection signal is inverted to an ineffective level;

After the sense phase of the read operation is complete, a write back phase of the read operation may be performed.

After the sensing phase of the write operation is completed, the write phase of the write operation may be performed.

As shown in fig. 8, at a first preset time t1 of a third preset time period, the second pull-up voltage VCC is provided to the amplification module based on the first voltage source and the second voltage source according to the control signal generated by the control module, so that the voltage at the PCS terminal is pulled up from VBLH to VCC, at a second preset time t2 of the third preset time period, the pull-up voltage is not provided to the amplification module according to the control signal generated by the control module, and after the second preset time t2, the voltage at the PCS terminal is decreased from VCC to the initial voltage.

In the embodiment of the present disclosure, the first preset time t1 is when the column selection signal is at the active level, and the second preset time t2 is when the column selection signal is switched to the inactive level.

In the embodiment of the disclosure, the overvoltage is added to the PCS section for a certain time within the third preset time period, so that the voltage of the target bit line can be quickly increased to the target voltage. Thereby facilitating the data in the memory cell to be written back or written quickly. This is advantageous for stability of the stored data and for increasing the speed of data write back or writing.

In some embodiments, the third preset time period may be 5ns. The value of the first preset time period can also be set to be different according to the change of the second pull-up voltage. For example, when the value of the first pull-up voltage is greater than VCC, the first preset time period may be less than 5ns, and when the value of the first pull-up voltage is greater than VCC, the first preset time period may be greater than 5ns.

In some embodiments, as shown in fig. 4, the control unit 230 includes a first control signal output terminal 211a and a second control signal output terminal 211b;

the pull-up driving unit 210 includes a first transistor M6 and a second transistor M5; the first transistor M6 is connected between the first voltage source input terminal VCC and the second voltage source input terminal VBLH, and a control terminal of the first transistor M6 is connected to the first control signal output terminal 211 a; the second transistor M5 is connected between the second voltage source input terminal VBLH and the first voltage terminal PCS of the amplification module 100, and a control terminal of the second transistor M5 is connected to the second control signal output terminal 211b; as shown in fig. 16 or 17, the method further includes: step S401, in the sensing phase of the read operation and/or the write operation, the control unit generates a first control signal and a second control signal according to an activation command.

The control signal generated by the control unit includes a first control signal and a second control signal. The first control signal is used to control the first transistor M6 to be turned on and off, and the second control signal is used to control the second transistor M5 to be turned on and off.

In step S401, the control unit may generate a first control signal and a second control signal according to the activation command.

In step S201 and/or step S301, the first pull-up voltage and/or the second pull-up voltage is provided to the amplification module for a specified time period (e.g., a first preset time period, a second preset time period, etc.) according to the first control signal and the second control signal generated in step S401.

In some embodiments, as shown in fig. 10, the first transistor M6 and the second transistor M5 are both P-type transistors; the control unit 230 includes an activation command input terminal 211a, a first control signal generation circuit and a second control signal generation circuit;

an input terminal of the first inverter 401 is connected to the activation command input terminal 211a, and an input terminal of the first inverter 401 is connected to a first input terminal of the first nor gate 402;

a second input of the first nor gate 402 is connected to the activate command input 211a, and an output of the first nor gate 402 is connected to a first input of the second nor gate 405;

the input end of the second inverter 403 is connected to the second control signal output end, and the output end of the second inverter 404 is connected to the first input end of the and gate 404;

a second input end of the and gate 404 is connected to the second control signal output end 211b, and an output end of the and gate 404 is connected to a second input end of the second nor gate 405;

an output terminal of the second nor gate 405 is connected to the first control signal output terminal 211 a;

the second control signal generating circuit comprises a delay circuit 406 connected between the activation command input terminal 211c and the second control signal output terminal 211b;

In some embodiments, the second preset time period is 2ns. The value of the second preset time period can also set different value ranges according to the change of the second pull-up voltage. For example, when the value of the second pull-up voltage is greater than VCC, the second preset time period may be less than 2ns, and when the value of the second pull-up voltage is greater than VCC, the second preset time period may be greater than 2ns.

It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description, and do not represent the advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A sense amplifier, comprising: the amplification module and the power supply module;

2. The sense amplifier of claim 1, wherein the power supply module comprises a control unit for providing a control signal to the pull-up driving unit;

3. The sense amplifier of claim 2, further comprising a column selection module for transmitting data on the bit line to a data output terminal in a read operation and transmitting input data on a data input terminal to the bit line in a write operation under control of a column selection signal;

4. The sense amplifier of claim 3, wherein the control unit comprises a first control signal output and a second control signal output;

5. The sense amplifier of claim 4, wherein the third predetermined period of time is to turn on the first transistor and to output a second voltage through the second control signal output terminal to turn on the second transistor.

6. The sense amplifier of claim 5, wherein the first transistor and the second transistor are both P-type transistors.

7. The sense amplifier of claim 6, wherein the control unit comprises an activation command input, a first control signal generating circuit and a second control signal generating circuit;

8. The sense amplifier of claim 7 wherein the first inverter has a second delay time and the second inverter has a third delay time.

9. A memory comprising a sense amplifier as claimed in any one of claims 1 to 8.

10. A method of operating a memory, wherein the memory includes the sense amplifier of claim 1; the method comprises the following steps: in a sensing phase of a reading operation and/or a writing operation, the pull-up driving unit supplies a first pull-up voltage and a second pull-up voltage to the amplifying module in a time sharing mode, and the first pull-up voltage is smaller than the second pull-up voltage.

11. The operating method of claim 10, wherein the power module comprises a control unit for providing a control signal to the pull-up drive unit; the pull-up driving unit comprises a first voltage source input end, a second voltage source input end and a control end; the sense amplifier also comprises a column selection module, a data output end and a data output end, wherein the column selection module is used for transmitting data on the bit line to the data output end in a read operation under the control of a column selection signal; the time-sharing supplying of the first pull-up voltage and the second pull-up voltage to the amplifying module by the pull-up driving unit in the sensing phase of the read operation and/or the write operation includes: the first pull-up voltage is provided to the amplification module based on a first voltage source according to the control signal for a first preset time period of a sensing phase of the read or write operation, and the second pull-up voltage is provided to the amplification module based on the first voltage source and a second voltage source according to the control signal for a second preset time period of the sensing phase.

12. The method of operation of claim 11, further comprising:

providing the second pull-up voltage to the amplifying module based on the first voltage source and the second voltage source according to the control signal within a third preset time period of a write-back stage of the read operation and/or a write-in stage of the write operation; the third preset time period is from a first preset moment when the column selection signal is at an effective level to a second preset moment after the column selection signal is inverted to an ineffective level;

13. An operating method according to claim 12, characterised in that the third preset period of time is 5ns.

14. The operating method according to claim 11 or 12, wherein the control unit comprises a first control signal output and a second control signal output;

15. The operating method according to claim 14, wherein the first transistor and the second transistor are both P-type transistors; the control unit comprises an activation command input end, a first control signal generation circuit and a second control signal generation circuit;

the input end of the first inverter is connected with the activation command input end, and the input end of the first inverter is connected with the first input end of the first NOR gate;

16. The operating method of claim 11, wherein the second predetermined period of time is 2ns.