CN115618937A

CN115618937A - Sensory and computational device and preparation method thereof

Info

Publication number: CN115618937A
Application number: CN202211242145.3A
Authority: CN
Inventors: 杨雅芬; 何振宇; 王天宇; 孟佳琳; 张卫
Original assignee: Shanghai IC Manufacturing Innovation Center Co Ltd
Current assignee: Shanghai IC Manufacturing Innovation Center Co Ltd
Priority date: 2022-10-11
Filing date: 2022-10-11
Publication date: 2023-01-17

Abstract

The invention discloses a sensing and calculating device and a preparation method thereof, which comprises a first electrode and a second electrode which are formed on a substrate in parallel, and a functional layer connected between the first electrode and the second electrode, wherein the functional layer is composed of oxide nanowires of a first electrode metal formed on the surface of the first electrode and oxide nanowires of a second electrode metal formed on the surface of the second electrode. The memristor constructed by the oxide nanowire based on the electrode metal is combined with the CMOS process material, so that the sensory-computational integrated neurosynaptic device with the characteristics of light weight, easiness in preparation and the like can be realized, and the application prospect is wide.

Description

Inductive computing device and preparation method

Technical Field

The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a CMOS (complementary metal oxide semiconductor) post-process-based inductive computing device and a preparation method thereof.

Background

With continuous progress of information technologies such as artificial intelligence and big data, a faster and more efficient computing system is needed to meet the development requirements of the information technologies. However, the limitation of moore's law and the defects of von neumann architecture restrict the development of the existing computer technology, so that the integrated device becomes a new development direction of the semiconductor industry. The memristor has the characteristic of integral calculation, and has higher speed and lower energy consumption than a traditional computer when processing the same amount of calculation tasks.

At present, a variety of neurosynaptic devices inspired by human brain in a body have been studied. To date, a computationally integrated memristive function has been implemented in various types of materials, such as semiconductors, insulators, solid electrolytes, two-dimensional materials, and organic materials.

For the resistance change memristor, the functional layer is a carrier of the resistance change characteristic. The selection of the functional layer not only depends on the manufacturing difficulty of the memristor, but also often determines the electrical characteristics of the memristor device.

At present, most of the memory and computation integrated devices based on memristors are mainly of an MIM (metal-insulator-metal) multilayer stack structure, and the planar structure device occupies a larger area compared with a three-dimensional structure. In addition, most materials are difficult to be compatible with the materials of the traditional CMOS process in terms of the material architecture of the device, and the introduction of new materials in the traditional integrated circuit process requires very high research and development cost and technical difficulty.

With the scaling of dimensions, today's transistors have evolved from planar structures to three-dimensional stacking and full-wrapping of nanoplates and nanowires, and the research of nanowire-based devices has become increasingly important. The traditional von Neumann transistor-based computing architecture has the problems of computing delay caused by larger signal transmission time and memory wall in the information processing process due to the separation of a computing unit and a memory unit. Therefore, the research of the novel inductive-computational integrated device based on the nanowire functional layer structure has very important significance for the development of future integrated circuits.

Disclosure of Invention

The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a sensory computing device and a method for manufacturing the same.

In order to achieve the purpose, the technical scheme of the invention is as follows:

the present invention provides a sensory computing device, including:

a substrate;

a first electrode and a second electrode provided in parallel on the substrate;

a functional layer connected between the first electrode and the second electrode;

wherein the functional layer is composed of oxide nanowires of a first electrode metal formed on the surface of the first electrode and oxide nanowires of a second electrode metal formed on the surface of the second electrode.

Furthermore, a first lower adhesion and barrier layer is arranged between the substrate and the first electrode, a second lower adhesion and barrier layer is arranged between the substrate and the second electrode, and the functional layer is suspended above the substrate between the first lower adhesion and barrier layer and the second lower adhesion and barrier layer.

Furthermore, a first upper adhesion and barrier layer is arranged on the upper surface of the first electrode, a second upper adhesion and barrier layer is arranged on the upper surface of the second electrode, and a dielectric layer covering the functional layer is arranged between the first upper adhesion and barrier layer and the second upper adhesion and barrier layer.

Further, the first electrode metal and the second electrode metal include copper, and the oxide nanowire of the first electrode metal and the oxide nanowire of the second electrode metal include copper oxide nanowires.

Further, the dielectric layer material comprises a low dielectric constant material.

The invention also provides a preparation method of the inductive computing device, which comprises the following steps:

providing a substrate;

forming a first dielectric layer on the substrate;

forming two first grooves reaching the surface of the substrate on the first dielectric layer;

forming a lower adhesion and barrier layer on the surface of the substrate exposed from the bottom of each first trench;

forming an electrode in each of the first trenches on each of the lower adhesion and barrier layers;

removing the first dielectric layer material between the two first trenches to form a second trench reaching the surface of the substrate and expose the side walls of the two opposite electrodes;

forming a functional layer of oxide nanowires of an electrode metal suspended between opposing sidewalls of two of the electrodes in the second trenches.

Further, still include: forming an upper adhesion and barrier layer on the upper surface of each of the electrodes; and forming a second dielectric layer covering the functional layer between the two upper adhesion and barrier layers.

Further, a copper electrode is formed in the first trench using a physical vapor deposition technique.

Further, a functional layer of copper oxide nanowires is formed between opposing sidewalls of two of the copper electrodes using a thermal oxidation technique.

Further, a first dielectric layer of a low dielectric constant material is formed on the substrate using a chemical vapor deposition technique, and the first trench is formed on the first dielectric layer using an ultraviolet lithography and etching technique.

The invention has the following advantages:

(1) The nerve synapse device constructed based on the copper oxide nanowires can realize connection of device-level simulated brain synapses;

(2) The copper oxide nanowires can be used for realizing response to gas change, can be applied to gas sensing and realize a storage and calculation integrated device based on device sensing;

(3) The memristor structure based on the copper oxide nanowire is combined with a CMOS material and a process, so that the connection of synapses of a device-level simulated brain can be realized, and the application of the synapses of the sensory-computational integrated nerve is realized;

(4) The preparation of the device can be realized through processes such as ultraviolet lithography, PVD and the like, the method is simple and convenient, and the device can be compatible with the traditional CMOS material and process as well as the CMOS subsequent process;

(5) The device is prepared based on the photoetching process, and the size of the device can be accurately controlled;

(6) The electrical characteristics of the device are simple and convenient to test.

Drawings

FIG. 1 is a schematic diagram of a storage device according to a preferred embodiment of the present invention;

FIG. 2 is a flow chart of a method for fabricating a storage device according to a preferred embodiment of the present invention;

fig. 3-12 are schematic diagrams illustrating the process steps of fabricating a storage device according to the method of fig. 2, in accordance with a preferred embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but not the exclusion of other elements or items.

Conventional computing systems are primarily based on von neumann architectures, where the processing of information requires transfer between an operator and memory. The novel sense-storage-calculation integrated device realized based on the novel semiconductor device memristor is inspired by the human brain, storage and processing of synapses between the brains on information are simulated, a novel information calculation and processing mode can be provided, a traditional Von Neumann calculation system can be expected to be broken through, and more efficient and low-power-consumption processing on the information is realized. The conductance of the memristor can change continuously with the change of the amount of charge flowing through, and the change can be maintained after power failure, and the characteristic is very similar to the nonlinear transmission characteristic of the nerve synapse. The memristor is used as the nerve synapse in the neuromorphic circuit, so that the method has a great application prospect.

The invention provides a CMOS (complementary metal oxide semiconductor) post process-based copper oxide nanowire sensing and calculating device, belongs to the field of novel semiconductor sensing and calculating artificial nerve synapse devices, and particularly relates to a CMOS process compatible material-based nerve synapse device prepared by ultraviolet lithography and physical vapor deposition processes, which is expected to be applied to the manufacturing of future sensing and calculating devices.

Al, co, cu, cuO, taN and the like are all materials which are compatible with the CMOS subsequent process and can be prepared. The neural morphology memristor with TaN, al, co and other materials as electrodes and CuO nanowires as functional layers can realize the computationally integrated artificial synapse function, can also realize the response of gas, further obtains the computationally integrated function, is expected to provide reference for breaking through the traditional Von Neumann computing architecture in the future, and has a great application prospect.

Currently, the maximum temperature of the CMOS backend process is approximately 400 to 450 ℃, while the current thermal oxidation growth temperature of the CuO nanowire is approximately 400 ℃. In the method for preparing the inductive computing device, the influence of the temperature condition of the traditional CMOS process on the whole process in the preparation process of the device is evaluated, and the compatibility with the traditional CMOS material and process and the subsequent CMOS process is realized by optimizing the process.

The conductance of a memristor can change continuously with changes in the amount of charge flowing through, and its changes can be maintained after a power outage, a characteristic very similar to the nonlinear transfer characteristic of a neural synapse. The nerve synapse device constructed based on the copper oxide nanowires can complete connection of device-level simulated brain synapses, and the copper oxide nanowires can be applied to gas sensing. The memristor constructed by the copper oxide nanowire is combined with CMOS process materials, and the sensing and storing integrated nerve synapse device with the characteristics of light weight, easiness in preparation and the like can be realized.

Based on the research, the invention provides a copper oxide nanowire inductive computing device based on a CMOS (complementary metal oxide semiconductor) subsequent process and a preparation method thereof.

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a storage device according to a preferred embodiment of the invention. As shown in fig. 1, a sensory computing device of the present invention includes: a substrate 10; a first electrode 12 and a second electrode 17 juxtaposed on the substrate 10; and a functional layer 15 connected between the first electrode 12 and the second electrode 17.

The functional layer 15 is composed of an interlaced structure (an interlaced structure) having an air gap, in which oxide nanowires of the first electrode metal formed on the sidewall surface of the first electrode 12 and oxide nanowires of the second electrode metal formed on the sidewall surface of the second electrode 17 are interlaced (interlaced).

In a preferred embodiment, the substrate 10 may be a conventional semiconductor substrate 10, such as a silicon substrate 10, but is not limited thereto.

In a preferred embodiment, the first electrode metal and the second electrode metal may comprise copper metal. Thus, the first electrode 12 is a first copper electrode, the second electrode 17 is a second copper electrode, and the oxide nanowires of the first electrode metal and the oxide nanowires of the second electrode metal are copper oxide nanowires 24 formed by oxidizing the electrode metal copper on the sidewall surface of the first copper electrode and the electrode metal copper on the sidewall surface of the second copper electrode, respectively. Thereby forming a memristor structure based on the copper oxide nanowires 24.

In a preferred embodiment, the thickness of the first copper electrode (first electrode 12) and the second copper electrode (second electrode 17) may be 300-1000 nm.

In some alternative embodiments, other metals than copper may be used for the first electrode metal and the second electrode metal, and the functional layer 15 may be formed by oxide nanowires corresponding to the electrode metals.

Please refer to fig. 1. In a preferred embodiment, a first lower adhesion and barrier layer 11 may be disposed between the substrate 10 and the first electrode 12; also, a second lower adhesion and barrier layer 18 may be disposed between the substrate 10 and the second electrode 17. The first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 are oppositely disposed so that a trench (refer to the second trench 23 in fig. 10) structure is formed between the first electrode 12 and the second electrode 17, and between the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18. Wherein the upper end of the trench is an opening, and the lower end of the trench reaches the upper surface of the silicon substrate 10, i.e., the upper surface of the silicon substrate 10 is exposed on the bottom surface of the trench. Thus, the copper oxide nanowire functional layer 15 connected between the sidewall of the first electrode 12 and the sidewall of the second electrode 17 is suspended in the trench above the silicon substrate 10 between the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18. I.e. a cavity 19 is formed between the copper oxide nanowire functional layer 15 and the upper surface of the silicon substrate 10.

By utilizing the formed cavity 19 structure, the cavity 19 can be communicated with the outside, so that the formed interweaving structure body with air gaps of the copper oxide nano wires 24 can be utilized for gas sensing, a storage and calculation integrated device based on device sensing can be realized, and the application of a sensing and calculation integrated nerve synapse can be realized.

In a preferred embodiment, the first lower adhesion and barrier layer 11 material and/or the second lower adhesion and barrier layer 18 material may be fabricated using a stack of Ti and Pt materials.

Further, the thickness of the Ti layer material in the first lower adhesion and barrier layer 11 material and/or the second lower adhesion and barrier layer 18 may be 10 to 20nm, and the thickness of the pt layer material may be 30 to 100nm.

In another preferred embodiment, the first lower adhesion and barrier layer 11 material and/or the second lower adhesion and barrier layer 18 material may be fabricated using a stacked material of Ta and TaN.

Further, the thickness of the Ta layer material in the first lower adhesion and barrier layer 11 and/or the second lower adhesion and barrier layer 18 may be 10-20nm, and the thickness of the TaN layer material may be 30-100 nm.

Please refer to fig. 1. In a preferred embodiment, a first upper adhesion and barrier layer 13 may be disposed on the upper surface of the first electrode 12; and, a second upper adhesion and barrier layer 16 may be provided on the upper surface of the second electrode 17.

In a preferred embodiment, the upper surface of the first upper adhesion and barrier layer 13 is flush with the upper surface of the second upper adhesion and barrier layer 16.

In an alternative embodiment, the first upper adhesion and barrier layer 13 is disposed opposite the second upper adhesion and barrier layer 16, and a dielectric layer 14 (second dielectric layer 14) covering the functional layer 15 may be disposed between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16.

Further, the dielectric layer 14 may also cover both a portion of the surface of the first electrode 12 and a portion of the surface of the second electrode 17 between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16. The two ends of the dielectric layer 14 may be respectively connected to the sidewalls of the first upper adhesion and barrier layer 13 and the sidewalls of the second upper adhesion and barrier layer 16. Therefore, the supporting effect of the first electrode 12 and the second electrode 17 on the dielectric layer 14 can be utilized to avoid the dielectric layer 14 from causing excessive pressure on the copper oxide nanowire functional layer 15 in the groove, and the structural stability of the device is enhanced.

In an alternative embodiment, the dielectric layer 14 may not be provided between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16, so that a window (refer to the opening 22 in fig. 9) communicating with the outside is formed above the functional layer 15 between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16. In this way, the window structure located above the copper oxide nanowire 24 and the cavity 19 structure located below the copper oxide nanowire 24 can be combined to form a gas convection channel, so as to further enhance the sensing effect and accuracy of the copper oxide nanowire 24 on the external gas.

In a preferred embodiment, the first upper adhesion and barrier layer 13 material and/or the second upper adhesion and barrier layer 16 material may be fabricated using a stack of Ta and TaN materials.

Further, the thickness of the Ta layer material in the first upper adhesion and barrier layer 13 and/or the second upper adhesion and barrier layer 16 may be 10 to 20nm, and the thickness of the TaN layer material may be 30 to 100nm.

In a preferred embodiment, the dielectric layer 14 material may comprise a low dielectric constant material. For example, the dielectric layer 14 material may comprise a low dielectric constant material such as SiCOH.

In other alternative embodiments, the dielectric layer 14 material may comprise a light transmissive material.

In a preferred embodiment, the upper surface of the dielectric layer 14 is flush with the upper surface of the first upper adhesion and barrier layer 13 and the upper surface of the second upper adhesion and barrier layer 16.

In a preferred embodiment, the top surface of the dielectric layer 14 may be lower than the top surface of the first top adhesion and barrier layer 13 and lower than the top surface of the second top adhesion and barrier layer 16.

The following describes a fabrication method of a storage device according to the present invention in detail with reference to the accompanying drawings and the detailed description.

Please refer to fig. 2. The preparation method of the sensory storage device can be used for preparing the sensory storage device and comprises the following steps:

step S1: a substrate is provided.

Please refer to fig. 3. In a preferred embodiment, the substrate 10 may be a conventional semiconductor substrate 10, such as a silicon substrate 10 that has been completed with all or part of a CMOS front end process. Also, the silicon substrate 10 after all or a portion of the CMOS front-end process is completed may be cleaned and dried to provide a clean silicon substrate 10 suitable for subsequent fabrication steps compatible with the CMOS back-end process, as described below.

Step S2: a first dielectric layer is formed on a substrate.

Please refer to fig. 4. In a preferred embodiment, the first dielectric layer 20 is grown on the surface of the silicon substrate 10 using a chemical vapor deposition technique.

In a preferred embodiment, the first dielectric layer 20 may be formed using conventional interlevel dielectric layer 14 materials.

Further, the first dielectric layer 20 may use a low dielectric constant material. For example, the first dielectric layer 20 may be made using low dielectric constant SiCOH.

And step S3: two first trenches reaching the surface of the substrate are formed on the first dielectric layer.

Please refer to fig. 5. In a preferred embodiment, two first trenches 21 may be etched on the surface of the first dielectric layer 20 by using uv lithography and etching techniques, and the lower ends of the first trenches 21 reach and stop on the upper surface of the silicon substrate 10 under etching control, so that the upper surface of the silicon substrate 10 is exposed on the bottom surfaces of the first trenches 21.

Two first trenches 21 are formed juxtaposed on the surface of the silicon substrate 10. Wherein the respective dimensions of the two first trenches 21 define the pattern dimensions of the two electrodes (the first electrode 12 and the second electrode 17) of the sensing calculation device. The distance between the two first trenches 21 defines the size of the functional layer 15 on the storage device connecting between the two electrodes.

And step S4: a lower adhesion and barrier layer is formed on the substrate surface exposed at the bottom of each first trench.

Please refer to fig. 6. In a preferred embodiment, the adhesion of the electrodes and the deposition of the barrier layer in the first trenches 21 may be performed using physical vapor deposition techniques. Thereby forming a first lower adhesion and barrier layer 11 on the surface of the silicon substrate 10 exposed at the bottom surface of one of the first trenches 21 and a second lower adhesion and barrier layer 18 on the surface of the silicon substrate 10 exposed at the bottom surface of the other one of the first trenches 21.

In a preferred embodiment, the first lower adhesion and barrier layer 11 material and the second lower adhesion and barrier layer 18 material may be fabricated using a stack of Ta and TaN materials. Namely, the Ta adhesion layer is deposited on the bottom surface of the first trench 21, and then the TaN barrier layer is deposited on the Ta adhesion layer, and the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 having a stacked structure are formed by the Ta adhesion layer and the TaN barrier layer.

In a preferred embodiment, the Ta adhesion layer may be 10-20nm thick and the TaN barrier layer may be 30-100 nm thick.

Step S5: an electrode is formed in each of the first trenches over each of the lower adhesion and barrier layers.

Please refer to fig. 7. In a preferred embodiment, the physical vapor deposition technique may be continued to grow an electrode metal on the first lower adhesion and barrier layer 11 and on the second lower adhesion and barrier layer 18 respectively located in the two first trenches 21 and fill the first trenches 21 to form the first electrode 12 on the first lower adhesion and barrier layer 11 and, at the same time, form the second electrode 17 on the second lower adhesion and barrier layer 18.

Please refer to fig. 8. In a preferred embodiment, the deposited electrode metal may be planarized by CMP techniques to remove excess electrode metal outside the first trench 21 and to make the surface of the first electrode 12 and the surface of the second electrode 17 flush with the surface of the first dielectric layer 20.

In a preferred embodiment, the electrode metal may be deposited using copper metal. That is, the first electrode 12 and the second electrode 17 may be formed using a metallic copper preparation (a first copper electrode and a second copper electrode).

In a preferred embodiment, the thickness of the first electrode 12 and the second electrode 17 may be 300-1000 nm.

Step S6: an upper adhesion and barrier layer is formed on the upper surface of each electrode.

Please refer to fig. 9. In a preferred embodiment, the adhesion of the electrodes and the deposition of the barrier layer may be performed using uv lithography and physical vapor deposition techniques. Thereby forming a patterned first upper adhesion and barrier layer 13 on the surface of the first electrode 12 and a patterned second upper adhesion and barrier layer 16 on the surface of the second electrode 17.

In a preferred embodiment, the first upper adhesion and barrier layer 13 material and the second upper adhesion and barrier layer 16 material may be fabricated using a stack of Ta and TaN materials. That is, a Ta adhesion layer is deposited on the surface of the first electrode 12 and the surface of the second electrode 17, and then a TaN barrier layer is deposited on the Ta adhesion layer, thereby further forming a first upper adhesion and barrier layer 13 pattern and a second upper adhesion and barrier layer 16 pattern having a stacked structure, which are composed of the Ta adhesion layer and the TaN barrier layer.

In a preferred embodiment, the width of the opening 22 (window) between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16 is made larger than the distance between the first electrode 12 and the second electrode 17 (i.e., the width dimension of the first dielectric layer 20).

Step S7: and removing the first dielectric layer material between the two first trenches to form a second trench reaching the surface of the substrate and expose the side walls of the two opposite electrodes.

Please refer to fig. 10. In a preferred embodiment, an etching technique may be used to selectively remove the material of the first dielectric layer 20 between the two first trenches 21, thereby forming a second trench 23 (corresponding to the trench in fig. 1) structure between the first electrode 12 and the second electrode 17, and between the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18.

After removing the material of the first dielectric layer 20 between the two first trenches 21, the lower end of the formed second trench 23 reaches the upper surface of the silicon substrate 10, i.e. the upper surface of the silicon substrate 10 is exposed on the bottom surface of the second trench 23.

Meanwhile, the sidewalls of the second trench 23 are formed by both opposite sidewalls of the first and

second electrodes

12 and 17 and both opposite sidewalls of the first and second lower adhesion and barrier layers 11 and 18. That is, two opposite sidewalls of the first electrode 12 and the second electrode 17 are exposed on the sidewalls of the second trench 23, and two opposite sidewalls of the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 are also exposed on the sidewalls of the second trench 23.

Step S8: an oxide nanowire functional layer of electrode metal suspended between opposing sidewalls of the two electrodes is formed in the second trench.

Please refer to fig. 11. In a preferred embodiment, a thermal oxidation technique may be used to form copper oxide nanowires 24 between two opposite sidewalls of the first electrode 12 and the second electrode 17 made of metal copper material, as the functional layer 15 of the memristor.

Wherein, in the process of performing thermal oxidation on the first electrode 12 and the second electrode 17, the copper oxide nanowire 24 grown from the surface of the sidewall of the first electrode 12 in the second trench 23 grows toward the sidewall of the second electrode 17 in the second trench 23; meanwhile, the copper oxide nanowire 24 grown from the surface of the sidewall of the second electrode 17 in the second trench 23 will also grow toward the sidewall of the first electrode 12 in the second trench 23. In this way, the copper oxide nanowires 24 grown in the opposite direction are inserted, wound, and contacted with each other, thereby forming an interlaced structure having air gaps. A connection is formed between the first electrode 12 and the second electrode 17 by the grown copper oxide nanowire 24 as the functional layer 15.

And, the first lower adhesion and barrier layer 11 and the second lower adhesion and barrier layer 18 which are arranged below the first electrode 12 and the second electrode 17 raise the height position of the first electrode 12 and the second electrode 17 in the second trench 23, so that the grown copper oxide nanowire 24 is suspended in the second trench 23, and a cavity 19 structure is formed between the copper oxide nanowire functional layer 15 and the upper surface of the silicon substrate 10.

Further, the method can further comprise the step S9: and forming a second dielectric layer covering the functional layer between the two upper adhesion and barrier layers.

Please refer to fig. 12. In a preferred embodiment, a second dielectric layer 14 (corresponding to dielectric layer 14 in fig. 1) is deposited and planarized in the opening between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16 using a chemical vapor deposition technique. The second dielectric layer 14 is formed to cover the surface of the functional layer 15, and a part of the surface of the first electrode 12 and a part of the surface of the second electrode 17.

The upper surface of the second dielectric layer 14 may also be made lower than the upper surface of the first upper adhesion and barrier layer 13 and lower than the upper surface of the second upper adhesion and barrier layer 16 by etching back.

In a preferred embodiment, the second dielectric layer 14 may be formed using conventional interlevel dielectric layer 14 materials.

Further, the second dielectric layer 14 may be prepared using a low dielectric constant material. For example, the second dielectric layer 14 may be made using low dielectric constant SiCOH.

In an alternative embodiment, the second dielectric layer 14 material may comprise a light transmissive material.

In other embodiments, the step of depositing the second dielectric layer 14 may be omitted, and the opening 22 between the first upper adhesion and barrier layer 13 and the second upper adhesion and barrier layer 16 may be used as a window for the copper oxide nanowire 24 to communicate with the outside.

In conclusion, the memristor constructed based on the copper oxide nanowire 24 is combined with CMOS process materials, so that the integrated neural synapse device with the sensing and storing functions and the characteristics of being light and convenient and easy to prepare can be realized, and the method is expected to provide reference for breaking through the traditional von Neumann computing architecture in the future and has a wide application prospect.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims

1. A sensory computing device, comprising:

a substrate;

a first electrode and a second electrode provided in parallel on the substrate;

2. The memory device of claim 1, wherein a first lower adhesion and barrier layer is disposed between the substrate and the first electrode, a second lower adhesion and barrier layer is disposed between the substrate and the second electrode, and the functional layer is suspended over the substrate between the first lower adhesion and barrier layer and the second lower adhesion and barrier layer.

3. The perceptual computing device of claim 1 wherein a first upper adhesion and barrier layer is disposed on the upper surface of the first electrode, a second upper adhesion and barrier layer is disposed on the upper surface of the second electrode, and a dielectric layer covering the functional layer is disposed between the first upper adhesion and barrier layer and the second upper adhesion and barrier layer.

4. The sensory computing device of claim 1, wherein the first electrode metal and the second electrode metal comprise copper, and the oxide nanowires of the first electrode metal and the oxide nanowires of the second electrode metal comprise copper oxide nanowires.

5. The sensory computing device of claim 3, wherein the dielectric layer material comprises a low dielectric constant material.

6. A method of making a sensory computing device, comprising:

providing a substrate;

forming a first dielectric layer on the substrate;

forming two first trenches reaching the surface of the substrate on the first dielectric layer;

7. The method for manufacturing a sensory computation device according to claim 6, further comprising:

forming an upper adhesion and barrier layer on the upper surface of each of the electrodes; and

and forming a second dielectric layer covering the functional layer between the two upper adhesion and barrier layers.

8. The method of claim 6, wherein a copper electrode is formed in the first trench using a physical vapor deposition technique.

9. The method of fabricating an inductive computing device according to claim 8, wherein a functional layer of copper oxide nanowires is formed between opposing sidewalls of two of said copper electrodes using a thermal oxidation technique.

10. The fabrication method of a sensorial computational device according to claim 6, wherein a first dielectric layer of a low dielectric constant material is formed on the substrate using a chemical vapor deposition technique, and wherein the first trench is formed on the first dielectric layer using an ultraviolet lithography and etching technique.