CN115618801A - Cache consistency checking method and device and electronic equipment - Google Patents

Cache consistency checking method and device and electronic equipment Download PDF

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CN115618801A
CN115618801A CN202211527653.6A CN202211527653A CN115618801A CN 115618801 A CN115618801 A CN 115618801A CN 202211527653 A CN202211527653 A CN 202211527653A CN 115618801 A CN115618801 A CN 115618801A
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cache
attribute
verification
model
behavior
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CN115618801B (en
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李德建
赵毅强
刘亮
张启智
李雷
陈琦
周永忠
姜义初
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Tianjin University
Beijing Smartchip Microelectronics Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
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    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

The invention relates to the technical field of chips, and provides a cache consistency checking method, a cache consistency checking device and electronic equipment. The cache consistency checking method comprises the following steps: constructing a state machine model corresponding to a cache module according to a hardware state set of the cache module when executing a cache instruction; establishing a verification attribute according to the behavior characteristics of the state machine model under the cache consistency protocol; and inputting the state machine model and the verification attribute into a model detector based on a time automaton, and obtaining a cache consistency verification result according to the output of the model detector. The implementation mode provided by the invention improves the completeness of the simulation technology based on the test vector and the reliability of protocol level verification.

Description

Cache consistency checking method and device and electronic equipment
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a cache consistency checking method, a cache consistency checking apparatus, an electronic device, and a computer-readable storage medium.
Background
For data consistency verification of the cache module, researchers have conducted a series of studies. At present, most of mainstream researches are focused on a function simulation technology based on test vector generation, and a simulation experiment is developed by optimizing the generation of the test vector and simulating the actual operation process of a circuit so as to check whether the circuit has functional hidden dangers. The technology cannot cover the extreme state of the circuit, complete verification of the circuit function is difficult to carry out, meanwhile, tracing to the functional defects is difficult, and a more efficient and complete verification means needs to be further explored. In addition, the verification aiming at the data consistency is mostly expanded at the protocol level and cannot go deep into the bottom layer hardware, and the risk that the bottom layer hardware has hidden danger and cannot be verified exists. Formal Verification (Formal Verification) is a Verification technology based on mathematical reasoning, can completely prove whether a system meets certain properties and specifications, and is suitable for full Verification of a cache module to ensure data consistency of the cache module.
The existing cache verification technology excessively depends on generation of test vectors, the test vectors are difficult to cover all running states of a circuit, and the detection capability for extreme situations of the circuit is lacked. The existing verification facing the cache consistency is concentrated on a protocol level, does not relate to the verification of bottom hardware, and has the risk of missing detection.
Disclosure of Invention
The embodiment of the invention aims to provide a cache consistency checking method, a cache consistency checking device and electronic equipment.
In order to achieve the above object, a first aspect of the present invention provides a cache consistency checking method, including: constructing a state machine model corresponding to a cache module according to a hardware state set of the cache module when executing a cache instruction; establishing a verification attribute according to the behavior characteristics of the state machine model under the cache consistency protocol; and inputting the state machine model and the verification attribute into a model detector based on a time automaton, and obtaining a cache consistency verification result according to the output of the model detector.
Preferably, constructing a state machine model corresponding to the cache module according to a hardware state set of the cache module when executing the cache instruction includes: acquiring circuit elements in the cache module and an association relation between the circuit elements; constructing a state space of the cache module according to the state of each circuit element and the incidence relation; and generating a corresponding state machine model according to the states in the state space and the transfer conditions and the control relation among the states.
Preferably, the establishing of the verification attribute according to the behavior characteristics of the state machine model under the cache coherence protocol includes: determining a state space of a circuit element related to a cache coherence protocol and the circuit element according to the expression form of the cache module under the state machine model; extracting the synchronous communication relation of data and states among the circuit elements according to a cache consistency protocol to form a cache verification network; and expressing the attribute of the behavior characteristic of the cache module as a verification attribute.
Preferably, expressing the attribute of the behavior feature of the cache module as a verification attribute includes: acquiring the attribute of the behavior characteristic expressed by the natural language; converting the attribute of the behavior feature expressed in the natural language into a behavior attribute expressed in a formal language; and taking the behavior attribute expressed by the formal language as the verification attribute.
Preferably, the converting the attribute of the behavior feature expressed in the natural language into the behavior attribute expressed in the formal language includes: and converting the attribute of the behavior characteristic expressed in the natural language into the behavior attribute expressed in the formal language through a natural language parser.
Preferably, the model detector based on the temporal automaton includes: the editor is configured to edit the model and perform system declaration and model declaration; the simulator is configured to simulate the established model and output a simulation result; and a validator configured to validate the property that the model should satisfy.
In a second aspect of the present invention, there is also provided a cache coherence checking apparatus, including: the model building module is used for building a state machine model corresponding to the cache module according to the hardware state set of the cache module when executing the cache instruction; the attribute construction module is used for constructing a verification attribute according to the behavior characteristics of the state machine model under the cache consistency protocol; and the verification execution module is used for inputting the state machine model and the verification attribute into a model detector based on a time automaton and obtaining a cache consistency verification result according to the output of the model detector.
Preferably, constructing a state machine model corresponding to the cache module according to a hardware state set of the cache module when executing the cache instruction includes: acquiring circuit elements in the cache module and an incidence relation between the circuit elements; constructing a state space of the cache module according to the state of each circuit element and the incidence relation; and generating a corresponding state machine model according to the states in the state space and the transfer conditions and the control relation among the states.
Preferably, the constructing of the verification attribute according to the behavior characteristics of the state machine model under the cache coherence protocol includes: determining a state space of a circuit element and a cache coherence protocol related circuit element according to the expression form of the cache module under the state machine model; extracting the synchronous communication relation of data and states among the circuit elements according to a cache consistency protocol to form a cache verification network; and expressing the attribute of the behavior characteristic of the cache module as a verification attribute.
Preferably, the expressing the attribute of the behavior feature of the cache module as a verification attribute includes: acquiring the attribute of the behavior characteristic expressed by the natural language; converting the attribute of the behavior characteristic expressed in the natural language into a behavior attribute expressed in a formal language; and taking the behavior attribute expressed by the formal language as the verification attribute.
Preferably, the converting the attribute of the behavior feature expressed in the natural language into the behavior attribute expressed in the formal language includes: and converting the attribute of the behavior feature expressed in the natural language into the behavior attribute expressed in the formal language through a natural language parser.
Preferably, the model detector based on the temporal automaton includes: the editor is configured to edit the model and perform system declaration and model declaration; the simulator is configured to simulate the established model and output a simulation result; and a validator configured to validate the property that the model should satisfy.
In a third aspect of the present invention, there is also provided an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the foregoing cache consistency checking method when executing the computer program.
In a fourth aspect of the present invention, there is also provided a computer-readable storage medium having stored therein instructions which, when run on a computer, cause the computer to perform the steps of the aforementioned cache coherence checking method.
In a fifth aspect the present invention provides a computer program product comprising a computer program which, when executed by a processor, implements the aforementioned cache coherence checking method.
The technical scheme at least has the following beneficial effects:
(1) The circuit formal model is constructed based on the finite state machine principle, all states and state transition relations of the circuit can be described in detail, and the simulation method is more complete than a general simulation technology based on a test vector.
(2) The method can be deeply combined with the hardware design of a cache circuit, can realize verification from the bottom layer, and is more reliable than the existing protocol level verification.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention and not to limit the embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating steps of a cache coherence checking method according to an embodiment of the present invention;
FIG. 2 is a logic diagram that schematically illustrates a method for cache coherency verification, in accordance with an embodiment of the present invention;
FIG. 3 is a diagram schematically illustrating a dual-core two-level cache processor according to an embodiment of the present invention;
FIG. 4 schematically illustrates a discrete mapping of a natural language to a logical language, according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a cache consistency check apparatus according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 schematically shows a step diagram of a cache consistency checking method according to an embodiment of the present invention. As shown in fig. 1, a cache coherence checking method includes:
s01, constructing a state machine model corresponding to a cache module according to a hardware state set of the cache module when the cache module executes a cache instruction; namely, according to the connection relation between storage elements such as triggers and the like in a cache circuit, a Boolean satisfiability algorithm is adopted to construct a state space model, and according to the state transition relation, an algorithm is extracted to extract transition conditions and control relations between states, so that the overall construction of a circuit formalized model is realized.
S02, establishing a verification attribute according to the behavior characteristics of the state machine model under the condition of a cache consistency protocol; analyzing the expression form of the cache circuit under the finite state machine, positioning the register and the state space related to the cache consistency protocol, and extracting the synchronous communication relation of data and states between all levels of caches according to the MESI cache consistency protocol to form a cache verification network of the multi-core processor system. The verification attribute is constructed by adopting a formal language, and further, the construction of a verification attribute library of cache consistency is realized. If the attributes in the protocol are expressed by adopting the natural language, the attributes of the natural language can be converted into the attributes of the formal language through the natural language parser.
And S03, inputting the state machine model and the verification attribute into a model detector based on a time automaton, and obtaining a cache consistency verification result according to the output of the model detector. And inputting the finite state machine model of the cache module and the cache consistency verification attribute into a model detector to complete verification of the data consistency of the cache module. The model detector is preferably an automatic model detector UPPAAL, and model state space is searched through an analysis means based on a time automaton and a verification attribute query of logic semantics, so that cache consistency verification is completed.
Fig. 2 schematically shows a logic diagram of a cache coherence checking method according to an embodiment of the present invention. As shown in fig. 2, the cache module circuit implements modeling and attribute extraction by a Finite State Machine (FSM), respectively, to obtain a cache module circuit formal model and a cache consistency verification attribute, and inputs the two into a verifier to complete cache consistency verification.
Through the implementation mode, circuit formal model construction can be carried out based on the finite-state machine principle, and the circuit formal model construction can be deeply combined with the circuit hardware design of the storage module, so that the verification efficiency and the verification accuracy are improved.
In some optional embodiments provided by the present invention, constructing a state machine model corresponding to a cache module according to a hardware state set of the cache module when executing a cache instruction includes: acquiring circuit elements in the cache module and an incidence relation between the circuit elements; constructing a state space of the cache module according to the state of each circuit element and the incidence relation; and generating a corresponding state machine model according to the states in the state space and the transfer conditions and the control relation among the states. Taking a trigger of a main circuit element of a circuit of a cache module as an example, determining a state space of the cache module according to a trigger state of the trigger and a connection relation thereof, wherein the state space is a set of all possible states of a circuit formal model corresponding to the cache module, and constructing a state machine model according to the state space.
In some optional embodiments provided by the present invention, the constructing a verification attribute according to the behavior feature of the state machine model under the cache coherence protocol includes: determining a state space of a circuit element related to a cache coherence protocol and the circuit element according to the expression form of the cache module under the state machine model; extracting the synchronous communication relation of data and states among the circuit elements according to a cache consistency protocol to form a cache verification network; and expressing the behavior attribute of the cache module as a verification attribute. Cache coherency protocols are used to ensure that data in cache memory is the same mechanism as data in main memory in computer systems employing hierarchical memory systems. Each Cache line in a Cache module (Cache) of a single core has 2 flags: dirty and valid flags that better describe the data relationship between the cache module and memory, such as whether the data is valid and whether the data is modified. In a multi-core processor, multiple cores may share some data, and the MESI protocol contains states describing the sharing. In the MESI protocol, each Cache line has 4 states, which can be represented by 2 bits, and they are respectively: m (Modified): the data is valid, the data is modified and is inconsistent with the data in the memory, and the data only exists in the Cache. E (Exclusive): the data is valid, the data is consistent with the data in the memory, and the data only exists in the Cache. S (Shared): the data is valid, the data is consistent with the data in the memory, and the data exists in a plurality of caches. And I (Invalid): this line is invalidated. The multi-core processing system has a plurality of levels of cache modules, and data and states between the cache modules at all levels have a synchronous communication relation, which forms a constraint condition of a single cache module. Under the constraint, its corresponding state is determined from within the state space. The state is expressed by the behavior attribute, and constitutes an attribute for verification in the subsequent step.
In some optional embodiments provided by the present invention, expressing the attribute of the behavior feature of the cache module as a verification attribute includes: acquiring the attribute of the behavior characteristic expressed by the natural language; converting the attribute of the behavior feature expressed in the natural language into a behavior attribute expressed in a formal language; and taking the behavior attribute expressed by the formal language as the verification attribute. Expressing behavior attributes in natural language, although easy to understand, is difficult for machines to recognize, and thus it is necessary to convert behavior attributes expressed in natural language into behavior attributes expressed in the formal language. The specific form of the converted formalized language depends on the input format of the subsequent model detector, subject to which the model detector can recognize.
In some optional embodiments provided herein, converting the attribute of the behavioral characteristic expressed in the natural language into a behavioral attribute expressed in a formal language includes: and converting the attribute of the behavior feature expressed in the natural language into the behavior attribute expressed in the formal language through a natural language parser. The manual creation of the attribute library is a time-consuming and error-prone project, the conversion between the expression forms of the behavior attributes in the previous embodiment is optimized in the embodiment, and the natural language attributes are converted into the formal language through a natural language processing tool, so that the conversion efficiency is improved.
In some alternative embodiments provided herein, the model detector is a temporal automaton model, comprising: the editor is configured to edit the model and perform system declaration and model declaration; the simulator is configured to simulate the established model and output a simulation result; and a validator configured to validate the property that the model should satisfy. The model detector can select existing tool software, such as an automatic model detector UPPAAL, and complete verification of data consistency of the cache module is completed by searching a model state space through a verification attribute query based on an analysis means and logic semantics of a time automaton.
The following embodiments take a dual-core two-level cache processor as an example, and verify the cache function of the processor. FIG. 3 is a diagram schematically illustrating a dual-core two-level cache processor according to an embodiment of the present invention. As shown in fig. 3, the following is implemented according to the foregoing embodiment:
step 1, constructing a global formalized model of the cache circuit based on a finite-state machine. Taking the flip-flops commonly found in the cache as an example, the state of the circuit and the state transition relation are extracted according to the state of each flip-flop.
And 2, constructing corresponding verification attributes based on the hardware behavior characteristics of cache consistency. According to the MESI cache coherence protocol, the cache line of the L1cache has the following four states: m (modify), E (exclusive), S (shared), I (invalid). Therefore, the states in which cache lines corresponding to L1 caches of two CPU cores are allowed to exist are shown in table 1 below (x represents that two cache lines are not allowed to be in a corresponding state at the same time, and v represents that two cache lines are not allowed to be in a corresponding state at the same time).
M E S I
M × × × √
E × × × √
S × × √ √
I √ √ √ √
TABLE 1
Taking the case that cache lines corresponding to the L1 caches of the two CPU cores cannot be in the M state at the same time, the description is made by using natural language as follows:
If CPU1_L1cache_state is ‘M’，
then a value of ‘M’ on signal CPU2_L1cache_state is not permitted。
however, the above natural language cannot be used for attribute verification, and needs to be converted into a formal language. And performing automatic semantic analysis aiming at the expression mode of the common attributes of the cache consistency verification, analyzing the discrete mapping relation from the natural language to the logic language, realizing the automatic generation of the cache consistency verification attributes in the logic semantic environment, and finally forming a logic language verification attribute library for the cache consistency verification.
FIG. 4 schematically illustrates a discrete mapping of a natural language to a logical language, according to an embodiment of the invention. As shown in fig. 4, the natural language is analyzed from the hardware hierarchy, and for example, the state of the L1cache of the CPU1 is represented by CPU1_ L1cache _ state, and the definition parameter M =11 is a Modify state. Attributes described in the SVA-based formalization language: CPU1_ L1cache _ state = = M | - > CPU2_ L1cache _ state | = = M. All attributes are described by natural language and converted into formalized language, and a verification attribute library of cache consistency is constructed.
And 3, realizing cache consistency verification based on an automatic model detector. Inputting a finite-state machine model of a cache module and cache consistency verification attributes into an automatic model detector UPPAAL, searching a model state space through an analysis means based on a time automaton and verification attribute query of logic semantics, and completing complete verification of data consistency of the cache module.
Based on the same inventive concept, the invention also provides a cache consistency checking device. Fig. 5 is a schematic structural diagram of a cache consistency check apparatus according to an embodiment of the present invention, and as shown in fig. 5, the cache consistency check apparatus includes: the model building module is used for building a state machine model corresponding to the cache module according to the hardware state set of the cache module when executing the cache instruction; the attribute construction module is used for constructing a verification attribute according to the behavior characteristics of the state machine model under the cache consistency protocol; and the verification execution module is used for inputting the state machine model and the verification attribute into a model detector based on a time automaton and obtaining a cache consistency verification result according to the output of the model detector.
In some optional embodiments, constructing a state machine model corresponding to the cache module according to a hardware state set of the cache module when executing the cache instruction includes: acquiring circuit elements in the cache module and an association relation between the circuit elements; constructing a state space of the cache module according to the state of each circuit element and the incidence relation; and generating a corresponding state machine model according to the states in the state space and the transfer conditions and the control relation among the states.
In some optional embodiments, constructing the validation attribute according to the state machine model under a cache coherence protocol-based behavior feature comprises: determining a state space of a circuit element related to a cache coherence protocol and the circuit element according to the expression form of the cache module under the state machine model; extracting the synchronous communication relation of data and states among the circuit elements according to a cache consistency protocol to form a cache verification network; and expressing the attribute of the behavior characteristic of the cache module as a verification attribute.
In some optional embodiments, expressing the attribute of the behavior feature of the cache module as a verification attribute comprises: acquiring the attribute of the behavior characteristic expressed by the natural language; converting the attribute of the behavior characteristic expressed in the natural language into a behavior attribute expressed in a formal language; and taking the behavior attribute expressed by the formal language as the verification attribute.
In some alternative embodiments, converting the attribute of the behavioral characteristic expressed in the natural language into a behavioral attribute expressed in a formal language includes: and converting the attribute of the behavior feature expressed in the natural language into the behavior attribute expressed in the formal language through a natural language parser.
In some alternative embodiments, the model detector is a temporal automaton model comprising: the editor is configured to edit the model and perform system declaration and model declaration; the simulator is configured to simulate the established model and output a simulation result; and a validator configured to validate the property that the model should satisfy. .
For the specific limitations of each functional module in the cache consistency check apparatus, reference may be made to the limitations of the cache consistency check method described above, and details are not described herein again. The various modules in the above-described apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent of a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In some embodiments of the present invention, an electronic device is further provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the aforementioned cache consistency checking method when executing the computer program. The processor herein has functions of numerical calculation and logical operation, and it has at least a central processing unit CPU having data processing capability, a random access memory RAM, a read only memory ROM, various I/O ports, an interrupt system, and the like. The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. One or more than one kernel can be set, and the method is realized by adjusting kernel parameters. The memory may include volatile memory in a computer readable medium, random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
In an embodiment of the present invention, there is also provided a computer-readable storage medium having stored therein instructions which, when executed on a computer, cause the processor to be configured to perform the steps of the above-described cache coherence checking method when executed by the processor.
In one embodiment provided by the present invention, a computer program product is provided, which comprises a computer program that, when being executed by a processor, implements the steps of the above-mentioned cache coherence checking method.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (14)

1. A method for cache coherency checking, the method comprising:
constructing a state machine model corresponding to a cache module according to a hardware state set of the cache module when executing a cache instruction;
establishing a verification attribute according to the behavior characteristics of the state machine model under the cache consistency protocol;
and inputting the state machine model and the verification attribute into a model detector based on a time automaton, and obtaining a cache consistency verification result according to the output of the model detector.
2. The method according to claim 1, wherein constructing the state machine model corresponding to the cache module according to the hardware state set of the cache module when executing the cache instruction comprises:
acquiring circuit elements in the cache module and an incidence relation between the circuit elements;
constructing a state space of the cache module according to the state of each circuit element and the incidence relation;
and generating a corresponding state machine model according to the states in the state space and the transfer conditions and the control relation among the states.
3. The method of claim 2, wherein constructing the validation attributes from the state machine model based on behavior characteristics of a cache coherence protocol comprises:
determining a state space of a circuit element and a cache coherence protocol related circuit element according to the expression form of the cache module under the state machine model;
extracting the synchronous communication relation of data and states among the circuit elements according to a cache consistency protocol to form a cache verification network;
and expressing the attribute of the behavior characteristic of the cache module as a verification attribute.
4. The method of claim 3, wherein expressing the attribute of the behavior feature of the cache module as a verification attribute comprises:
acquiring the attribute of the behavior characteristic expressed by the natural language;
converting the attribute of the behavior feature expressed in the natural language into a behavior attribute expressed in a formal language;
and taking the behavior attribute expressed by the formal language as the verification attribute.
5. The method of claim 4, wherein converting the attributes of the behavioral features expressed in the natural language into the behavioral attributes expressed in the formal language comprises:
and converting the attribute of the behavior feature expressed in the natural language into the behavior attribute expressed in the formal language through a natural language parser.
6. The method of claim 1, wherein the model detector based on temporal automata comprises:
the editor is configured to edit the model and perform system declaration and model declaration;
the simulator is configured to simulate the established model and output a simulation result; and
a validator configured to validate a property that the model should satisfy.
7. A cache coherency checking apparatus, the apparatus comprising:
the model building module is used for building a state machine model corresponding to the cache module according to the hardware state set of the cache module when the cache module executes the cache instruction;
the attribute construction module is used for constructing a verification attribute according to the behavior characteristics of the state machine model under the cache consistency protocol; and
and the verification execution module is used for inputting the state machine model and the verification attribute into a model detector based on a time automaton and obtaining a cache consistency verification result according to the output of the model detector.
8. The apparatus according to claim 7, wherein constructing the state machine model corresponding to the cache module according to the hardware state set of the cache module when executing the cache instruction comprises:
acquiring circuit elements in the cache module and an incidence relation between the circuit elements;
constructing a state space of the cache module according to the state of each circuit element and the incidence relation;
and generating a corresponding state machine model according to the states in the state space and the transfer conditions and the control relation among the states.
9. The apparatus of claim 8, wherein constructing verification attributes from the state machine model based on behavior characteristics of a cache coherence protocol comprises:
determining a state space of a circuit element and a cache coherence protocol related circuit element according to the expression form of the cache module under the state machine model;
extracting the synchronous communication relation of data and states among the circuit elements according to a cache consistency protocol to form a cache verification network;
and expressing the attribute of the behavior characteristic of the cache module as a verification attribute.
10. The apparatus of claim 9, wherein expressing the attribute of the behavior feature of the caching module as a verification attribute comprises:
acquiring the attribute of the behavior characteristic expressed by the natural language;
converting the attribute of the behavior feature expressed in the natural language into a behavior attribute expressed in a formal language;
and taking the behavior attribute expressed by the formal language as the verification attribute.
11. The apparatus of claim 10, wherein transforming the attributes of the behavioral features expressed in the natural language into behavioral attributes expressed in a formal language comprises:
and converting the attribute of the behavior feature expressed in the natural language into the behavior attribute expressed in the formal language through a natural language parser.
12. The apparatus of claim 7, wherein the model detector based on a temporal automaton comprises:
the editor is configured to edit the model and perform system declaration and model declaration;
the simulator is configured to simulate the established model and output a simulation result; and
a validator configured to validate a property that the model should satisfy.
13. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the cache coherence checking method according to any one of claims 1 to 6 when executing the computer program.
14. A computer readable storage medium having stored therein instructions which, when run on a computer, cause the computer to perform the steps of the cache coherence checking method of any one of claims 1 to 6.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116070567A (en) * 2023-03-27 2023-05-05 北京燧原智能科技有限公司 Verification method, device and equipment of cache circuit and storage medium
CN116167310A (en) * 2023-04-25 2023-05-26 上海芯联芯智能科技有限公司 Method and device for verifying cache consistency of multi-core processor

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103150264A (en) * 2013-01-18 2013-06-12 浪潮电子信息产业股份有限公司 Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method
US20140236561A1 (en) * 2013-02-19 2014-08-21 International Business Machines Corporation Efficient validation of coherency between processor cores and accelerators in computer systems
CN105912415A (en) * 2016-04-05 2016-08-31 浪潮电子信息产业股份有限公司 Method and device for verifying cache consistency protocol
CN109062613A (en) * 2018-06-01 2018-12-21 杭州中天微系统有限公司 Multicore interconnects L2 cache and accesses verification method
CN110659172A (en) * 2019-09-11 2020-01-07 上海高性能集成电路设计中心 Instruction level checking method for microprocessor locking mechanism
CN110674055A (en) * 2019-09-11 2020-01-10 上海高性能集成电路设计中心 Cache consistency simulation verification method for component level and component combination level
CN110727611A (en) * 2019-09-09 2020-01-24 无锡江南计算技术研究所 Configurable consistency verification system with state monitoring function
CN112152795A (en) * 2020-08-11 2020-12-29 中国人民解放军战略支援部队信息工程大学 Security protocol code vulnerability mining method based on state machine consistency detection
CN113138721A (en) * 2021-04-30 2021-07-20 清华大学 Bypass attack vulnerability formal verification method and device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103150264A (en) * 2013-01-18 2013-06-12 浪潮电子信息产业股份有限公司 Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method
US20150095008A1 (en) * 2013-01-18 2015-04-02 Inspur Electronic Information Industry Co., Ltd Extension cache coherence protocol-based multi-level coherency domain simulation verification and test method
US20140236561A1 (en) * 2013-02-19 2014-08-21 International Business Machines Corporation Efficient validation of coherency between processor cores and accelerators in computer systems
CN105912415A (en) * 2016-04-05 2016-08-31 浪潮电子信息产业股份有限公司 Method and device for verifying cache consistency protocol
CN109062613A (en) * 2018-06-01 2018-12-21 杭州中天微系统有限公司 Multicore interconnects L2 cache and accesses verification method
CN110727611A (en) * 2019-09-09 2020-01-24 无锡江南计算技术研究所 Configurable consistency verification system with state monitoring function
CN110659172A (en) * 2019-09-11 2020-01-07 上海高性能集成电路设计中心 Instruction level checking method for microprocessor locking mechanism
CN110674055A (en) * 2019-09-11 2020-01-10 上海高性能集成电路设计中心 Cache consistency simulation verification method for component level and component combination level
CN112152795A (en) * 2020-08-11 2020-12-29 中国人民解放军战略支援部队信息工程大学 Security protocol code vulnerability mining method based on state machine consistency detection
CN113138721A (en) * 2021-04-30 2021-07-20 清华大学 Bypass attack vulnerability formal verification method and device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116070567A (en) * 2023-03-27 2023-05-05 北京燧原智能科技有限公司 Verification method, device and equipment of cache circuit and storage medium
CN116070567B (en) * 2023-03-27 2023-06-30 北京燧原智能科技有限公司 Verification method, device and equipment of cache circuit and storage medium
CN116167310A (en) * 2023-04-25 2023-05-26 上海芯联芯智能科技有限公司 Method and device for verifying cache consistency of multi-core processor

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