CN115617594B

CN115617594B - Method, apparatus, storage medium, and program product for generating incentive information

Info

Publication number: CN115617594B
Application number: CN202211589103.7A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Thread Intelligent Technology Chengdu Co ltd; Moore Threads Technology Co Ltd
Current assignee: Moore Thread Intelligent Technology Chengdu Co ltd; Moore Threads Technology Co Ltd
Priority date: 2022-12-12
Filing date: 2022-12-12
Publication date: 2023-03-14
Anticipated expiration: 2042-12-12
Also published as: CN115617594A

Abstract

The present disclosure relates to the field of chip verification technology, and provides a method, an apparatus, a computer-readable storage medium, and a computer program product for generating incentive information for chip verification. In order to generate the incentive information efficiently and completely, the method provided by the present disclosure comprises: acquiring user constraint information and system constraint information; generating query information which accords with user constraint information and system constraint information through a random engine; querying the database using the query information; and in response to obtaining the combined information matching the query information in the database, using the combined information as incentive information for chip verification.

Description

Method, apparatus, storage medium, and program product for generating incentive information

Technical Field

The present disclosure relates to the field of chip verification technologies, and in particular, to a computer-implemented method, apparatus, computer-readable storage medium, and computer program product for generating incentive information.

Background

In the verification process of the medium and large chips, excitation information is complex and various, and is difficult to construct, thus being not beneficial to maintenance and inspection. The current mechanism for generating the excitation information during the chip verification using the chip verification system includes:

first, incentive information is generated based on an Application (Application based): and generating the incentive information according to a constraint file (config-file) set by the application program to be tested. Such a mechanism requires a complete upper layer application program to be developed in a chip verification stage, such an application program requires a lot of manpower and is too high in time cost, and the integrity of the excitation information cannot be guaranteed by the excitation information generated by the upper layer application, in other words, it cannot be guaranteed that each function of the chip is tested.

Second, randomly (Random) generates excitation information: the incentive information is generated from a randomly generated constraint file (config-file). The mechanism has high randomness, can not ensure the legality of the excitation information (the legality in the disclosure means that the excitation information conforms to the requirement or rule of the excitation information so as to enable the excitation information to be effective), and increases the difficulty of verification and debugging. Third, excitation information is generated based on a Template (Template base): and generating the excitation information according to a constraint file (config-file) in the excitation information generating device template library. The constraint files in the template library comprise constraint files set according to basic function points of the chip to be verified and constraint files corresponding to excitation information with high influence on coverage rate improvement. The mechanism can only generate the excitation information based on the constraint file in the specific template, and can not dynamically adjust the generation of the excitation information according to the verified emphasis point of the module characteristic.

The chip verification is the most critical step in ensuring the chip quality, and in order to ensure that each function of the chip is verified, a set of system which can generate excitation information fast, efficiently and completely and meet requirements or rules is very important.

Disclosure of Invention

In view of this, according to a first aspect of the present disclosure, there is provided a method for generating incentive information for chip verification, the method comprising: acquiring user constraint information and system constraint information; generating query information which accords with user constraint information and system constraint information through a random engine; querying a database by using the query information, wherein the database comprises a table for storing a set of combined information corresponding to a plurality of items of legal incentive information, one item of combined information corresponds to one item of legal incentive information, and the combined information comprises an instruction type, an instruction function and an instruction characteristic of the corresponding legal incentive information; and in response to obtaining the combined information matched with the query information in the database, using the combined information as the excitation information of the chip verification.

According to a second aspect of the present disclosure, there is provided a computing device comprising: a processor; and a memory configured to have stored thereon computer-executable instructions that, when executed in the processor, cause the method as provided in the preceding aspect to be implemented.

According to a third aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium has stored therein computer-executable instructions, which, when executed on a computing device, cause the computing device to implement the method as provided by the preceding aspect.

According to a fourth aspect of the present disclosure, there is provided a computer program product comprising computer executable instructions which, when executed by a processor, cause the method as provided in the preceding aspect to be carried out.

According to the incentive information generation method based on the database, the inquiry of the database is faster and more efficient than the conventional key value pair inquiry mode, so that the incentive information can be generated more quickly and more efficiently.

These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Drawings

Further details, features and advantages of the disclosure are disclosed in the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 schematically illustrates an example application scenario in which the technical solution provided by the embodiments of the present disclosure may be applied;

FIG. 2 schematically illustrates an example flow diagram of preparation of a method for generating incentive information, in accordance with some embodiments of the present disclosure;

3a-3b schematically illustrate example flow diagrams of methods for generating incentive information, in accordance with some embodiments of the present disclosure; and

fig. 4 schematically illustrates an example block diagram of an apparatus according to some embodiments of this disclosure.

Detailed Description

Embodiments of the disclosed concept will now be described more fully with reference to the accompanying drawings. The presently disclosed concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Thus, the scope of the disclosed concept includes modifications, equivalents, adaptations, and alternatives to the illustrated embodiments. Like reference numbers and designations are used throughout the written description and drawings to refer to like or similar elements. In the drawings, certain dimensions, relative dimensions, and/or relative dimensions may be exaggerated for clarity.

Moreover, all examples and conditional language recited herein are to be construed as being without limitation to such specifically recited examples and conditions. Throughout this specification, the singular forms may include the plural forms unless there is a specific description to the contrary. Also, terms such as "comprising" or "includes" are used to specify the presence of stated tables, numbers, procedures, operations, components, and/or groups thereof, but do not preclude the presence or addition of one or more other stated tables, one or more other numbers, one or more other procedures, one or more other operations, one or more other components, and/or groups thereof.

Although the terms "first" and "second", etc. are used to describe various components, it is apparent that the components are not limited to the terms "first" and "second". The terms "first" and "second" are used merely to distinguish between each component. For example, a first component can be used interchangeably with a second component without conflicting with the disclosed concept.

Unless explicitly described herein, all terms used herein, including descriptive terms and technical terms, should be interpreted as having meanings apparent to those of ordinary skill in the art. Also, terms defined in a general dictionary and terms used in the following description should be construed to have meanings equivalent to those used in the related description, and the terms should not be construed as idealized or overly formal unless expressly so described herein.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When an expression such as at least one of is located after a list of elements, it will modify the entire list of elements rather than modifying individual elements of the list.

Fig. 1 schematically illustrates an example application scenario 100 in which technical aspects according to some embodiments of the present disclosure may be applied.

As shown in fig. 1, the scene 100 includes an incentive information generating apparatus 110. The method for generating incentive information provided by the present disclosure may be deployed in the incentive information generating apparatus 110. The user 120 may configure parameters, files, etc. involved in the method for generating motivational information through interactive operations. Illustratively, the incentive information generating apparatus 110 includes, but is not limited to, various computing devices. The specific structure of the excitation information generating device 110 will be described in detail later, and will not be described in detail here.

Further, the scenario 100 also includes a chip verification device 130. For example, the chip verification apparatus 130 may be independent of the incentive information generation apparatus 110, or may be the same physical device, device cluster or distributed system as the incentive information generation apparatus 110, and the incentive information generation apparatus 110 and the chip verification apparatus 130 may also be cloud devices providing basic cloud computing services such as cloud service, cloud database, cloud computing, cloud function, cloud storage, web service, cloud communication, middleware service, domain name service, security service, CDN, and big data and artificial intelligence platform.

The scenario 100 also includes a chip 140 to be verified. Chip 140 may be any functional, model, complexity chip.

In the present disclosure, the network 150 may be a wired network connected via, for example, a cable, an optical fiber, etc., or may be a wireless network such as 2G, 3G, 4G, 5G, wi-Fi, bluetooth, zigBee, li-Fi, etc., or may be an internal connection line of one or several devices, etc. In general, the excitation information generating apparatus 110 and the chip verification apparatus 130 independent therefrom may be connected through an arbitrary network, and the chip verification apparatus 130 and the chip 140 are more connected in a wired manner. The chip verification means 130 verifies the chip 140 using the excitation information generated by the excitation information generation means 110, and optionally, can also convert the generated excitation information into a format recognizable by the chip 140 before being supplied to the chip 140. The chip verification device 130 compares and verifies the operation result of the chip and the operation result of the chip verification device 130 itself to determine whether the function of the chip under test is correct.

Schematically, fig. 2 illustrates an example flow diagram of a preparation 200 of a method for generating incentive information according to some embodiments of the present disclosure. Illustratively, the preparation 200 of the method for generating motivational information may be applied to the scenario 100 shown in fig. 1, for example, the method may be performed by the motivational information generating device 110 alone. As shown, preparation 200 of a method for generating incentive information may include

steps

210 and 220, which may be implemented by various programs, routines, scripts, etc., such as Python scripts, etc. The details are as follows.

Referring to fig. 2, in step 210, information in the incentive instruction set is combined to generate a set of combined information corresponding to a plurality of items of legal incentive information (e.g., all pieces of legal incentive information), wherein each item of combined information includes an instruction type, an instruction function, and an instruction feature corresponding to one piece of legal incentive information. The stimulus instruction set is, as the name implies, a set of stimulus instructions, and chip verification is known to have standard rules concerning various instruction types, instruction functions, and instruction features, which are described in the stimulus instruction set. Typically, the stimulus Instruction Set is stored in a file, such as an Instruction Set Architecture (ISA) file, however, embodiments of the present disclosure are not so limited and the stimulus Instruction Set may be stored in any form and at any location.

In one embodiment, the set of composition information has version attributes such as version number, version time, version description, and the like.

In one embodiment, the set of portfolio information is represented in the form of an excel form. The form may include a version information page and an instruction information page in which version attributes and instruction types, instruction functions, instruction features, and the like of each combination information are respectively described.

Table 1 shown below is an example of an excel form version information page.

TABLE 1

Version number	Version description	Version time
			v1.0	1st version	2021.09.30

Table 2 shown below is an example of an excel form instruction information page.

TABLE 2

Table 2 includes two main columns: a column for the instruction type and a column for the field. Where the column for instruction types is represented in the form of "instruction type + '/' + instruction function," such as INST _ A/MTRCP, INST _ B/BR, etc.

The columns of the fields define the field segments each instruction has, i.e. understood as the characteristics of the instructions mentioned above. For example, the INST _ A instruction has fields of CC/SF/WDF/WNDF/DST REG/DST FMT/SRC REG/SRC FMT/SRC CHAN/SRC ABS/SRC NEG. I.e. INST _ a has the above 11 domain segments. The following description is made for each domain segment.

CC column: enumerated types defining selectable values for the INST _ A instruction CC field segment, such as 0XEX,0XE1,00E1,01E1.

SF column: an enumerated type of optional value, such as NDF/DF/NONE, is defined for the INST _ A instruction SF field segment.

WDF column: the range of selectable values of the WDF field segment of the INST _ A instruction is defined, wherein the range is represented from large to small, separated by a colon, and placed in middle brackets, for example [2:0] indicates that the selectable range is 0, 1, 2.

WNDF series: a range of selectable values of the WNDF field segment of the INST _ A instruction is defined, wherein the range is represented from large to small, separated by colons, and placed in middle brackets, and if [1:0] represents that the selectable range is 0 and 1.

DST _ REG column: a range of selectable values for the INST _ A instruction DST _ REG field segment, such as TEMPLATE/ATTRIBUTE/SL, is defined.

DST _ FMT column: a range of selectable values for the INST _ A instruction DST _ FMT field segment is defined, such as T32/T16T16.

SRC _ REG column: a range of selectable values, such as TEMPLATE/ATTRIBUTE/SL, for the SRC REG field segment of the INST _ A instruction is defined.

SRC _ FMT column: a range of selectable values for the INST _ A instruction SRC FMT field segment is defined, e.g., T32/T16T16.

CHAN is as follows: a range of selectable values, e.g., E0/E1, for the INST _ A instruction CHAN field segment is defined.

ABS column: a range of optional values, such as TRUE/FALSE, for the ABS field segment of the INST _ A instruction is defined.

NEG columns: a range of selectable values, such as TRUE/FALSE, for the INST _ A instruction NEG field segment is defined.

It is to be understood that the above-listed instruction types, instruction functions and instruction features are merely illustrative of the concepts of the present disclosure and that no specific function or meaning of these instructions is required, and thus, no detailed description of the specific function or meaning of the instructions is provided herein. In fact, there may be a variety of different instructions for different chips or chip vendors.

At step 220, the set of combined information is imported into a database to generate a table in the database. A database, as referred to in this disclosure, is a "repository that organizes, stores, and manages data according to a data structure" in the general sense of the art.

In one embodiment, the tables of the database also have version attributes. Optionally, the method 200 further comprises: and in response to the version attribute of the combined information set not being consistent with the version attribute of the table of the corresponding database, re-importing the combined information set into the database to generate a new table in the database. The new table may overwrite the original table or be a table independent of the original table, which is typically used for version upgrades. By including version attributes in the tables of the combined information and database, version management is facilitated.

When the query is implemented in a conventional manner, a corresponding key-value pair (key-value) structure is constructed for each query, for example, to query an instruction with an instruction name of fma, the following structure needs to be constructed:

{"fma": ["fma,None,None,TMP,TMP,TMP","fma,TMP,TMP,TMP,TMP,TMP"]}。

in the above structure, the key is preceded by a colon, and the contents of the two quotation marks following the colon are the two values of the key, respectively. Wherein fma in the first quote is instruction type, fma in the second and third quotes are both instruction functions (just renamed), the "None" and "TMP" in the second quote and third quote are the corresponding features, respectively, and the "TMP" in the third quote is also the corresponding feature. Of course, the above structure is only an example, the number of field segments of each instruction type may be different, that is, the corresponding characteristics are different, here, the instruction type having 5 field segments is exemplified, and there are actually more field segment instruction types. It is very complex if one such structure is created for each query, and if one is not created, all instructions must be traversed to implement the query, thereby necessarily reducing query efficiency.

The present disclosure can easily implement queries on complex conditions using a database to support queries on a variety of conditions, such as screening combinations of instructions that do not use slots when slots are disabled, or screening instructions that support a particular CC mode when CCs must be used.

Optionally, in one embodiment, the database has an encapsulated application program interface to enable operation of the database. For example, the database supports an Object Relational Mapping (ORM) framework, which encapsulates an operation program, facilitates calling, shields a bottom layer program from developers, and supports chained query, thereby simplifying the workload of development, and particularly for those skilled in the chip field, the operation program of the database does not need to be mastered specially, thereby realizing library building and table building operations more conveniently.

Optionally, in one embodiment, the database is a lightweight database. The database is stable and reliable, and the query speed is high. The motivational information generating device is implemented more as a gadget and runs locally than if a computationally powerful remote server and calls shared by users. The lightweight database can meet the requirements of local operation on stable, reliable and quick query, such as an open source lightweight database SQLite which is widely quoted.

The query of the database is faster and more efficient than the existing key-value pair query mode, so that the incentive information can be generated more quickly and more efficiently.

The design of the database table structure in one embodiment is described below with the table name LDMA as an example. First, define the LDMA data type, corresponding to the LDMA table in the database, whose Python-based script implementation is, for example:

class LDMA(Base):

__tablename__ = "ldma"

id = Column(String(64), primary_key = True)

pipeline = Column(String(64), default = "ldma")

op = Column(String(32))

……

the id can represent the combination of the instruction type and the instruction function, even the combination of some important instruction features, so that the query is convenient, the op represents the function of the instruction, and the pipeline represents the pipeline to which the instruction belongs. Of course, more fields corresponding to tables in the database are also included in the data structure, and are not listed here.

Alternatively, one table may be provided for each instruction type, each table defining a data structure as above. At the time of calling, a table of all inherited bases can be created, for example, by the following statements, thereby omitting the cumbersome table building statement:

Base.metadata.create_all(engine)。

after the database is ready, the generation of the incentive information may be based on the database.

Referring to fig. 3a, an example flow diagram 300a of a method for generating incentive information is shown, in accordance with some embodiments of the present disclosure. Therein, at step 230, user constraint information and system constraint information are obtained.

In one embodiment, the user constraint information and the system constraint information are both in the form of files, and configuration based on the system constraint information is supported to obtain the user constraint information. By the mode, the method is beneficial for developers to maintain and inspect the codes. In addition, the user constraint information is obtained by supporting configuration on the basis of the system constraint information, so that the user-defined constraint is realized, the configuration difficulty of the user on the user-defined constraint is reduced, and the user-defined constraint is directly modified on the basis of the system constraint information. Each data item of the system constraint information comprises a value range, a default value, a configuration switch and the like, and a user can reserve the format of the system constraint information and carry out constraint configuration on the value, the default value, the configuration switch and the like of the data item which is expected to be constrained.

Of course, the user constraint information in the embodiment of the present disclosure is not limited to only adopting a user-defined manner, and may also be a manner based on template generation.

In step 240, query information conforming to the user constraint information and the system constraint information is generated by a random engine, wherein the random engine referred to in this disclosure may also be referred to as a random number engine, a random number generator, or the like, and is used for assigning a value of a random object according to a random algorithm based on a random probability of each available value within an available value range of the random object. For example, when the random object is an instruction function, the instruction function has four available values, and a random engine may be used to determine one of the four available values. As another example, a random object may also be one or more instruction types, instruction features, or any combination of one or more instruction functions, instruction features, e.g., a random object may be a combination of instruction type A, instruction features B and C, and instruction functions D and E. The query information includes a random object, and a value available for the random object may be defined, for example, by user constraint information or system constraint information. Of course, the random object that the random engine can operate on is not limited to the above example, and any object with a constraint range (so the random object is also referred to as a constraint term in this disclosure, so step 240 can be described as determining a constraint term and determining an available value of the constraint term based on user constraint information and/or system constraint information, and then generating query information by the random engine based on the determined constraint term and the available value thereof) can randomly designate a value in the range as the value of the object by the random engine. As will be appreciated by those skilled in the art, the stochastic engine assigns the values of the random objects in such a way that for each available value of the random object, a random probability is assigned, from which a value is then assigned according to a stochastic algorithm.

In one embodiment, the random object included in the query information includes an instruction type, an instruction function, and an instruction feature, and the random engine supports a value of at least one of the instruction type, the instruction function, and the instruction feature to configure a weight, that is, to receive a weight, which is input by a user, an administrator, or the like through an input interface, or the like, for example, so as to determine a random probability of a corresponding value according to the weight. For example, the user may set a higher weight to 0XE1 of the INST _ a instruction CC field segment than to other selectable values, so that the probability of the 0XE1 value is increased when generating query information that matches the user constraint information and the system constraint information. For unconfigured weights, a default weight, such as 1, is used.

In one embodiment, in response to a constraint term being any one of an instruction type, the instruction function, and the instruction feature, generating, by the random engine, query information based on the constraint term and an available value thereof, includes: and acquiring the weight of each available value of the constraint item, wherein the weight comprises a configured weight and a default weight, and then generating query information by the random engine based on the constraint item and the weight of each available value of the constraint item.

In one embodiment, in response to a constraint being a combination of any of an instruction type, the instruction function, and the instruction feature, generating, by the random engine, query information based on the constraint and its available values, includes: calculating the weight of each available value of the constraint item, and then generating query information through the random engine based on the constraint item and the weight of each available value of the constraint item; wherein, calculating the weight of each available value of the constraint term comprises:

a set of weights for instruction type, instruction function and instruction characteristics in the available values for the constraint terms is determined, which, of course, includes configured and default weights,

step A: two weights in the set of weights are selected, a combined weight of the two weights is calculated using the following calculation formula, the two weights are then deleted from the set of weights, and the calculated combined weight is added.

And repeating the step A until only one combined weight exists in the set, and taking the only combined weight as the weight of the available value of the constraint item.

The above mentioned calculation formula is:

wc = (W1 x W2)/(W1 + W2), where Wc is the combining weight and W1 and W2 are the two weights selected from the set at a time.

According to the above calculation formula, for example, if the weight of one data item in a combination is 0, the weight of the combination should be 0, which ensures that 100% of the combination is not screened, and for example, if the weight of a single data item in a combination is linearly increased, the weight of the combination is also linearly increased.

The random engine supports that any combination of any number of instruction types, instruction functions and instruction features is used as a random object, the weight of the available value of the combination is calculated according to the weight of the available value of at least one of the instruction types, the instruction functions and the instruction features, and the random probability of the available value of the combination is determined according to the weight of the available value of the combination. In this way, it is advantageous for the random engine to specify values directly for a combination.

In one embodiment, the random engine supports setting a random number seed (random seed) which refers to an initial value used in the random engine to generate a random number. The same random number seed can correspond to the same randomly generated number, which is advantageous for achieving reproducibility of the value of the random object. This is advantageous for the desire to repeatedly test a piece of stimulus information that may, for example, cause problems during the verification of the chip.

At step 250, a table of the database is queried using the query information. An example of a complex query code, based on the sql allelchem framework in Python, is shown below:

query = session

if cond:

query = query filter (fop. Id. Like (". TMP")) # queries for instructions with TMP in operand

else：

query = query.filter (fop. Id. Like ("# None")) # queries for None in operand

All () # query all results

According to the above code, if cond is true, an entry with op = fmul and id containing TMP is selected from the inside of the FOP sheet, otherwise if cond is false, an entry with op = fmul and id containing None is selected.

In step 260, in response to obtaining the combined information matching the query information, the combined information is taken as the stimulus information for chip verification. For example, in the above query code example, if the result of result () return is not empty, the entry returned is the generated stimulus information.

The computer-implemented method for generating the incentive information based on the database can quickly and efficiently generate the incentive information, and is favorable for completely generating the incentive information because the combined information covers all legal incentive information.

Fig. 3b schematically illustrates another example flow diagram 300b of a method for generating incentive information, in accordance with some embodiments of the present disclosure. On the basis of the flowchart of fig. 3a, the following steps (which may be implemented by various programs, routines, or scripts, as with the steps of fig. 3 a) are executed at least once until a matching entry is obtained, or the maximum number of executions is reached:

in step 270, in response to that the combination information matching the query information is not obtained, that is, the result returned by result () in the above code example is null, generating new query information conforming to the user constraint information and the system constraint information using the random engine; and at step 280, the tables of the database are queried using the new query information.

In some embodiments, in step 270, the new query information is generated according to the following rule: the method comprises the steps of firstly regenerating at least one instruction feature in query information until all the instruction features are regenerated and then a query result cannot be obtained, secondly regenerating at least one instruction function in the query information until all the instruction functions are regenerated and then the query result cannot be obtained, and finally regenerating at least one instruction type in the query information until all the instruction types are regenerated and then the query result cannot be obtained.

Specifically, the order in which a piece of query information is generated is: first the instruction type, second the instruction function, and last the instruction feature. For example, for instruction type A, instruction function B and instruction features C1, C2 have been generated. In the query process, for example, when the query result is not obtained when the instruction feature C2 is generated, a step is backed off to regenerate the instruction feature C1 and then regenerate the instruction feature C2, if the query result is still not obtained, the step is backed off to the instruction function to regenerate the instruction function B and regenerate the instruction features C1 and C2, if the query result is still not obtained, the step is backed off to the instruction type to regenerate the instruction type a and regenerate the instruction function B and the instruction features C1 and C2, and so on until a matched entry, namely matched combination information, is obtained or the maximum execution number is reached. Each regeneration involves the use of a random engine, i.e., the random engine generation is used for the objects that need to be regenerated, as in step 240. The strategy can relieve or avoid invalid query generation, and is beneficial to querying matched items as soon as possible.

In some embodiments, the maximum number of executions is configured in a user constraint file, such as 3. If no matching entry is found after exceeding the maximum number of executions, an error may be reported in step 290.

In one embodiment, after the entry of the database is obtained, the obtained entry is also subjected to dependency processing in step 310, and the dependency processed entry is used as the incentive information for chip verification. In a first example, a determination is made as to whether execution of the generated incentive information is premised on a result of execution of one or more other incentive information (which may be referred to herein as a first set of incentive information), and in response to a yes determination, the generated incentive information and each of the first set of incentive information are correspondingly tagged such that the generated incentive information is executed after each of the first set of incentive information is executed. In a second example, a determination is made as to whether the result of the execution of the generated excitation information is a precondition for the execution of one or more other excitation information (referred to herein as a second set of excitation information), and in response to a yes determination, the generated excitation information and each excitation information of the second set of excitation information are correspondingly tagged such that each excitation information of the second set of excitation information is executed after the generated excitation information is executed. In a third example, the previous two examples are combined for operation. Specifically, for example, in the first example, one or more flags for the generated excitation information may be provided, the number of excitation information corresponding to the first excitation information set is counted, the flag type is a wait flag, for example, f1, f2 … …, and the flag type corresponding to each excitation information in the first excitation information set is a set flag, for example, f1, f2 … …, and corresponds to the wait flag.

It is understood that one incentive message may set a plurality of waiting flags to wait for a plurality of incentive messages that need to be previously executed.

Fig. 4 schematically illustrates an example block diagram of an apparatus 400 according to some embodiments of this disclosure. The apparatus 400 may represent, for example, the incentive information generating apparatus 110 of fig. 1.

As shown, the example apparatus 400 includes a processing system 401, one or more computer-readable media 402, and one or more I/O interfaces (input/output interfaces) 403 communicatively coupled to each other. Although not shown, the apparatus 400 may also include a system bus or other data and command transfer system that couples the various components to one another. A system bus can include any one or combination of different bus structures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and/or a processor or local bus that utilizes any of a variety of bus architectures, or that also includes data lines, such as control and data lines.

Processing system 401 represents functionality to perform one or more operations using hardware. Thus, the processing system 401 is illustrated as including hardware elements 404 that may be configured as processors, functional blocks, and so forth. This may include implementing an application specific integrated circuit or other logic device formed using one or more semiconductors in hardware. Hardware elements 404 are not limited by the materials from which they are formed or the processing mechanisms employed therein. For example, a processor may be comprised of semiconductor(s) and/or transistors (e.g., electronic Integrated Circuits (ICs)). In such a context, processor-executable instructions may be electronically-executable instructions.

The computer-readable medium 402 is illustrated as including memory/storage 405. Memory/storage 405 represents memory/storage associated with one or more computer-readable media. The memory/storage 405 may include volatile storage media (such as Random Access Memory (RAM)) and/or nonvolatile storage media (such as Read Only Memory (ROM), flash memory, optical disks, magnetic disks, and so forth). The memory/storage 405 may include fixed media (e.g., RAM, ROM, a fixed hard drive, etc.) as well as removable media (e.g., flash memory, a removable hard drive, an optical disk, and so forth). Illustratively, the memory/storage 405 may be used to store various image data, scene data, and the like mentioned in the above embodiments. The computer-readable medium 402 may be configured in various other ways as further described below.

One or more I/O interfaces 403 represent functionality that allows a user to enter commands and information to apparatus 400, and also allows information to be presented to the user and/or sent to other components or devices using various input/output devices. Examples of input devices include a keyboard, a cursor control device (e.g., a mouse), a microphone (e.g., for voice input), a scanner, touch functionality (e.g., capacitive or other sensors configured to detect physical touch), a camera (e.g., motion that does not involve touch may be detected as gestures using visible or invisible wavelengths such as infrared frequencies), a network card, a receiver, and so forth. Examples of output devices include a display device (e.g., a display or projector), speakers, a printer, a haptic response device, a network card, a transmitter, and so forth. For example, in the above-described embodiments, the user may be allowed to perform various interactive operations through the input device, may be allowed to input a configuration of user constraint information, or a configuration of weights of the random engine, or the like through the input device.

The apparatus 400 also includes an application 406. The application 406 may be stored as computer program instructions in the memory/storage 405. The application 406 may implement the methods described with respect to fig. 2, 3a-3b, in conjunction with the processing system 401, and the like.

The present disclosure may describe various techniques in the general context of software, hardware, elements, or program modules. Generally, these modules include routines, programs, objects, elements, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The terms "module," "functionality," and the like as used in this disclosure generally represent software, firmware, hardware, or a combination thereof. The features of the techniques described in this disclosure are platform-independent, meaning that the techniques may be implemented on a variety of computing platforms having a variety of processors.

An implementation of the described modules and techniques may be stored on or transmitted across some form of computer readable media. Computer readable media can include a variety of media that can be accessed by device 400. By way of example, and not limitation, computer-readable media may comprise "computer-readable storage media" and "computer-readable signal media".

"computer-readable storage medium" refers to media and/or devices capable of persistently storing information, and/or tangible storage devices, as opposed to mere signal transmission, carrier waves, or signals per se. Accordingly, computer-readable storage media refers to non-signal bearing media. Computer-readable storage media include hardware such as volatile and nonvolatile, removable and non-removable media and/or storage devices implemented in a method or technology suitable for storage of information such as computer-readable instructions, data structures, program modules, logic elements/circuits or other data. Examples of computer readable storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical storage, hard disks, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other storage devices, tangible media, or an article of manufacture suitable for storing the desired information and accessible by a computer.

"computer-readable signal medium" refers to a signal-bearing medium configured to transmit instructions to hardware of apparatus 400, such as via a network. Signal media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave, data signal or other transport mechanism. Signal media also includes any information delivery media. By way of example, and not limitation, signal media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

As previously described, the hardware elements 404 and the computer-readable medium 402 represent instructions, modules, programmable device logic, and/or fixed device logic implemented in hardware form that may be used in some embodiments to implement at least some aspects of the techniques described in this disclosure. The hardware elements may include integrated circuits or systems-on-chips, application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), complex Programmable Logic Devices (CPLDs), and other implementations in silicon or components of other hardware devices. In this context, a hardware element may serve as a processing device that performs program tasks defined by instructions, modules, and/or logic embodied by the hardware element, as well as a hardware device for storing instructions for execution, such as the computer-readable storage medium described previously.

Combinations of the foregoing may also be used to implement the various techniques and modules described in this disclosure. Thus, software, hardware, or program modules and other program modules may be implemented as one or more instructions and/or logic embodied on some form of computer-readable storage medium and/or by one or more hardware elements 404. The apparatus 400 may be configured to implement particular instructions and/or functions corresponding to software and/or hardware modules. Thus, implementing modules as modules executable by the apparatus 400 as software may be implemented at least partially in hardware, for example, using computer-readable storage media of a processing system and/or the hardware elements 404. The instructions and/or functions may be executable/operable by, for example, one or more apparatus 400 and/or processing system 401 to implement the techniques, modules, and examples described in this disclosure.

The techniques described in this disclosure may be supported by these various configurations of apparatus 400 and are not limited to specific examples of the techniques described in this disclosure.

It will be appreciated that embodiments of the disclosure have been described with reference to different functional units for clarity. However, it will be apparent that the functionality of each functional unit may be implemented in a single unit, in a plurality of units or as part of other functional units without departing from the disclosure. For example, functionality illustrated to be performed by a single unit may be performed by a plurality of different units. Thus, references to specific functional units are only to be seen as references to suitable units for providing the described functionality rather than indicative of a strict logical or physical structure or organization. Thus, the present disclosure may be implemented in a single unit or may be physically and functionally distributed between different units and circuits.

The present disclosure provides a computer-readable storage medium having stored thereon computer-executable instructions that, when executed, implement the above-described method for generating incentive information.

The present disclosure provides a computer program product or computer program comprising computer executable instructions stored in a computer readable storage medium. The processor of the computing device reads the computer-executable instructions from the computer-readable storage medium, and the processor executes the computer-executable instructions, causing the computing device to perform the methods for generating incentive information provided in the various embodiments described above.

Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method for generating stimulus information for chip verification, the method comprising:

acquiring user constraint information and system constraint information;

determining constraint items and determining available values of the constraint items based on user constraint information and/or system constraint information, wherein the constraint items comprise any one or more of combination of instruction types, instruction functions and instruction features of legal incentive information;

generating query information through a random engine based on the constraint items and the available values thereof;

querying a database by using the query information, wherein the database comprises a table for storing a set of combined information corresponding to a plurality of items of legal incentive information, one item of combined information corresponds to one item of legal incentive information, and the combined information comprises an instruction type, an instruction function and an instruction characteristic of the corresponding legal incentive information; and

and in response to the combined information matched with the query information obtained in the database, taking the combined information as the excitation information of chip verification.

2. The method of claim 1, wherein in response to the constraint term being any one of the instruction type, the instruction function, and the instruction characteristic, generating, by the random engine, query information based on the constraint term and its available values comprises:

acquiring the weight of each available value of the constraint item, wherein the weight comprises a configured weight and a default weight; and

generating, by the random engine, query information based on the constraint terms and the weights for each available value of the constraint terms.

3. The method of claim 1, wherein in response to the constraint term being a combination of any of the instruction type, the instruction function, and the instruction feature, the generating, by the random engine, query information based on the constraint term and its available values comprises:

calculating the weight of each available value of the constraint term; and

generating query information by the random engine based on the constraint terms and the weights of each available value of the constraint terms;

wherein the calculating comprises:

determining a set of weights for instruction types, instruction functions and instruction features in the available values of the constraint terms, the weights including configured weights and default weights,

step A: selecting two weights in the set of weights, calculating a combined weight of the two weights by using a calculation formula, deleting the two weights from the set, and adding the combined weight, wherein the calculation formula is as follows:

wc = (W1 × W2)/(W1 + W2), wherein Wc is the combining weight, W1 and W2 are the two weights,

4. The method of claim 1, further comprising: in response to not obtaining combined information that matches the query information, regenerating, using the random engine, new query information that conforms to the user constraint information and the system constraint information; and

and querying a table of the database by using the new query information.

5. The method of claim 4, wherein the generating the new query information comprises:

regenerating at least one instruction feature in the query information,

in response to that the query result cannot be obtained after all the instruction features are regenerated, regenerating at least one instruction function in the query information;

and in response to that the query result cannot be obtained after all the instruction functions are regenerated, regenerating at least one instruction type in the query information.

6. The method of claim 1, wherein the method further comprises: in response to receiving a configuration value for a random number seed of the random engine, configuring the random number seed of the random engine using the configuration value.

7. The method of claim 1, further comprising: performing dependency processing on the excitation information of the chip verification, wherein the dependency processing comprises:

in response to the existence of a first excitation information set, wherein the execution of the excitation information of the chip verification is premised on the execution result of the excitation information in the first excitation information set, marking the excitation information of the chip verification and each excitation information in the first excitation information set correspondingly, so that the excitation information of the chip verification is executed after each excitation information in the first excitation information set is executed; and/or

In response to the existence of a second excitation information set, wherein the execution result of the excitation information of the chip verification is the execution premise of the excitation information in the second excitation information set, marking the excitation information of the chip verification and each excitation information in the second excitation information set correspondingly, so that each excitation information in the second excitation information set is executed after the excitation information of the chip verification is executed.

8. The method of claim 1, wherein the user constraint information and the system constraint information are each in the form of a file and support configuring on the basis of the system constraint information to obtain the user constraint information.

9. The method of claim 8, wherein the file is in a text format independent of a programming language.

10. The method of claim 1, wherein the database has an encapsulated application program interface.

11. The method of claim 1, wherein the database is a lightweight database.

12. The method of claim 1, further comprising:

combining information in the excitation instruction set to generate a set of the combined information; and

importing the set of combined information into a database to generate a table in the database.

13. The method of claim 12, wherein the generated tables in the database include a plurality, each table corresponding to a set of the combined information and to an instruction type.

14. The method of claim 12, wherein the set of combined information has a first version attribute and the table of the database has a second version attribute, the method further comprising:

in response to a first version attribute of the set of combined information not being consistent with a corresponding second version attribute of a table of the database, re-importing the set of combined information into the database to generate a new table in the database, the new table having a third version attribute consistent with the first version attribute.

15. An apparatus for generating incentive information for chip verification, the apparatus comprising:

a processor; and

a memory having stored thereon computer-executable instructions that, when executed in the processor, cause performance of the method of any one of claims 1-14.

16. A computer-readable storage medium having stored therein computer-executable instructions that, when executed on a computing device, cause the computing device to implement the method of any of claims 1-14.