CN115617107A - Trimming circuit applied to low-power-consumption chip - Google Patents

Abstract

The invention discloses a trimming circuit applied to a low-power chip, which comprises: the power-on reset circuit comprises a power-on reset circuit, a first delay circuit, a second delay circuit, a third delay circuit, a trimming unit, a logic circuit and a control circuit; the input end of the power-on reset circuit is connected with a power supply, and the output end of the power-on reset circuit is respectively connected with the input end of the first delay circuit, the input end of the second delay circuit and the input end of the third delay circuit; the output end of the first delay circuit is connected with the input end of the logic circuit, the output end of the second delay circuit is connected with the input end of the trimming unit, and the output end of the third delay circuit is connected with the input end of the control circuit; the output end of the trimming unit is connected with the input end of the logic circuit, and the output end of the logic circuit is connected with the input end of the control circuit. The trimming circuit provided by the invention can complete the selection and logic control of the trimming state after the chip is electrified, almost does not consume power, and is an ideal selection of a low-power chip.

Description

Trimming circuit applied to low-power-consumption chip

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a trimming circuit applied to a low-power chip.

Background

In the design of an integrated circuit, due to the deviation of the design process, the precision of parameters is often insufficient, even exceeds the range of specifications, and thus the parameters need to be modified. In the measurement of chip performance, power consumption is an important index, but a parameter trimming circuit needs a certain working current which exists all the time as long as the chip is not powered down. Usually, a chip needs to modify a plurality of parameters, and then a plurality of modifying units are needed, which increases the power consumption of the whole chip, which is unacceptable for a low-power chip.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a trimming circuit applied to a low-power chip.

In order to achieve the purpose, the invention provides the following scheme:

a trimming circuit applied to a low-power chip comprises: the power-on reset circuit comprises a power-on reset circuit, a first delay circuit, a second delay circuit, a third delay circuit, a trimming unit, a logic circuit and a control circuit;

the input end of the power-on reset circuit is connected with a power supply, and the output end of the power-on reset circuit is respectively connected with the input end of the first delay circuit, the input end of the second delay circuit and the input end of the third delay circuit; the output end of the first delay circuit is connected with the input end of the logic circuit, the output end of the second delay circuit is connected with the input end of the trimming unit, and the output end of the third delay circuit is connected with the input end of the control circuit; the output end of the trimming unit is connected with the input end of the logic circuit, and the output end of the logic circuit is connected with the input end of the control circuit.

Optionally, the trimming unit includes: the device comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a bias current source and a fuse wire;

the input end of the first phase inverter is connected with the output end of the second delay circuit, the output end of the first phase inverter is respectively connected with the input end of the second phase inverter and the grid electrode of the second PMOS tube, the power supply end of the first phase inverter is connected with the power supply, and the ground end of the first phase inverter is grounded; the output end of the second phase inverter is respectively connected with the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the fourth NMOS tube and the grid electrode of the seventh NMOS tube; the power supply end of the second inverter is connected with the power supply, and the ground end of the second inverter is grounded; the input end of the bias current source is connected with the power supply, and the output end of the bias current source is connected with the source electrode of the first PMOS tube; the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube; the source electrode of the first NMOS tube is grounded; the source electrode of the second NMOS tube is grounded; the drain electrode of the third NMOS tube is respectively connected with the drain electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube, and the source electrode of the third NMOS tube is grounded; the source electrode of the second PMOS tube is connected with the power supply; the source electrode of the third PMOS tube is connected with the power supply; the drain electrode of the fourth PMOS tube is respectively connected with the drain electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube, and the source electrode of the fourth PMOS tube is connected with the power supply; the drain electrode of the fifth PMOS tube is respectively connected with the drain electrode of the sixth NMOS tube, the drain electrode of the seventh NMOS tube and the input end of the third phase inverter, and the source electrode of the fifth PMOS tube is connected with the power supply; the source electrode of the fourth NMOS tube is grounded; the source electrode of the fifth NMOS tube is grounded; the source electrode of the sixth NMOS tube is connected with the first input end of the fuse, and the second input end of the fuse is grounded; the source electrode of the seventh NMOS tube is grounded; the output end of the third inverter is connected with the input end of the fourth inverter, the power supply end of the third inverter is connected with the power supply, and the ground end of the third inverter is grounded; the output end of the fourth phase inverter is connected with the input end of the logic circuit, the power supply end of the fourth phase inverter is connected with the power supply, and the ground end of the fourth phase inverter is grounded.

Optionally, the W/L ratio of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor is 2; the W/L ratio of the second NMOS tube to the third NMOS tube is 1; the W/L ratio of the fifth NMOS tube to the sixth NMOS tube is 1.

Optionally, when the output of the second delay circuit is at a low level, the trimming unit is in a normal operating state; if the repair is not carried out, the fuse wire is not blown, and the output end of the fourth inverter outputs low level; and if the voltage is modified, the fuse is blown, and the output end of the fourth inverter outputs high level.

Optionally, the logic circuit comprises: the NOR gate, the fifth inverter, the sixth inverter and the NAND gate;

a first input end of the nor gate is connected with an output end of the sixth phase inverter, a second input end of the nor gate is connected with an output end of the fourth phase inverter, and an output end of the nor gate is connected with an input end of the fifth phase inverter; the output end of the fifth inverter is connected with the first input end of the NAND gate; the second input end of the NAND gate is connected with the output end of the first delay circuit, and the output end of the NAND gate is connected with the input end of the sixth inverter; and the output end of the sixth inverter is also connected with the input end of the control circuit.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the trimming circuit provided by the invention is suitable for a trimming circuit (universal type) for blowing a fuse wire, and after a chip is electrified, the trimming circuit not only can finish the selection and logic control of a trimming state, but also hardly consumes power, so that the trimming circuit is an ideal selection of a low-power chip.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a trimming circuit applied to a low power consumption chip according to the present invention;

fig. 2 is a schematic structural diagram of a trimming unit according to the present invention;

FIG. 3 is a schematic diagram of a logic circuit according to the present invention

Fig. 4 is a schematic diagram of the working curves of the points in the trimming circuit applied to the low power consumption chip according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description thereof.

As shown in fig. 1, the trimming circuit applied to a low power consumption chip provided by the present invention includes: the power-on reset circuit comprises a power-on reset circuit I1, a first delay circuit I2, a second delay circuit I3, a third delay circuit I7, a trimming unit I4, a logic circuit I5 and a control circuit I6.

The input end of the power-on reset circuit I1 is connected with a power supply VCC, and the output end of the power-on reset circuit I1 is respectively connected with the input end of the first delay circuit I2, the input end of the second delay circuit I3 and the input end of the third delay circuit I7. The output end of the first delay circuit I2 is connected with the input end of the logic circuit I5, the output end of the second delay circuit I3 is connected with the input end of the trimming unit I4, and the output end of the third delay circuit I7 is connected with the input end of the control circuit I6; the output end of the trimming unit I4 is connected with the input end of the logic circuit I5, and the output end of the logic circuit I5 is connected with the input end of the control circuit I6.

The power-on reset circuit I1 generates a logic signal POR during the rising of VCC to reset or enable control of other blocks. POR goes from low to high after VCC rises to a certain threshold. The timing operation of the first delay circuit I2 and the second delay circuit I3 is controlled by a signal POR.

The second delay circuit I3 performs delay processing (using an inverter and an RC) on the signal POR output by the power-on reset circuit I1, and turns off each branch current in the trimming unit I4 after the delay is finished.

The trimming unit I4 determines whether the output TRIM _ DATA is high or low by using whether the FUSE is blown or not, and if trimming is needed, namely, the FUSE is blown, the TRIM _ DATA is high; if not, TRIM _ DATA is low.

The logic circuit I5 will set TRIM _ OK using the output TRIM _ CTL of the first delay circuit I2 and latch the output TRIM _ DATA state of the trimming unit I4. When VCC is not powered down, TRIM _ OK is kept high or low all the time, TRIM _ OK is a latch signal which is finally output, and the high or low state represents trimming or not trimming.

The third delay circuit I7 generates a delay time TDC based on the output signal POR of the power-on reset circuit I1, and outputs a POR _ END signal for determining the operating state of the control circuit I6. The control circuit I6 determines whether to transmit the TRIM _ OK signal to the subsequent stage circuit according to the POR _ END signal.

The working principle of the trimming circuit applied to the low-power-consumption chip provided by the invention is as follows:

during VCC power-up, if VCC>VPOR, the output POR of the power-on reset circuit I1 is changed from low to high, and meanwhile, the first delay circuit I2, the second delay circuit I3 and the third delay circuit IAnd 7, starting timing. At T _DA During the time, the output TRIM _ CTL of the first delay circuit I2 is low at T _DB During this time, the output TRIM _ RST of the second delay circuit I3 is low at T _DC During the time, the third delay circuit I7 outputs POR _ END low. If trimming is performed, the fuse is blown at T _DB During the time, the output TRIM _ DATA of the trimming unit I4 remains high, at T _DA During the time, the output TRIM _ OK of the logic circuit I5 remains low at T _DC During the time, the output CTL of the control circuit I6 remains low. Once T is completed _DA At the end of this time, the first delay circuit I2 turns the output TRIM _ CTL from low to high, sets the output TRIM _ OK of the logic circuit I5 high, and keeps high, and as long as VCC does not power down, TRIM _ OK remains high. Once T is completed _DB At the end of the time, the output TRIM _ RST of the second delay circuit I3 goes from low to high, the output TRIM _ DATA of the trimming unit I4 goes from high to low, and the current of each branch in the trimming unit I4 is turned off. If not trimmed, the fuse is not blown and the output TRIM _ OK of the logic circuit I5 is always low, also at T _DB After the time is over, the second delay circuit I3 outputs the TRIM _ RST from low to high, and the current of each branch in the trimming unit I4 is also turned off. Once T is completed _DC At the END of the time, the output signal POR _ END of the third delay circuit I7 goes high, allowing the control circuit I6 to transmit a TRIM _ OK signal to CTL, i.e. CTL in the same direction as TRIM _ OK. The operating curves for each point in the trimming circuit are shown in fig. 4.

As shown in fig. 2, the trimming unit includes: a first phase inverter I8, a second phase inverter I9, a third phase inverter (schmitt phase inverter) I10, a fourth phase inverter I11, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, a bias current source I _BIAS And a FUSE.

The input end of the first phase inverter I8 is connected with the output end of the second delay circuit I3, the output end of the first phase inverter I8 is respectively connected with the input end of the second phase inverter I9 and the grid electrode of the second PMOS tube P2, the power supply end of the first phase inverter I8 is connected with a power supply VCC, and the ground end of the first phase inverter I8 is grounded GND; the output end of the second phase inverter I9 is respectively connected with the grid electrode of the first PMOS tube P1, the grid electrode of the first NMOS tube N1, the grid electrode of the fourth NMOS tube N4 and the grid electrode of the seventh NMOS tube N7; the power supply end of the second phase inverter I9 is connected with a power supply VCC, and the ground end of the second phase inverter I9 is grounded GND; the input end of the bias current source is connected with a power supply VCC, and the output end of the bias current source is connected with the source electrode of the first PMOS tube P1; the drain electrode of the first PMOS tube P1 is respectively connected with the drain electrode of the first NMOS tube N1, the drain electrode of the second NMOS tube N2, the grid electrode of the second NMOS tube N2 and the grid electrode of the third NMOS tube N3; the source electrode of the first NMOS tube N1 is grounded GND; the source electrode of the second NMOS tube N2 is grounded GND; the drain electrode of a third NMOS tube N3 is respectively connected with the drain electrode of a second PMOS tube P2, the drain electrode of a third PMOS tube P3, the grid electrode of the third PMOS tube P3, the grid electrode of a fourth PMOS tube P4 and the grid electrode of a fifth PMOS tube P5, and the source electrode of the third NMOS tube N3 is grounded GND; the source electrode of the second PMOS pipe P2 is connected with a power supply VCC; the source electrode of the third PMOS pipe P3 is connected with a power supply VCC; the drain electrode of the fourth PMOS tube P4 is respectively connected with the drain electrode of the fourth NMOS tube N4, the drain electrode of the fifth NMOS tube N5, the grid electrode of the fifth NMOS tube N5 and the grid electrode of the sixth NMOS tube N6, and the source electrode of the fourth PMOS tube P4 is connected with a power supply VCC; the drain electrode of a fifth PMOS tube P5 is respectively connected with the drain electrode of a sixth NMOS tube N6, the drain electrode of a seventh NMOS tube N7 and the input end of a third phase inverter I10, and the source electrode of the fifth PMOS tube P5 is connected with a power supply VCC; the source electrode of the fourth NMOS tube N4 is grounded GND; the source electrode of the fifth NMOS tube N5 is grounded GND; the source electrode of the sixth NMOS tube N6 is connected with the first input end of the fuse, and the second input end of the fuse is grounded GND; the source electrode of the seventh NMOS tube N7 is grounded GND; the output end of the third phase inverter I10 is connected with the input end of the fourth phase inverter I11, the power supply end of the third phase inverter I10 is connected with a power supply VCC, and the ground end of the third phase inverter I10 is grounded GND; the output end of the fourth phase inverter I11 is connected with the input end of the logic circuit I5, the power supply end of the fourth phase inverter I11 is connected with a power supply VCC, and the ground end of the fourth phase inverter I11 is grounded GND.

The W/L ratio of the third PMOS pipe P3, the fourth PMOS pipe P4 and the fifth PMOS pipe P5 is 2; the W/L ratio of the second NMOS transistor N2 to the third NMOS transistor N3 is 1; the W/L ratio of the fifth NMOS transistor N5 to the sixth NMOS transistor N6 is 1.

The operating principle of the trimming unit I4 is as follows:

when the TRIM _ RST is high, the trimming unit I4 does not consume power and is in a turn-off state; the output end of the first inverter I8 is low, and the output end of the second inverter I9 is high; the grid electrode of the second PMOS pipe P2 is set to be low; the grid electrode of the first PMOS pipe P1, the grid electrode of the first NMOS pipe N1, the grid electrode of the fourth NMOS pipe N4 and the grid electrode of the seventh NMOS pipe N7 are all set to be high; the grid and the drain of the second NMOS transistor N2 and the grid of the third NMOS transistor N3 are all set to low, and the grid and the drain of the fifth NMOS transistor N5 and the grid and the drain of the sixth NMOS transistor N6 are all set to low; the grid and the drain of the third PMOS tube P3, the grid of the fourth PMOS tube P4 and the grid of the fifth PMOS tube P5 are all set to be high; the input end of the third inverter I10 is set to low, and the output end thereof is set to high; the fourth inverter I11 has its input high and its output TRIM _ DATA low. When the TRIM _ RST is low, the trimming unit I4 is in a normal working state; if the FUSE is not burned off, the drain electrode of the sixth NMOS tube N6 is low, and the output end TRIM _ DATA of the fourth inverter I11 is low; if the trimming is performed, the FUSE is blown, the drain of the sixth NMOS transistor N6 is high, and the output terminal TRIM _ DATA of the fourth inverter I11 is high. At T _DB In time, the TRIM _ RST is low, trimming or not trimming is performed, the TRIM _ DATA state is determined, the TRIM _ DATA state is transmitted to the logic circuit I5, and the logic circuit I5 latches the TRIM _ DATA state; at T _DB After the time is over, TRIM _ RST changes from low to high, and the current of each branch in trimming unit I4 is turned off.

As shown in fig. 3, the logic circuit I5 includes: a NOR gate I12, a fifth inverter I13, a sixth inverter I15 and a NAND gate I14.

A first input end of the nor gate I12 is connected with an output end of the sixth inverter I15, a second input end of the nor gate I12 is connected with an output end of the fourth inverter I11, and an output end of the nor gate I12 is connected with an input end of the fifth inverter I13; the output end of the fifth inverter I13 is connected with the first input end of the NAND gate I14; a second input end of the NAND gate I14 is connected with the output end of the first delay circuit I12, and the output end of the NAND gate I14 is connected with the input end of the sixth inverter I15; the output terminal of the sixth inverter I15 is also connected to the input terminal of the control circuit I16.

The operating principle of the logic circuit I5 is as follows:

if the second input terminal TRIM _ CTL of the nand gate I14 is low, the output terminal TRIM _ OK of the sixth inverter I15 is low, and the output terminal TRIM _ OK of the sixth inverter I15 is always low regardless of whether the second input terminal of the nor gate I12 is high or low. If the second input TRIM _ DATA of the nor gate I12 is low during the time that the second input TRIM _ CTL of the nand gate I14 is low, the output TRIM _ OK of the fifth inverter I13 is low, and the output TRIM _ OK of the sixth inverter I15 is latched low once the second input TRIM _ CTL of the nand gate I14 is changed from low to high. If the second input TRIM _ DATA of the nor gate I12 is high during the time when the second input TRIM _ CTL of the nand gate I14 is low, the output TRIM _ OK of the sixth inverter I15 is latched high once the second input TRIM _ CTL of the nand gate I14 is high from low.

The invention is suitable for trimming circuit (universal type) of blowing fuse, after the chip is electrified, it not only completes the selection and logic control of trimming state, but also almost consumes no power, which is an ideal choice for low power consumption chip.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (5)

1. A trimming circuit applied to a low-power chip is characterized by comprising: the power-on reset circuit comprises a power-on reset circuit, a first delay circuit, a second delay circuit, a third delay circuit, a trimming unit, a logic circuit and a control circuit;

the input end of the power-on reset circuit is connected with a power supply, and the output end of the power-on reset circuit is respectively connected with the input end of the first delay circuit, the input end of the second delay circuit and the input end of the third delay circuit; the output end of the first delay circuit is connected with the input end of the logic circuit, the output end of the second delay circuit is connected with the input end of the trimming unit, and the output end of the third delay circuit is connected with the input end of the control circuit; the output end of the trimming unit is connected with the input end of the logic circuit, and the output end of the logic circuit is connected with the input end of the control circuit.

2. The trimming circuit applied to a low-power consumption chip according to claim 1, wherein the trimming unit comprises: the device comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a bias current source and a fuse wire;

the input end of the first phase inverter is connected with the output end of the second delay circuit, the output end of the first phase inverter is respectively connected with the input end of the second phase inverter and the grid electrode of the second PMOS tube, the power supply end of the first phase inverter is connected with the power supply, and the ground end of the first phase inverter is grounded; the output end of the second phase inverter is respectively connected with the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the fourth NMOS tube and the grid electrode of the seventh NMOS tube; the power supply end of the second inverter is connected with the power supply, and the ground end of the second inverter is grounded; the input end of the bias current source is connected with the power supply, and the output end of the bias current source is connected with the source electrode of the first PMOS tube; the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube; the source electrode of the first NMOS tube is grounded; the source electrode of the second NMOS tube is grounded; the drain electrode of the third NMOS tube is respectively connected with the drain electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube, and the source electrode of the third NMOS tube is grounded; the source electrode of the second PMOS tube is connected with the power supply; the source electrode of the third PMOS tube is connected with the power supply; the drain electrode of the fourth PMOS tube is respectively connected with the drain electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube, and the source electrode of the fourth PMOS tube is connected with the power supply; the drain electrode of the fifth PMOS tube is respectively connected with the drain electrode of the sixth NMOS tube, the drain electrode of the seventh NMOS tube and the input end of the third phase inverter, and the source electrode of the fifth PMOS tube is connected with the power supply; the source electrode of the fourth NMOS tube is grounded; the source electrode of the fifth NMOS tube is grounded; the source electrode of the sixth NMOS tube is connected with the first input end of the fuse, and the second input end of the fuse is grounded; the source electrode of the seventh NMOS tube is grounded; the output end of the third inverter is connected with the input end of the fourth inverter, the power supply end of the third inverter is connected with the power supply, and the ground end of the third inverter is grounded; the output end of the fourth phase inverter is connected with the input end of the logic circuit, the power supply end of the fourth phase inverter is connected with the power supply, and the ground end of the fourth phase inverter is grounded.

3. The trimming circuit applied to a low power consumption chip according to claim 2, wherein the W/L ratio of the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor is 2; the W/L ratio of the second NMOS tube to the third NMOS tube is 1; the W/L ratio of the fifth NMOS tube to the sixth NMOS tube is 1.

4. The trimming circuit applied to a low-power consumption chip according to claim 2, wherein when the output of the second delay circuit is at a low level, the trimming unit is in a normal operating state; if the repair is not carried out, the fuse wire is not blown, and the output end of the fourth inverter outputs low level; and if the voltage is modified, the fuse is blown, and the output end of the fourth inverter outputs high level.

5. The trimming circuit applied to a low-power consumption chip according to claim 2, wherein the logic circuit comprises: the NOR gate, the fifth inverter, the sixth inverter and the NAND gate;

a first input end of the nor gate is connected with an output end of the sixth inverter, a second input end of the nor gate is connected with an output end of the fourth inverter, and an output end of the nor gate is connected with an input end of the fifth inverter; the output end of the fifth inverter is connected with the first input end of the NAND gate; a second input end of the NAND gate is connected with an output end of the first delay circuit, and an output end of the NAND gate is connected with an input end of the sixth inverter; and the output end of the sixth phase inverter is also connected with the input end of the control circuit.

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