CN115616291A - Test method for reducing influence of contact parasitic resistance on device test - Google Patents

Test method for reducing influence of contact parasitic resistance on device test Download PDF

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CN115616291A
CN115616291A CN202211336879.8A CN202211336879A CN115616291A CN 115616291 A CN115616291 A CN 115616291A CN 202211336879 A CN202211336879 A CN 202211336879A CN 115616291 A CN115616291 A CN 115616291A
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resistance value
resistance
testing
depth
tested
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刘倩倩
高玉珠
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GTA Semiconductor Co Ltd
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GTA Semiconductor Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08—Measuring resistance by measuring both voltage and current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention discloses a test method for reducing the influence of contact parasitic resistance on device test, which comprises the following steps: s101: providing a semiconductor wafer, and selecting a grain to be tested on the semiconductor wafer; s102: testing the resistance of the crystal grain to be tested by adopting a four-terminal method to obtain a first resistance value; s103: testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value; s104: and adjusting the pricking depth of the crystal grain to be tested pricked by the two-end method to be the first pricking depth so that the second resistance value is equal to the first resistance value. Furthermore, the resistance value of the resistance measured by the two-end method is adjusted by adjusting the depth of the pin of the two-end method, so that the resistance value measured by the two-end method is equal to the resistance value measured by the four-end method, the influence of the contact parasitic resistance on the resistance measured by the two-end method is further eliminated, and the reliability or yield of the semiconductor wafer or the device is tested by the depth of the pin when the resistance measured by the two-end method is equal to the resistance measured by the four-end method, so that the test accuracy is improved.

Description

Test method for reducing influence of contact parasitic resistance on device test
Technical Field
The invention relates to the technical field of semiconductor device testing, in particular to a testing method for reducing the influence of contact parasitic resistance on device testing.
Background
In the field of semiconductor manufacturing, semiconductor resistivity is one of the most critical parameters. Probes are commonly used in the prior art to measure resistivity of semiconductor wafers or films. For example, when a wafer film is tested by using an equidistant four-point probe apparatus, probes are inserted into a film to be tested formed on the surface of a semiconductor wafer, and fixed currents are applied to the first probe and the fourth probe, and a voltage between the second probe and the third probe is measured at the same time, so that the resistivity of the film to be tested is obtained.
However, when devices are tested, some device tests can only be performed by using two-point probes, when the devices are tested by using the two-point probes, some contact parasitic resistances between the probes and the wafer pad interfere with test results, and the obtained device test parameter data is not intrinsic to the devices, so that the test results are not accurate.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a testing method for reducing the influence of contact parasitic resistance on device testing, so as to reduce the influence of contact parasitic resistance on device testing.
To achieve the above and other related objects, the present invention provides a testing method for reducing the influence of contact parasitic resistance on device testing, comprising the steps of:
s101: providing a semiconductor wafer, and selecting a crystal grain to be tested on the semiconductor wafer;
s102: testing the resistance of the crystal grain to be tested by adopting a four-terminal method to obtain a first resistance value;
s103: testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value;
s104: and adjusting the pricking depth of the crystal grain to be tested pricked by the two-end method to be a first pricking depth, so that the second resistance value is equal to the first resistance value.
Optionally, after adjusting the pricking depth of the die to be tested pricked by the two-end method to the first pricking depth, the method further includes:
s106: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value;
s107: pricking to the to-be-tested crystal grains by the first pricking depth, and testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a two-end method to obtain a fourth resistance value;
s108: and comparing the third resistance value with the fourth resistance value, judging whether the third resistance value is the same as the fourth resistance value, and determining whether to readjust the puncture depth according to the judgment result.
Optionally, the step of determining whether to readjust the puncture depth according to the determination result includes:
if the third resistance value is equal to the fourth resistance value, taking the first pricking depth as the pricking depth for the subsequent test of the semiconductor wafer;
if the third resistance value is not equal to the fourth resistance value, the depth of the needle insertion is readjusted.
Optionally, the step of readjusting the depth of the needle insertion comprises:
testing the resistance of the crystal grain to be tested by adopting a four-terminal method to obtain a first resistance value;
testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value;
adjusting the depth of the two-end method for inserting the crystal grain to be tested to be a second inserting depth so that the second resistance value is equal to the first resistance value;
testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value;
penetrating the second pricking pin to the grain to be tested in depth, and testing the resistance of the grain at the edge of the semiconductor wafer by adopting a two-end method to obtain a fourth resistance value;
if the fourth resistance value is equal to the third resistance value, taking the second pricking depth as the pricking depth for the subsequent test of the semiconductor wafer;
if the fourth resistance value is not equal to the third resistance value, the steps S102 to S108 are repeated until the third resistance value is equal to the fourth resistance value, and the pricking depth at this time is used as the pricking depth during the subsequent semiconductor wafer test.
Optionally, before testing the resistance of the die to be tested by using a four-terminal method, the method further includes:
and pricking the to-be-detected crystal grain by adopting a four-terminal needle or a probe card in a Kelvin four-wire detection method, so that the four probes are pricked into the to-be-detected crystal grain.
Optionally, after the die under test is punctured by a four-terminal puncturing pin or a probe card using a kelvin four-wire detection method, the method further includes:
check whether the needle mark is normal.
Optionally, the step of testing the resistance of the die to be tested by using a four-terminal method includes:
applying a current between the first probe and the fourth probe, and testing the voltage between the second probe and the third probe;
and calculating to obtain a first resistance value according to the applied current value and the measured voltage value.
Optionally, the step of testing the resistance of the die to be tested by using a two-terminal method includes:
applying a current between the second probe and the third probe, and testing a voltage between the second probe and the third probe;
and calculating to obtain a second resistance value according to the applied current value and the tested voltage value.
Optionally, the semiconductor wafer test comprises a hot carrier effect test.
Optionally, after determining whether to readjust the insertion depth according to the determination result, the method further includes:
and setting the finally determined needle inserting depth as the automatic needle inserting depth of the semiconductor wafer test.
Compared with the prior art, the test method for reducing the influence of the contact parasitic resistance on the device test at least has the following beneficial effects:
the test method for reducing the influence of the contact parasitic resistance on the device test comprises the following steps: s101: providing a semiconductor wafer, and selecting a grain to be tested on the semiconductor wafer; s102: testing the resistance of the grain to be tested by adopting a four-terminal method to obtain a first resistance value; s103: testing the resistance of the grain to be tested by adopting a two-end method to obtain a second resistance value; s104: and adjusting the depth of the needle penetrating into the crystal grain to be measured by the two-end method to be the first depth of the needle, so that the second resistance value is equal to the first resistance value. Furthermore, the resistance value of the resistance measured by the two-end method is adjusted by adjusting the depth of the pin of the two-end method, so that the resistance value measured by the two-end method is equal to the resistance value measured by the four-end method, the influence of the contact parasitic resistance on the resistance measured by the two-end method is further eliminated, and the reliability or yield of the semiconductor wafer or the device is tested by the depth of the pin when the resistance measured by the two-end method is equal to the resistance measured by the four-end method, so that the test accuracy is improved.
Further, in order to ensure the applicability of the above-mentioned needle insertion depth to the whole wafer, the test method of the present invention further includes S106: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value; s107: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a two-end method, and enabling the probe to penetrate into the crystal grains by the first penetration depth to obtain a fourth resistance value; s108: and comparing the third resistance value with the fourth resistance value, judging whether the third resistance value is the same as the fourth resistance value, and determining whether to readjust the pricking depth according to the judgment result. Therefore, the invention uses the crystal grains at the four corners of the edge of the semiconductor wafer to perform the reinspection on the depth of the puncturing needle, when the third resistance value obtained by measuring the resistance by the four-end method is equal to the fourth resistance value, the puncturing depth is suitable for the whole wafer, and each crystal grain on the wafer can be tested by using the puncturing depth. And when the third resistance value obtained by measuring the resistance of the crystal grains at the four corners of the edge of the wafer by adopting the four-terminal method is equal to the fourth resistance value, the steps S102 to S108 are repeatedly executed until the third resistance value is equal to the fourth resistance value, and the pricking depth at the moment is taken as the pricking depth in the subsequent whole semiconductor wafer test.
Drawings
FIG. 1 is a flow chart of steps of a test method for reducing the impact of contact parasitic resistance on device testing in accordance with the present invention;
FIG. 2 is a schematic diagram of an equivalent circuit of a four-terminal method resistance test;
FIG. 3 is a photograph of a pin mark in the case of testing a resistor by a four-terminal method;
FIG. 4 is a schematic diagram of an equivalent circuit of a two-terminal method resistance test;
FIG. 5 is a photograph of a pin mark of a two-terminal test resistor;
FIG. 6 is a schematic diagram of a two-terminal method equivalent circuit after adjustment of the needle;
FIG. 7 is a photograph showing the pin marks of the electrical resistance measured by the both-end method after the adjustment of the pin.
FIG. 8 is a flowchart of a test performed on a semiconductor wafer according to comparative example 1 of the present invention by a two-terminal method;
FIG. 9 is a graph showing a test data distribution of a semiconductor wafer according to comparative example 1 of the present invention;
fig. 10 is a flowchart illustrating the testing operation of the hot carrier effect test on the semiconductor wafer according to embodiment 1 of the present invention;
fig. 11 is a distribution diagram of test data obtained by performing a hot carrier effect test on a semiconductor wafer in embodiment 1 of the present invention.
List of reference numerals:
first probe of SMU1
Second probe of SMU2
SMU3 third Probe
SMU4 fourth Probe
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure of the present invention. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present application. It should be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be understood that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component in actual implementation can be changed freely, and the layout of the components may be more complicated. The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, the drawings and the appended claims are for illustrative purposes only and are not intended to limit the scope of the present disclosure.
In order to solve the problems in the background art, the influence of the contact parasitic resistance on test data when a semiconductor wafer or a semiconductor device is tested by adopting a two-terminal method is eliminated. The embodiment provides a testing method for reducing the influence of contact parasitic resistance on device testing, and with reference to fig. 1, the testing method comprises the following steps:
s101: providing a semiconductor wafer to be tested;
a semiconductor wafer to be tested is provided, the semiconductor wafer is divided into a plurality of crystal grains, and each crystal grain is provided with a semiconductor device structure. In the present embodiment, a MOS device is formed on each of the crystal grains. Selecting a certain crystal grain on the semiconductor wafer to carry out resistance test on the semiconductor device, wherein the crystal grain is the crystal grain to be tested.
Before testing, the die to be tested needs to be pricked. Optionally, a kelvin four-wire detection method may be adopted to prick a die to be tested at four ends or a probe card, the four probes are respectively pricked onto a test pad of the die to be tested, after the pricking is completed, whether the needle mark is normal needs to be checked, if the needle mark is not normal, the needle needs to be pricked again, and the next operation can be performed only when the needle mark is normal.
S103: testing the resistance of the grain to be tested by adopting a four-terminal method to obtain a first resistance value;
after the pin mark is checked, the resistance of the grain to be tested is tested by adopting a four-end method to obtain a first resistance value. It should be noted that the method for testing the resistance by the four-terminal method described in the present invention is also called kelvin four-wire detection method.
Before testing the resistor, four probes are selected to be respectively inserted on the bonding pads of the die to be tested, and the pin marks are shown in fig. 3. When the four-terminal method is adopted to test the resistor, current is applied between the first probe and the fourth probe, voltage between the second probe and the third probe is tested, and a first resistance value is calculated and obtained according to the applied current value and the measured voltage value. In this embodiment, referring to fig. 2, a current I is applied between the first probe SMU1 and the fourth probe SMU4, a voltage value U is measured at the second probe SMU2 and the third probe SMU3, a voltage difference between the second probe SMU2 and the third probe SMU3 measured at this time is a voltage of the structure to be measured, and Rtest can be obtained by using a formula R = U/I. In this embodiment, the resistance Rtest of the structure to be tested is measured to be 60 Ω. Therefore, the resistance value obtained by adopting the four-terminal method is the actual resistance of the structure to be tested, the contact parasitic resistance is not included, the influence of the contact resistance between the probe and the structure to be tested can be eliminated, and the tested resistance value is not easily influenced by the needle mark.
S104: testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value;
and testing the resistance of the grain to be tested by adopting a two-end method to obtain a second resistance value. It should be noted that the method for measuring the resistance by the two-terminal method is also called voltammetry.
During testing, current is applied between the second probe and the third probe, voltage between the second probe and the third probe is tested at the same time, and a second resistance value is calculated and obtained according to the applied current value and the tested voltage value. The pin mark of the resistance measured by the both-end method is shown in FIG. 5.
Specifically, referring to fig. 4, a current is applied between the second probe SMU2 and the third probe SMU3 while a voltage between the second probe SMU2 and the third probe SMU3 is tested, and a resistance value obtained by the final test is a resistance value R2+ Rtest + R3. Therefore, the resistance value obtained by the two-end method includes the resistance values of the contact parasitic resistance R2 and the contact parasitic resistance R3, and the resistance value obtained by the two-end method is easily affected by the contact parasitic resistance value, that is, the puncturing depth affects the test resistance value. In the present embodiment, the resistance value R2+ Rtest + R3 obtained by the test is about 69 Ω, and the resistance value Rtest in the four-terminal method test is 60 Ω. The contact parasitic resistance R2 and the contact parasitic resistance R3 have a value of 9 Ω, as calculated.
However, when testing a semiconductor wafer, for example, when testing a hot carrier effect of the semiconductor wafer, the four-terminal method cannot be used for testing, and the two-terminal method is generally used for testing the semiconductor wafer. The depth of the needle insertion in the two-end method test can affect the test data in the hot carrier effect test, further affect the final test result and is not beneficial to the accuracy of the test result.
S105: adjusting the pricking depth of the crystal grain to be tested pricked by the two-end method to be a first pricking depth so that the second resistance value is equal to the first resistance value;
in order to eliminate the testing defects in the two-end method, the present embodiment adjusts the puncturing depth to make the testing result approach to the testing structure of the four-end method, and finally obtains the proper puncturing depth. The puncture depth is adjusted to enable the test structure to approach the test of a four-end method, finally, the proper puncture depth can be obtained, the test resistance value Rtest on the puncture depth is 60 omega, and the contact resistance can be ignored. The depth of the pin can be referred to when the device is tested subsequently, so that the influence of the contact parasitic resistance can be eliminated.
Specifically, in this embodiment, referring to fig. 6, when the first resistance value and the second resistance value of the test are not equal, the puncturing is repeatedly performed, and the puncturing depth of the die to be tested, which is punctured by the two-end method, is adjusted, so that the second resistance value is close to the first resistance value, until the second resistance value is equal to the first resistance value, the puncturing depth is determined to be the first puncturing depth. When the first pricking depth can eliminate the resistance test by a two-end method, the influence of the contact parasitic resistance on the test result can be eliminated, and the contact parasitic resistance value at the moment can be ignored. The needle mark after adjusting the depth of the needle insertion is shown in fig. 7.
However, in order to ensure the applicability of the puncturing depth to the dies at other positions of the semiconductor wafer, the present embodiment adopts a die-skipping test to perform a re-inspection on the first puncturing depth.
S106: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value;
in this embodiment, the dies at the four corners of the edge of the semiconductor wafer are selected to perform a review of the depth of the needle. Specifically, a four-terminal method is used to test the resistance of a certain die at the edge of the semiconductor wafer, and a third resistance value is obtained. Similarly, a current is applied between the first probe and the fourth probe, a voltage between the second probe and the third probe is tested, and a third resistance value is calculated and obtained according to the applied current value and the measured voltage value. Optionally, a plurality of dies at the edge of the semiconductor wafer may be selected for review to ensure the applicability of the above-mentioned puncturing depth, in this embodiment, a certain die at the four corners of the edge of the semiconductor is selected for illustration, and the number of the reviewed dies does not limit the present invention.
S107: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a two-end method, and enabling the probe to penetrate into the crystal grains by the first penetration depth to obtain a fourth resistance value;
and continuing to test the selected crystal grains at the edge of the semiconductor wafer by a two-end method, and adopting the first pricking pin to prick into the bonding pad of the crystal grains to check whether the pin marks are normal. Similarly, a current is applied between the second probe and the third probe while a voltage between the second probe and the third probe is measured, and a fourth resistance value is calculated from the applied current value and the measured voltage value.
S108: and comparing the third resistance value with the fourth resistance value, judging whether the third resistance value is the same as the fourth resistance value, and determining whether to readjust the pricking depth according to the judgment result.
The third resistance value obtained in step S106 and the fourth resistance value obtained in step S107 are compared. If the third resistance value is equal to the fourth resistance value, taking the first pricking depth as the pricking depth of the semiconductor wafer in the subsequent test; if the third resistance value is not equal to the fourth resistance value, the depth of the needle insertion is readjusted.
Wherein, readjusting the depth of the needle insertion comprises the following steps: and pricking the crystalline grains to be tested again, and testing the resistance of the crystalline grains to be tested by adopting a four-end method to obtain a first resistance value. And testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value. And adjusting the needle inserting depth of the two-end method into the crystal grain to be detected to be a second needle inserting depth so that the second resistance value is equal to the first resistance value. And testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value. And testing the resistance of the crystal grain at the edge of the semiconductor wafer by adopting a two-end method, and enabling the probe to penetrate into the crystal grain by the second penetration depth to obtain a fourth resistance value.
And if the fourth resistance value is equal to the third resistance value, taking the second pricking depth as the pricking depth of the subsequent test of the semiconductor wafer. If the fourth resistance value is not equal to the third resistance value, the steps S102 to S108 are repeated until the third resistance value is equal to the fourth resistance value, and the pricking depth at this time is used as the pricking depth in the subsequent test of the semiconductor wafer.
After readjusting the puncturing depth, the finally determined puncturing depth is set as an automatic puncturing depth for semiconductor wafer testing. The semiconductor wafer is tested according to the pricking depth, so that a relatively accurate test result is ensured, and the influence of the contact parasitic resistance on test data is avoided when a two-end method is adopted for testing. Optionally, the semiconductor wafer test described in this embodiment may be a Hot Carrier Injection (HCI) test, a reliability test, an electrical test, or the like. It should be noted that the present invention is applicable to any device test performed by the both-end method.
The following describes the testing method for reducing the influence of contact parasitic resistance on device testing according to the present invention in detail with reference to specific comparative examples and examples.
Comparative example 1
Referring to fig. 8, generally, in the hot carrier effect test of a semiconductor wafer, a four-terminal pin is first used on the semiconductor wafer or the semiconductor device to check whether the pin mark is normal. If the needle mark is detected to be abnormal, the needle insertion needs to be performed again so as to avoid the test error caused by poor needle insertion. If the pin mark is normal, the initial current and the voltage value are continuously checked to be normal, and after the initial current is checked to be normal, the hot carrier effect test is carried out on the semiconductor wafer or the semiconductor device. Referring to fig. 7, since the present comparative example tests the resistance using the two-terminal method, the test resistance includes a contact parasitic resistance R2 and a contact parasitic resistance R3, and the presence of the contact parasitic resistance may have an influence on the test result.
The test data obtained by performing the hot carrier effect test on the semiconductor wafer by using the test method in the comparative example is shown in fig. 9, and it can be seen that the hot carrier effect test is performed on the semiconductor device for 5 times at different time points in the figure, the obtained saturation current is irregularly distributed along with the increase of time, and it can be seen that the contact parasitic resistance has a large influence on the test result.
Example 1
Referring to fig. 10, in the hot carrier effect test of the semiconductor wafer according to the present embodiment, a die on the semiconductor wafer is selected, and the die is pinned by a four-terminal pin or a probe card using a kelvin four-wire detection method, so that four probes are inserted into the pads of the die.
After the probe is pricked into the bonding pad of the crystal grain, whether the probe mark is normal is checked, if the probe mark is abnormal, the previous step is returned to prick the probe again, and if the probe mark is normal, the four-end method is adopted to carry out resistance test on the crystal grain.
When the four-terminal method is adopted to carry out resistance test on the crystal grain, current is applied between the first probe and the fourth probe, voltage between the second probe and the third probe is tested, and a first resistance value is calculated and obtained according to the applied current value and the measured voltage value.
When the two-end method is adopted to carry out resistance test on the crystal grain, current is applied between the second probe and the third probe, voltage between the second probe and the third probe is tested at the same time, and a second resistance value is calculated and obtained according to the applied current value and the tested voltage value.
And comparing whether the first resistance value is the same as the second resistance value, if the first resistance value is different from the second resistance value, returning to the needle insertion again, and adjusting the needle insertion depth of the probe during the resistance test by the two-end method until the second resistance value is equal to the first resistance value, wherein the needle insertion depth at the moment is recorded as the first needle insertion depth.
And continuously pricking the crystal grains at the four corners of the edge of the wafer by adopting the first pricking depth, and carrying out resistance test on the crystal grains at the edge of the wafer by adopting a four-end method to obtain a third resistance value. And carrying out resistance test on the crystal grains by adopting a two-end method to obtain a fourth resistance value. And comparing whether the third resistance value is the same as the fourth resistance value or not, and if the third resistance value is equal to the fourth resistance value, taking the first pricking depth as the pricking depth in the subsequent semiconductor wafer test. And if the third resistance value is not equal to the fourth resistance value, returning to the initial step until the third resistance value is equal to the fourth resistance value, taking the pricking depth with the third resistance value being equal to the fourth resistance value as the pricking depth of the final semiconductor wafer in the test, and setting the pricking depth as the automatic pricking depth.
The hot carrier effect test is performed on the semiconductor wafer by using the depth of the pricking pin, and test data as shown in fig. 11 is obtained. Therefore, when the hot carrier effect test is performed on the semiconductor wafer by using the test method described in this embodiment, the saturation currents obtained in different time periods are regularly distributed, and as the time increases, the saturation current value regularly increases, and at this time, the test parameters meet the intrinsic performance of the device. Furthermore, the embodiment effectively avoids the influence of the contact parasitic resistance on the hot carrier effect test result of the semiconductor wafer.
In summary, the test method for reducing the influence of the contact parasitic resistance on the device test of the invention comprises the following steps: s101: providing a semiconductor wafer, and selecting a grain to be tested on the semiconductor wafer; s102: testing the resistance of the crystal grain to be tested by adopting a four-terminal method to obtain a first resistance value; s103: testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value; s104: and adjusting the pricking depth of the crystal grain to be tested pricked by the two-end method to be the first pricking depth so that the second resistance value is equal to the first resistance value. Furthermore, the resistance value of the resistance measured by the two-end method is adjusted by adjusting the depth of the pin of the two-end method, so that the resistance value measured by the two-end method is equal to the resistance value measured by the four-end method, the influence of the contact parasitic resistance on the resistance measured by the two-end method is further eliminated, and the reliability or yield of the semiconductor wafer or the device is tested by the depth of the pin when the resistance measured by the two-end method is equal to the resistance measured by the four-end method, so that the test accuracy is improved.
Further, in order to ensure the applicability of the above puncturing depth to the whole wafer, the testing method of the present invention further includes S106: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value; s107: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a two-end method, and enabling the probe to penetrate into the crystal grains by the first penetration depth to obtain a fourth resistance value; s108: and comparing the third resistance value with the fourth resistance value, judging whether the third resistance value is the same as the fourth resistance value, and determining whether to readjust the puncture depth according to the judgment result. Therefore, the invention uses the crystal grains at the four corners of the edge of the semiconductor wafer to perform the reinspection on the depth of the needle, when the third resistance value obtained by measuring the resistance by the four-end method of the crystal grains at the four corners of the edge of the wafer is equal to the fourth resistance value, the depth of the needle is proved to be suitable for the whole wafer, each crystal grain on the wafer can be tested by the depth of the needle, when the third resistance value obtained by measuring the resistance by the four-end method of the crystal grains at the four corners of the edge of the wafer is equal to the fourth resistance value, the steps S102-S108 are repeatedly executed until the third resistance value is equal to the fourth resistance value, and the depth of the needle at the moment is used as the depth of the needle in the subsequent whole semiconductor wafer test.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A test method for reducing the influence of contact parasitic resistance on device test is characterized by comprising the following steps:
s101: providing a semiconductor wafer, and selecting a crystal grain to be tested on the semiconductor wafer;
s102: testing the resistance of the crystal grain to be tested by adopting a four-terminal method to obtain a first resistance value;
s103: testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value;
s104: and adjusting the pricking depth of the crystal grain to be tested pricked by the two-end method to be a first pricking depth, so that the second resistance value is equal to the first resistance value.
2. The method according to claim 1, further comprising the step of, after adjusting the puncturing depth of the die to be tested by the two-terminal method to the first puncturing depth,:
s106: testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value;
s107: pricking to the to-be-tested crystal grains by the first pricking depth, and testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a two-end method to obtain a fourth resistance value;
s108: and comparing the third resistance value with the fourth resistance value, judging whether the third resistance value is the same as the fourth resistance value, and determining whether to readjust the puncture depth according to the judgment result.
3. The method for testing to reduce the influence of contact parasitic resistance on device testing according to claim 2, wherein in the step of determining whether to readjust the pricking depth according to the determination result, the method comprises:
if the third resistance value is equal to the fourth resistance value, taking the first pricking depth as the pricking depth for the subsequent test of the semiconductor wafer;
if the third resistance value is not equal to the fourth resistance value, the pricking depth is readjusted.
4. The method for testing to reduce the impact of contact parasitic resistance on device testing according to claim 3, wherein in the step of readjusting the pin depth, the method comprises:
testing the resistance of the crystal grain to be tested by adopting a four-terminal method to obtain a first resistance value;
testing the resistance of the crystal grain to be tested by adopting a two-end method to obtain a second resistance value;
adjusting the depth of the needle inserted into the to-be-detected crystal grain by the two-end method to be a second needle insertion depth, so that the second resistance value is equal to the first resistance value;
testing the resistance of the crystal grains at the edge of the semiconductor wafer by adopting a four-terminal method to obtain a third resistance value;
penetrating the second pricking pin to the grain to be tested in depth, and testing the resistance of the grain at the edge of the semiconductor wafer by adopting a two-end method to obtain a fourth resistance value;
if the fourth resistance value is equal to the third resistance value, taking the second pricking depth as the pricking depth for the subsequent test of the semiconductor wafer;
if the fourth resistance value is not equal to the third resistance value, the steps S102 to S108 are repeated until the third resistance value is equal to the fourth resistance value, and the pricking depth at this time is used as the pricking depth in the subsequent semiconductor wafer test.
5. The method for testing influence of contact parasitic resistance on device testing according to claim 1, further comprising, before testing the resistance of the die to be tested by a four-terminal method:
and pricking the to-be-detected crystal grain by adopting a Kelvin four-wire detection method and a four-end needle or a probe card, so that the four probes are pricked into the to-be-detected crystal grain.
6. The method as claimed in claim 5, further comprising, after the die under test is punched by a kelvin four-wire test method with a four-terminal punch or a probe card, the steps of:
and checking whether the pin mark is normal.
7. The method for testing influence of contact parasitic resistance on device testing according to claim 6, wherein in the step of testing the resistance of the die to be tested by using a four-terminal method, the method comprises:
applying a current between the first probe and the fourth probe, and testing the voltage between the second probe and the third probe;
and calculating to obtain a first resistance value according to the applied current value and the measured voltage value.
8. The method for testing influence of contact parasitic resistance on device testing according to claim 6, wherein in the step of testing the resistance of the die to be tested by using a two-terminal method, the method comprises:
applying a current between the second probe and the third probe, and testing a voltage between the second probe and the third probe;
and calculating to obtain a second resistance value according to the applied current value and the voltage value obtained by testing.
9. The method as claimed in claim 3 or 4, wherein the semiconductor wafer test comprises a hot carrier effect test.
10. The method for testing to reduce the influence of contact parasitic resistance on device testing according to claim 3, wherein after determining whether to readjust the pricking depth according to the determination result, the method further comprises:
and setting the finally determined needle inserting depth as the automatic needle inserting depth of the semiconductor wafer test.
CN202211336879.8A 2022-10-28 2022-10-28 Test method for reducing influence of contact parasitic resistance on device test Pending CN115616291A (en)

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