CN115603705A

CN115603705A - Impedance matching circuit for transmitting terminal

Info

Publication number: CN115603705A
Application number: CN202110778869.9A
Authority: CN
Inventors: 蔡千慧; 朱宏镇; 陈永泰
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2023-01-13

Abstract

A transmitting end impedance matching circuit can operate according to a signal of an overvoltage signal source and comprises a first potential converter, a voltage generating circuit and an impedance matching circuit. The first level shifter generates a first shift voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage and a medium voltage, wherein the second high voltage is lower than the first high voltage. The impedance matching circuit comprises N matching circuits, wherein each matching circuit comprises a second potential converter, a transistor, a first resistor and a second resistor. The second level shifter generates a gate voltage according to the second high voltage, a low voltage and an input signal. The transistor is turned on or off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmitting terminal.

Description

Impedance matching circuit for transmitting terminal

Technical Field

The present invention relates to impedance matching circuits, and more particularly, to an impedance matching circuit capable of operating according to a signal of an overvoltage signal source.

Background

A general broadband network system should ensure compatibility through an InterOperability test Laboratory Specification (IOL Spec), and a transmission end of the system should achieve output impedance matching. The impedance matching is usually implemented by an impedance matching circuit, which usually uses an input/output device (IO device) in a Complementary Metal Oxide Semiconductor (CMOS) process. Fig. 1 shows a conventional impedance matching circuit 100, which includes an N-channel metal oxide semiconductor (NMOS) transistor 110, a first resistor 120 and a second resistor 130, wherein the NMOS transistor 110 is turned on or off according to a trigger signal (toggle signal), the first resistor 120 is coupled between a first signal output terminal OUTP and the NMOS transistor 110, and the second resistor 130 is coupled between a second signal output terminal OUTN and the NMOS transistor 110.

As mentioned above, although the i/o device has a higher voltage endurance than the core device, the voltage endurance of the i/o device in some advanced processes (e.g., fin field effect transistor (FinFET)) is only 1.8V, and such devices cannot directly operate according to the trigger signal with a large voltage range. For example, if the impedance matching circuit 100 of fig. 1 is manufactured by advanced processes, the NMOS transistor 110 can only operate according to a trigger signal with a small voltage range (e.g., 0-1.8V), but cannot operate according to a trigger signal with a large voltage range (e.g., 0-3.3V), otherwise the NMOS transistor 110 is damaged.

Disclosure of Invention

It is an object of the present disclosure to provide a transmit-side impedance matching circuit to avoid the problems of the prior art.

An embodiment of a transmitting end impedance matching circuit disclosed by the invention comprises a first potential converter, a voltage generating circuit and an impedance matching circuit. The first level shifter is used for generating a first shifting voltage according to a source signal, wherein the first level shifter operates in a first voltage range between a first high voltage and a ground voltage, and the high voltage is higher than a medium voltage. The voltage generating circuit is used for generating a second high voltage according to the first conversion voltage, the first high voltage and the medium voltage, wherein the second high voltage is lower than the first high voltage. The impedance matching circuit comprises N matching circuits, wherein N is a positive integer. Each of the N matching circuits includes a second level shifter, a transistor, a first resistor and a second resistor. The second level shifter is coupled to the voltage generating circuit and configured to generate a gate voltage according to an input signal, wherein the second level shifter operates in a second voltage range between a second high voltage and a low voltage, the low voltage being greater than zero and lower than the second high voltage, and the gate voltage falling within the second voltage range. The transistor comprises a grid, a first transistor end, a second transistor end and a base, wherein the grid is used for receiving the grid voltage, the base is used for receiving a base voltage, the transistor is conducted or not conducted according to the grid voltage, and a withstand voltage of the transistor is lower than the first high voltage. The first resistor is coupled between a first differential signal transmitting terminal and the first transistor terminal. The second resistor is coupled between the second transistor end and a second differential signal transmitting end.

The features, operation and efficacy of the present invention will be described in detail with reference to the drawings.

Drawings

FIG. 1 shows a conventional impedance matching circuit;

fig. 2 shows an embodiment of a transmit-side impedance matching circuit of the present disclosure;

FIG. 3 shows an embodiment of the voltage generation circuit of FIG. 2;

FIG. 4 shows an embodiment of N matching circuits included in the impedance matching circuit of FIG. 2; and

FIG. 5 shows an embodiment of each matching circuit of FIG. 4.

Detailed Description

The present disclosure includes a transmit-side impedance matching circuit capable of operating according to a signal of an over-voltage signal source. The transmitting end impedance matching circuit can be applied to a wired network transmitter and can also be an integrated circuit; however, this is not a practical limitation of the transmit-side impedance matching circuit.

Fig. 2 shows an embodiment of a transmit-side impedance matching circuit according to the present disclosure. The transmitting end impedance matching circuit 200 of fig. 2 includes a first level shifter 210, a voltage generating circuit 220 and an impedance matching circuit 230. These circuits are described below.

Please refer to fig. 2. The first level shifter 210 is used for generating a source signal V according to a first input signal _REG/RESET Generating a first conversion voltage V _C Wherein the first level shifter operates in a first voltage range between a first high voltage VDDH2 (e.g., 3.3V) and a ground voltage GND (e.g., 0V), the high voltage being higher than the middle voltage VDDH1. The source signal V _REG/RESET For example, the output of a circuit of a core power domain (core power domain) is converted into a signal by a general level shifter. In one embodiment, when the source signal V is _REG/RESET At a low level (e.g., 0V), the first conversion voltage V _C Is the medium voltage VDDH1; when the source signal V is _REG/RESET When the voltage level is high (e.g., 1.8V), the first switching signal is the first high voltage VDDH2. The first level shifter 210 may be a known or self-developed circuit, which is not within the scope of the present disclosure.

Please refer to fig. 2. The voltage generating circuit 220 is used for generating a first converting voltage V according to the first converting voltage V _C The first high voltage VDDH2 and the middle voltage VDDH1 generate a second high voltage VDD3 (e.g., 3V) and a base voltage VDD3_ b, wherein the second high voltage VDD3 is lower than the first high voltage VDDH2. Fig. 3 shows an embodiment of the voltage generating circuit 220, which includes a first voltage generating circuit 310, a first voltage stabilizing capacitor 320, a first clamping switch 330, a second voltage generating circuit 340, a second voltage stabilizing capacitor 350, and a second clamping switch 360. The circuit of fig. 3 is described below.

Please refer to fig. 3. The first voltage generating circuit 310 is used for generating the second high voltage VDD3, and includes a first operating switch 312 and a first voltage dividing circuit 314; in fig. 3, the first operation switch 312 is a PMOS transistor, and the first voltage divider 314 includes two resistors (R3, R4), which is not a limitation of the first voltage generator 310. The first operation switch 312 is coupled between a first high voltage terminal and the first voltage divider circuit 314Is used for converting the voltage V according to the first conversion voltage _C And either conductive or non-conductive. The voltage of the first high voltage terminal is the first high voltage VDDH2. The first voltage divider circuit 314 is coupled between the first operation switch 312 and a middle voltage terminal. The voltage of the middle voltage terminal is the middle voltage VDDH1. When the first operating switch 312 is turned on, the first voltage divider circuit 314 generates the second high voltage VDD3 according to the first high voltage VDDH2 and the middle voltage VDDH1, and outputs the second high voltage VDD3 through a first voltage division output terminal (i.e., a node between the two resistors (R3, R4)).

Please refer to fig. 3. The first voltage stabilizing capacitor 320 is coupled between the first voltage division output end and the middle voltage end; in fig. 3, the first voltage-stabilizing capacitor 320 is a Metal Oxide Semiconductor (MOS) capacitor, but this is not a limitation of the present invention. A first clamp switch 330 (e.g., deep N-well transistor) coupled between the first divided output terminal and the medium voltage terminal; in a first mode, the first clamp switch 330 is operated according to the first converting voltage V _C Is not conducted; in a second mode, the first clamp switch 330 is operated according to the first converting voltage V _C Is turned on to pull the voltage of the first voltage division output terminal (i.e., the node between the two resistors (R3, R4)) to the middle voltage VDDH1. In FIG. 3, the first clamp switch 330 is an N-channel metal oxide semiconductor (NMOS) transistor and the first operating switch 312 is a P-channel metal oxide semiconductor (PMOS) transistor, which are not fully turned on at the same time. It is noted that the base of the first clamp switch 330 may be connected to the medium voltage terminal; however, this is not a limitation of the present invention. It is noted that the first voltage-stabilizing capacitor 320 and the first clamp switch 330 can be omitted according to the implementation requirements.

Please refer to fig. 3. The second voltage generating circuit 340 is used for generating the base voltage VDD3_ b, and includes a second operation switch 342 and a second voltage dividing circuit 344; in fig. 3, the second operation switch 342 is a PMOS transistor, and the second voltage divider 344 includes two resistors (R5, R6), which is not a limitation of the second voltage generator 340. A second operation switch 342 coupled between the first high voltage terminal and a second voltage divider 344 for converting the first conversion voltage V _C And either conductive or non-conductive. The second voltage divider 344 is coupled between the second operation switch 342 and the middle voltage terminal. When the second operation switch 342 is turned on, the second voltage divider 344 generates the base voltage VDD3_ b according to the first high voltage VDDH2 and the middle voltage VDDH1, and outputs the base voltage VDD3_ b through a second voltage dividing output terminal (i.e., a node between the two resistors (R5, R6)). In an implementation example, the base voltages VDD3_ b are all equal to the second high voltage VDD3; however, this is not a limitation of the practice of the present invention.

Please refer to fig. 3. The second voltage-stabilizing capacitor 350 is coupled between the second voltage-dividing output terminal and the middle voltage terminal; in fig. 3, the second voltage-stabilizing capacitor 350 is a MOS capacitor, but this is not a limitation of the present invention. A second clamp switch 360 (e.g., deep N-well transistor) coupled between the second divided output terminal and the medium voltage terminal; in a first mode, the second clamp switch is based on the first switching voltage V _C Is not conducted; in a second mode, the second clamp switch 360 is operated according to the first converting voltage V _C Conducting to pull the voltage at the second voltage division output terminal to the middle voltage VDDH1. In FIG. 3, the second clamp switch 360 is an NMOS transistor and the second operation switch 342 is a PMOS transistor, which are not completely turned on at the same time. It is noted that the base of the second clamp switch 360 may be connected to the medium voltage terminal; however, this is not a limitation of the practice of the present invention. It is noted that the second voltage generating circuit 340, the second voltage-stabilizing capacitor 350 and the second clamp switch 360 can be omitted according to the implementation requirements. When the second voltage generating circuit 340 is omitted, the base voltage VDD3_ b is provided by other circuits (e.g., a constant voltage source).

Please refer to fig. 2. The impedance matching circuit 230 includes N matching circuits, where N is a positive integer. Fig. 4 shows an embodiment of the N matching circuits, where N is greater than one, and N matching circuits 410 operate in parallel. Fig. 5 shows an embodiment of each matching circuit 410, which includes a second level shifter 510, a transistor 520, a first resistor 530 and a second resistor 540. These circuits are described below.

Please refer to fig. 5. The second level shifter 510 is coupled to the voltage generationA circuit 220 for generating a gate voltage V IN response to an input signal (IN) _G The second level shifter 510 operates in a second voltage range between the second high voltage VDD3 and a low voltage VDDL (e.g., 0.9V) that is greater than zero and lower than the second high voltage VDD3. The gate voltage V _G Falls within the second voltage range. In one exemplary embodiment, the gate voltage V is set to a low level (e.g., 0V) _G Is the low voltage VDDL; when the input signal is at a high level (e.g., 1.8V), the gate voltage V _G The second high voltage VDD3. The second level shifter 510 may be a known or self-developed circuit, which is not within the scope of the present disclosure.

Please refer to fig. 5. The transistor 520 includes a gate, a first transistor terminal, a second transistor terminal, and a base. The gate is used for receiving the gate voltage V _G . The base is used for receiving the base voltage VDD3_ b. The base voltage VDD3_ b is usually not lower than the voltage at either end of the transistor 520 to avoid leakage problems; however, this is not a limitation of the practice of the present invention. The transistor 520 is based on the gate voltage V _G And is conducted or not conducted, and has a withstand voltage (e.g., 1.8V) lower than the first high voltage VDDH2; however, with the circuit configuration of fig. 2, the voltage difference between any two terminals of the transistor 520 is not too large. Even though the voltage difference may slightly exceed the withstand voltage of the transistor 520, it is still within the tolerable range of the transistor 520.

Notably, the transistor 520 of fig. 5 is a PMOS transistor; however, this is not a limitation of the present invention. Compared to the prior art of fig. 1 using NMOS transistors, the embodiment of fig. 5 using PMOS transistors has higher breakdown voltage, and the reliability of the transistor 520 is better ensured. In addition, the transistor 520 may be a component of an advanced manufacturing process, such as a fin field effect transistor (FinFET) process.

Please refer to fig. 5. The first resistor 530 (e.g., a polysilicon resistor in a CMOS process) is coupled between a first differential signal transmitter MDIP and the first transistor end. A second resistor 540 (e.g., a polysilicon resistor in a CMOS process) is coupled between the second transistor end and a second differential signal transmitter MDIN. The resistance values of the first resistor 530 and the second resistor 540 may be the same or different. The signal of the first differential signal transmitting terminal MDIP is complementary to the signal of the second differential signal transmitting terminal MDIN. In this embodiment, the voltage of each of the signal of the first differential signal transmitting terminal MDIP and the signal of the second differential signal transmitting terminal MDIN falls within a third voltage range (e.g., 0.4V-2.9V), the upper limit of the third voltage range is higher than the withstand voltage of the transistor 520; however, the structure of the present embodiment can ensure that the voltage difference between any two terminals of the transistor 520 is less than or similar to the withstanding voltage, and the transistor 520 is not damaged.

It is noted that, when the implementation is possible, a person skilled in the art may selectively implement some or all of the technical features of any one of the foregoing embodiments, or selectively implement a combination of some or all of the technical features of the foregoing embodiments, thereby increasing the flexibility in implementing the invention.

In summary, the transmitting-end impedance matching circuit of the present disclosure can operate according to a signal of an overvoltage signal source without causing damage to transistors in the circuit.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations are possible within the scope of the patent protection sought by the present invention.

[ notation ] to show

100: impedance matching circuit

110: NMOS transistor

120: a first resistor

130: a second resistor

OUTP: a first signal output terminal

OUTN: second signal output terminal

200: impedance matching circuit for transmitting terminal

210: first potential converter

220: voltage generating circuit

230: impedance matching circuit

VREG/RESET: source signal

VDDH2: a first high voltage

VDDH1: medium voltage

VC: first converted voltage

VDD3: second high voltage

VDD3_ b: base voltage

310: first voltage generating circuit

312: first operation switch

314: a first voltage dividing circuit

320: first voltage-stabilizing capacitor

330: first clamping switch

340: second voltage generating circuit

342: second operation switch

344: second voltage division circuit

350: second voltage-stabilizing capacitor

360: second clamping switch

R3 and R4: electric resistance

R5 and R6: resistance (RC)

410: matching circuit

510: second potential converter

520: transistor with a high breakdown voltage

530: a first resistor

540: second resistance

IN: input signal

VG: grid voltage

VDDL: low voltage

MDIP: first differential signal transmitting terminal

MDIN: second differential signal transmitting terminal

Claims

1. A transmit-side impedance matching circuit, comprising:

the first potential converter is used for generating a first conversion voltage according to a source signal, wherein the first potential converter operates in a first voltage range;

a voltage generating circuit for generating a second high voltage according to the first conversion voltage, a first high voltage and a middle voltage, wherein the second high voltage is lower than the first high voltage; and

an impedance matching circuit comprising N matching circuits, wherein N is a positive integer, each of the N matching circuits comprising:

a second level shifter coupled to the voltage generating circuit for generating a gate voltage according to an input signal, wherein the second level shifter operates in a second voltage range between a second high voltage and a low voltage, the low voltage being greater than zero and lower than the second high voltage, the gate voltage falling within the second voltage range;

a transistor including a gate, a first transistor terminal, a second transistor terminal, and a base, wherein the gate is used for receiving the gate voltage, the base is used for receiving a base voltage, the transistor is turned on or off according to the gate voltage, and a withstand voltage of the transistor is lower than the first high voltage;

a first resistor coupled between a first differential signal transmitting terminal and the first transistor terminal; and

the second resistor is coupled between the second transistor end and a second differential signal transmitting end.

2. The transmit-side impedance matching circuit of claim 1, wherein the voltage generation circuit comprises:

a first voltage generating circuit for generating the second high voltage, and including a first operation switch and a first voltage dividing circuit, wherein:

the first operation switch is coupled between a first high voltage end and the first voltage division circuit and used for conducting or not conducting according to the first conversion voltage, and the voltage of the first high voltage end is the first high voltage;

the first voltage division circuit is coupled between the first operating switch and a medium voltage end, and the voltage of the medium voltage end is the medium voltage; and

when the first operation switch is turned on, the first voltage division circuit generates the second high voltage according to the first high voltage and the medium voltage, and outputs the second high voltage through a first voltage division output end.

3. The transmit end impedance matching circuit of claim 2, wherein the first voltage generating circuit further comprises a first voltage stabilizing capacitor coupled between the first voltage dividing output end and the middle voltage end.

4. The transmit end impedance matching circuit of claim 2, wherein the first voltage generating circuit further comprises a first clamp switch coupled between the first voltage division output end and the medium voltage end; in a first mode, the first clamp switch is not conducted according to the first conversion voltage; in a second mode, the first clamp switch is turned on according to the first switching voltage to pull the voltage of the first voltage division output end to the middle voltage.

5. The transmit-side impedance matching circuit of claim 2 wherein the voltage generation circuit further comprises:

a second voltage generating circuit for generating the base voltage, and including a second operation switch and a second voltage dividing circuit, wherein:

the second operation switch is coupled between the first high voltage end and the second voltage division circuit and used for conducting or not conducting according to the first conversion voltage;

the second voltage division circuit is coupled between the second operating switch and the medium voltage end; and

when the second operation switch is turned on, the second voltage division circuit generates the base voltage according to the first high voltage and the medium voltage, and outputs the base voltage through a second voltage division output end.

6. The transmit-end impedance matching circuit of claim 5, wherein the second voltage generating circuit further comprises a second voltage-stabilizing capacitor, the second voltage-stabilizing capacitor being coupled between the second divided-voltage output end and the medium-voltage end.

7. The transmit end impedance matching circuit of claim 5, wherein the second voltage generating circuit further comprises a second clamp switch coupled between the second divided output end and the medium voltage end; in a first mode, the second clamp switch is not conducted according to the first conversion voltage; in a second mode, the second clamp switch is turned on according to the first switching voltage to pull the voltage of the second voltage division output end to the middle voltage.

8. The transmit-side impedance matching circuit of claim 1 wherein N is greater than 1, the N matching circuits being connected in parallel.

9. The transmit-side impedance matching circuit of claim 1 wherein the base voltage is not lower than the voltage at either side of the transistor.

10. The transmit impedance matching circuit of claim 1, wherein a voltage of each of the signal of the first differential signal transmit terminal and the signal of the second differential signal transmit terminal falls within a third voltage range, an upper limit of the third voltage range being higher than the withstand voltage of the transistor.