CN115601219A

CN115601219A - Image processing method, image processing device, reference monitor and medium

Info

Publication number: CN115601219A
Application number: CN202211183091.8A
Authority: CN
Inventors: 夏建龙; 王伟
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2023-01-13

Abstract

According to the embodiment of the application, the corresponding relation between the first number and the column of the first VBO signal line is pre-stored in the FPGA, so that for each first transmission group, the FPGA determines the first target column of each column of RGB data in the first transmission group according to the first VBO signal line corresponding to each column of RGB data contained in the first transmission group and the pre-stored corresponding relation, the problems that pixels of a received image are dislocated and the like are avoided, and the accuracy of image transmission is improved.

Description

Image processing method, image processing device, reference monitor and medium

Technical Field

The present application relates to the field of image processing technologies, and in particular, to an image processing method and apparatus, a reference monitor, and a medium.

Background

In the prior art, a System On Chip (SOC) mainly transmits an image with a Field Programmable Gate Array (FPGA)

The HS (VBO) signal line.

Specifically, the pins corresponding to the SOC and the FPGA are connected by VBO signal lines, the SOC groups pixel points in the image in columns, and the number of columns of pixel points included in each group is the same as the number of VBO signal lines. And the SOC sequentially sends the RGB data of each row of pixel points in each group to the FPGA according to the sequence of the pins. After receiving the RGB data, the FPGA takes the pin sequence as the sequence of the VBO signal lines, and combines and splices the received RGB data to obtain a complete image.

However, when designing and manufacturing each chip circuit board, in order to meet the requirement of equal spacing such as the size of the circuit board or the VBO signal lines, the connection sequence of the SOC and the pins of the FPGA is adjusted during the manufacturing process, which results in that the SOC and the pins of the FPGA are not correspondingly connected. For example, pin 1 of the SOC should be connected to pin 1 of the FPGA, but pin 1 of the SOC is connected to pin 3 of the FPGA during the manufacturing process. And further, the image spliced by the FPGA is inconsistent with the original image, and the accuracy of image transmission is reduced.

Disclosure of Invention

The application provides an image processing method, an image processing device, a reference monitor and a medium, which are used for solving the problems that in the prior art, due to the influence of circuit board design, an SOC (system on chip) is not correspondingly connected with a pin of an FPGA (field programmable gate array), an image obtained by splicing the FPGA is inconsistent with an original image, and the accuracy of image transmission is low.

In a first aspect, an embodiment of the present application provides an image processing method, which is applied to a field programmable gate array FPGA, and the method includes:

receiving each column of RGB data sent by the system level chip SOC through a first VBO signal lines with a first preset number, and determining each column of RGB data contained in each first transmission group;

for each first transmission group, determining a first target column of each column of RGB data in the first transmission group according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises the first preset number of rows of RGB data;

and determining a target image according to the sequence of the first target column where each column of RGB data in each first transmission group is located and the first transmission group.

In a second aspect, an embodiment of the present application further provides an image processing apparatus, which is applied to a field programmable gate array FPGA, where the apparatus includes:

the receiving module is used for receiving each column of RGB data sent by the SOC through a first VBO signal lines with a first preset number, and determining each column of RGB data contained in each first transmission group;

the determining module is used for determining a first target column of each column of RGB data in each first transmission group according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises the first preset number of rows of RGB data; and determining a target image according to the sequence of the first target column where each column of RGB data in each first transmission group is located and the first transmission group.

In a third aspect, an embodiment of the present application further provides a reference monitor, where the reference monitor includes an FPGA, and the FPGA is configured to perform the steps of the image processing method.

In a fourth aspect, the present application further provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the image processing method as described above.

In the embodiment of the application, the FPGA receives each column of RGB data sent by the SOC through a first VBO signal lines with a first preset number, and determines each column of RGB data contained in each first transmission group; for each first transmission group, determining a first target column of each column of RGB data in the first transmission group according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises a first preset number of columns; and determining a target image according to the target column of each column of RGB data in each first transmission group and the sequence of the first transmission groups. In the embodiment of the application, the corresponding relation between the first number of the first VBO signal line and the column is pre-stored in the FPGA, so that for each first transmission group, the FPGA determines the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-stored corresponding relation, thereby avoiding the problems of pixel dislocation and the like of a received image, and improving the accuracy of image transmission.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a reference monitor in the related art according to an embodiment of the present application;

fig. 2 is a schematic diagram of an image processing process provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a reference monitor according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a first test image and a first prediction image provided in an embodiment of the present application;

FIG. 5 is a schematic diagram illustrating a flow of determining a correspondence relationship between a first number and a column of a first VBO signal line according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of an internal structure of an FPGA provided in the embodiment of the present application;

fig. 7 is a schematic structural diagram of an interior of a data detection comparison module of an FPGA according to an embodiment of the present application;

FIG. 8 is a schematic diagram of second test images of two second transmission groups according to an embodiment of the present application;

fig. 9 is a schematic diagram of predicted images corresponding to second test images of two second transmission sets according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating a flow chart for determining a correspondence relationship between a second number and a column of a second VBO signal line according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of an image processing apparatus according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of protection of the present application.

In the related art, the reference monitor includes an SOC, an FPGA, and a Time Controller (TCON). Fig. 1 is a schematic diagram of a reference monitor in the related art. As shown in fig. 1, a pin of the SOC is connected to a pin of one side of the FPGA through a VBO signal line, and a pin of the other side of the FPGA is connected to the TCON. The RGB data of the image are transmitted to the FPGA chip from the SOC through the VBO signal line, and the FPGA chip processes the RGB data, transmits the processed RGB data to the TCON at the rear end through the VBO signal line, and finally displays the processed RGB data.

The SOC and the FPGA, and the FPGA and the TCON are usually connected by 8 VBO signal lines, and each VBO signal line is used for transmitting RGB data of a specific column in an image. The 8 VBO signal lines independently transmit RGB data. The order between the lines of the VBO signal lines does not affect the quality of data transfer, but affects the arrangement order of RGB data. Based on this, if the back-end chip does not recombine the image data according to the sequence transmitted by the front-end chip, the image displayed at the back end has pixel dislocation and display error.

Therefore, in order to solve the above problem, an embodiment of the present application provides an image processing method, where the method is applied to an FPGA, and the FPGA receives RGB data of each column sent by an SOC through a first preset number of first VBO signal lines, and determines RGB data of each column included in each first transmission group; for each first transmission group, determining a first target column of each column of RGB data in the first transmission group according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises a first preset number of columns; and determining a target image according to the first target column of each column of RGB data in each first transmission group and the sequence of the first transmission groups.

Fig. 2 is a schematic diagram of an image processing process provided in an embodiment of the present application, where the process includes:

s201: receiving each column of RGB data sent by the SOC through a first preset number of first VBO signal lines, and determining each column of RGB data contained in each first transmission group.

The image processing method provided by the embodiment of the application is applied to the FPGA, and the FPGA is deployed on a reference monitor.

Fig. 3 is a schematic structural diagram of a reference monitor provided in an embodiment of the present application, as shown in fig. 3, the reference monitor includes: a Micro Controller Unit (MCU), an SOC, a PC, an upper computer and a TCON. In the embodiment of the application, the MCU can configure the parameters of the FPGA after the FPGA is powered on; the SOC is a core device of the reference monitor, has rich input and output interfaces such as a High Definition Multimedia Interface (HDMI) and a VBO, and has a digital signal processing function; the PC is provided with upper computer software, and technicians can read and write the contents stored in the FPGA in real time through the upper computer software arranged in the PC; TCON is used for driving the liquid crystal display to display images; the FPGA is used for receiving the image sent by the SOC, carrying out image processing on the image, such as image quality enhancement effect, and sending the processed image to the TOCN.

In the embodiment of the application, the FPGA is connected to the SOC through a first predetermined number of first VBO signal lines, and the SOC transmits RGB data of each column of an image to the FPGA through the first predetermined number of first VBO signal lines. In the embodiment of the present application, when performing RGB data transmission of an image, the SOC divides the image into at least one first transmission group, and each first VBO signal line is used for transmitting RGB data of a specific column in each first transmission group. Each first transmission group comprises the first preset number of rows of RGB data.

Based on this, in the embodiment of the present application, the FPGA receives each column of RGB data sent by the SOC through the first predetermined number of first VBO signal lines, and determines each column of RGB data included in each first transmission group according to a transmission sequence of each column of RGB data in the corresponding first VBO signal line. Specifically, each column of RGB data having the same transmission order is located in one first transmission group. For example, in the embodiment of the present application, the first column of RGB data transmitted by each first VBO signal line is determined as a first transmission group, the second column of RGB data transmitted by each first VBO signal line is determined as a first transmission group, and the like.

S202: for each first transmission group, determining a first target column of each column of RGB data in the first transmission group according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises the first preset number of columns of RGB data.

Due to the design of the circuit board, pins with the same serial number of the FPGA and the SOC may not be correspondingly connected, and in order to avoid the situation that FGPA directly arranges each column of RGB data received according to the pin sequence, so that the obtained image has pixel dislocation, in the embodiment of the present application, a corresponding relationship between a first serial number of a first VBO signal line and a column is stored in the FPGA, so that after receiving each column of RGB data, the FPGA can determine, for each first transmission group, a first target column corresponding to each column of RGB data included in the first transmission group according to the corresponding relationship.

In this embodiment of the present application, the columns in the corresponding relationship are columns in the first transmission group, and the first number of each first VBO signal line is generally a serial number of a pin of the FPGA corresponding to the first VBO signal line.

Specifically, in the embodiment of the present application, after the FPGA determines the RGB data included in each first transmission group, the FPGA determines the first VBO signal line for transmitting each column of RGB data, and obtains the stored first number corresponding to each first VBO signal line. And the FPGA determines a first target column where each column of RGB data is located according to the stored corresponding relation between the first number and the column of the first VBO signal line. In the embodiment of the application, the first target column corresponding to each column of RGB data is the column in which the column of RGB data is located in the first transmission group. And finally, the FPGA generates an image which is consistent with the image sent by the SOC according to the sequence of the first transmission group in which each column of RGB data is positioned and the first target column in the first transmission group in which each column of RGB data is positioned.

It should be noted that each first transmission group includes a first preset number of columns.

In addition, in the embodiment of the present application, a VBO signal line order adjustment module at the receiving end may be added inside the FGPA, and the correspondence between the first number and the column of the first VBO signal line is stored in the adjustment module.

In this embodiment of the application, the correspondence between the first number of the first VBO signal line and the column may be stored in the MCU, and after the FPGA is powered on, the MCU may write the correspondence into the FPGA, so that the FPGA may combine the received RGB data of each column according to the correspondence and generate an image, where the image generated by the FPGA is consistent with the image sent by the SOC.

S203: and determining a target image according to the sequence of the first target column where each column of RGB data in each first transmission group is located and the first transmission group.

In the embodiment of the application, after the FPGA determines the first target column where each column of RGB data in each first transmission group is located, the FPGA determines the target image according to the first target column where each column of RGB data in each first transmission group is located and the order of the first transmission groups.

Specifically, for each first transmission group, the FPGA determines, according to a first target column in which RGB data of each column in the first transmission group is located, a sub-target image corresponding to the first transmission group. After the FPGA determines each sub-target image corresponding to each first transmission group, the FPGA splices each sub-target image according to the sequence of the first transmission group to obtain a target image.

In the embodiment of the application, the corresponding relation between the first number of the first VBO signal line and the column is pre-stored in the FPGA, so that for each first transmission group, the FPGA determines the first target column where each column of RGB data in the first transmission group is located according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and the pre-stored corresponding relation, thereby avoiding the problems of pixel dislocation and the like of a received image, and improving the accuracy of image transmission.

In order to avoid the problem of pixel misalignment of an image obtained by performing image reconstruction based on received RGB data, on the basis of the above embodiments, in this embodiment of the application, determining a first target column in which each column of RGB data in the first transmission group is located according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a correspondence relationship between a first number and a column of the first VBO signal line stored in advance includes:

determining a target first VBO signal line corresponding to each column of RGB data in the first transmission group; and determining a column corresponding to the target first number of the target first VBO signal line according to the corresponding relation, and determining the column as a first target column where the RGB data of the column is located.

In this embodiment of the application, when the FPGA determines the first target column where each column of RGB data in the first transmission group is located, for each column of RGB data in the first transmission group, the FPGA determines a target first VBO signal line for transmitting the column of RGB data, and determines, according to the stored correspondence, a column corresponding to a target first number of the target first VBO signal line, and determines the column as the first target column where the column of RGB data is located.

For example, in the embodiment of the present application, the SOC sends four columns of RGB data to the FPGA through four first VBO signal lines in the first transfer group. The numbers of the four first VBO signal lines are 1, 2, 3 and 4, the four rows of RGB data are RGB data A, RGB data B, RGB data C and RGB data D respectively, the first VBO signal line with the number of 1 transmits the RGB data A, the first VBO signal line with the number of 2 transmits the RGB data B, the first VBO signal line with the number of 3 transmits the RGB data C, and the first VBO signal line with the number of 4 transmits the RGB data D. The corresponding relations stored in the FPGA are that the number 1 corresponds to the first row, the number 2 corresponds to the fourth row, the number 3 corresponds to the second row and the number 4 corresponds to the third row. Based on this, the FPGA determines that the first target column in which the RGB data a is located is the first column, the first target column in which the RGB data B is located is the fourth column, the first target column in which the RGB data C is located is the second column, and the first target column in which the RGB data D is located is the third column.

In order to improve the accuracy of image transmission, on the basis of the foregoing embodiments, in an embodiment of the present application, the determining process of each first transmission group includes:

determining the transmission sequence of each RGB data in the corresponding first VBO signal line;

the RGB data having the same transfer order is determined as a first transfer group.

In the embodiment of the application, when the FPGA determines each first transmission group, the FPGA determines the transmission order of each RGB data in the corresponding first VBO signal line, and determines the RGB data with the same transmission order as one first transmission group. For example, the FPGA determines the first column of RGB data transmitted by each first VBO signal line as one transmission group, and the like.

In order to enable the FPGA to store the corresponding relationship between the first number of the first VBO signal line and the column, and further improve the accuracy of image transmission, on the basis of the foregoing embodiments, in an embodiment of the present application, a process of determining the corresponding relationship between the first number of the first VBO signal line and the column includes:

sending the generated first test image to the SOC through an upper computer, wherein the first test RGB data of each column in the first test image are different, and the first test image comprises a first preset number of columns;

sending a sending instruction carrying RGB data of each row to the SOC, and receiving second test RGB data of each row sent by the SOC through the first VBO signal lines of the first preset number;

and for each column of second test RGB data, determining a second target column corresponding to the column of second test RGB data in the first test image, and correspondingly storing the second target column and a first number of a first VBO signal line for transmitting the column of second test RGB data.

In the embodiment of the application, the FPGA generates a first test image and sends the first test image to the SOC. In order to save transmission resources, in this embodiment of the application, the first test image may be composed of one first transmission group, that is, the number of columns included in the first test image is consistent with the number of first VBO signal lines.

In order to enable the SOC to accurately receive the first test image generated by the FPGA, in the embodiment of the present application, the FPGA sends the generated first test image to the SOC through the upper computer.

In the embodiment of the application, after the FPGA sends the first test image to the SOC through the upper computer, the FPGA sends a sending instruction to the SOC, so that after the SOC receives the sending instruction, each column of first test RGB data of the first test image is sent to the FPGA through a first VBO signal line with a first preset number. Moreover, since the RGB data received by the pin with a certain serial number of the FPGA may not be in the same column as the RGB data transmitted by the pin with the same serial number of the SOC, for example, the pin with the serial number of the SOC 1 is responsible for transmitting the RGB data in the first column of the first test image, but the RGB data received by the pin with the serial number of the FPGA 1 is the third column of the first test image, in the embodiment of the present application, the RGB data received by the FPGA is referred to as the second test RGB data.

In this embodiment of the application, after receiving the second test RGB data, for each column of the second test RGB data, the FPGA determines a second target column corresponding to the column of the second test RGB data in the first test image, and correspondingly stores the second target column and a first number of a first VBO signal line transmitting the column of the second test RGB data.

Specifically, in the embodiment of the present application, when determining the second target column corresponding to each column of the second test RGB data, the FPGA may determine through one or more of the following manners:

the first method is as follows: and aiming at each column of second test RGB data, searching a second target column corresponding to the second test RGB data in the first test image according to the first test RGB data corresponding to each column of pixel points in the first test image.

Because the first test RGB data of each column of the first test image are different, the FPGA may search the first test RGB data of the target having the same value as the second test RGB data in the first test image for each column of the second test RGB data, and determine the column where the first test RGB data of the target is located as the second target column corresponding to the second test RGB data.

For example, there are 4 rows of first test RGB data in the first test image, and for a certain second test RGB data, the FPGA determines that the value of the second test RGB data is the same as the value of the first test RGB data of the third row in the first test image, and then the FPGA determines that the third row is the second target row corresponding to the second test RGB data.

The second method comprises the following steps: the FPGA sequences the pre-stored first numbers of the first VBO signal lines, and splices the second test RGB data transmitted by the first VBO signal lines according to the sequencing result to obtain a first prediction image. The FPGA compares the first prediction image with the first test image and adjusts the sequence of the second test RGB data in the first prediction image according to the sequence of the first test RGB data in the first test image, so that the first prediction image is consistent with the first test image. And for each second test RGB data, the FPGA determines the column of the second test RGB data where the adjusted first prediction image is located, and determines the column as a second target column corresponding to the second test RGB data.

Fig. 4 is a schematic diagram of a first test image and a first prediction image provided in an embodiment of the present application, as shown in fig. 4, each column of the first test RGB data in the first test image is different, and the second column and the third column of the first prediction image are different.

In addition, in this embodiment of the application, after determining the correspondence between the first number of the first VBO signal line and the column, the FPGA stores the correspondence in the register and sends the correspondence to the MCU, so that the MCU writes the correspondence in the program of the power-on configuration parameter. When the FPGA is powered on again, the MCU may send the power-on configuration parameters to the FPGA, so that the FPGA stores the corresponding relationship.

Fig. 5 is a schematic diagram of a flow of determining a correspondence relationship between a first number and a column of a first VBO signal line according to an embodiment of the present application, as shown in fig. 5, the process includes:

s501: the reference monitor is powered on.

S502: and the MCU configures the parameters of the FPGA so that the reference monitor can work normally.

S503: technicians control the FPGA to enter a VBO signal line detection mode through the upper computer.

In the embodiment of the application, a technician can send an instruction for entering a VBO signal line detection mode to the FPGA through the upper computer, so that the FPGA enters the VBO signal line detection mode, and the corresponding relation between the first number of the first VBO signal line and the column is determined.

S504: the FPGA generates a first test image.

S505: the upper computer obtains the first test image generated by the FPGA and sends the first test image to the SOC.

S506: the FPGA sends a sending instruction carrying RGB data of each row to the SOC, and receives second test RGB data of each row sent by the SOC through the first VBO signal lines of the first preset number.

S507: the FPGA sequences the pre-stored first numbers of the first VBO signal lines, and splices the second test RGB data transmitted by the first VBO signal lines according to the sequencing result to obtain a first prediction image.

S508: the FPGA compares the first predictive image to the first test image.

S509: the order of the second test RGB data in the first predictive image is adjusted according to the order of the first test RGB data in the first test image so that the first predictive image coincides with the first test image.

S510: and for each second test RGB data, the FPGA determines the column of the second test RGB data where the adjusted first prediction image is located, and determines the column as a second target column corresponding to the second test RGB data.

S511: and correspondingly storing the second target column and the first number of the first VBO signal line for transmitting the column of the second test RGB data into a register.

S512: and the upper computer reads the corresponding relation stored in the register.

S513: the display screen displays the first test image and the first prediction image, and a technician verifies whether the corresponding relationship is correct according to the display.

S514: the technician writes the corresponding relation into a program of the power-on configuration parameters of the MCU, and powers on the FPGA again.

In order to enable the image to be correctly displayed on the display screen of the reference monitor, on the basis of the above embodiments, in an embodiment of the present application, the method further includes:

acquiring a second preset number of second VBO signal lines connected with the FPGA and the time sequence controller TCON, grouping RGB data of each column in the target image according to the second preset number, and determining each second transmission group;

determining a second VBO signal line with a second number corresponding to each column of each second transmission group in the target image according to a pre-stored corresponding relationship between the second number and the column of the second VBO signal line;

and sending each column of RGB data in the target image to the TCON by adopting a second VBO signal line with a second number corresponding to each column of RGB data in each second transmission group.

In this embodiment, the FPGA is further connected to the TCON and sends RGB data to the TCON, so that the TCON controls the display to display an image.

Specifically, in this embodiment of the present application, the FPGA obtains a second preset number of second VBO signal lines that are connected to the TCON and stored in the FPGA, and groups each column of RGB data in the received target image according to the second preset number, to determine each second transmission group. In this embodiment, the second preset number may be the same as or different from the first preset number.

Due to the design of the circuit board, the pin connection sequence of the FPGA and the TCON is adjusted in the manufacturing process of the circuit board, which results in that the pins of the TCON and the FPGA are not correspondingly connected. For example, pin 1 of TCON should be connected to pin 1 of FPGA, but pin 1 of TCON is connected to pin 3 of FPGA during the manufacturing process. Further, the image obtained by TCON splicing is inconsistent with the target image, and the accuracy of image transmission is reduced. Based on this, in the embodiment of the present application, a corresponding relationship between a second number of a second VBO signal line and a column is further stored in the FPGA, and the FPGA determines, according to the corresponding relationship, a second number corresponding to each column of each second transmission group in the target image, and sends, to the TCON, each column of RGB data in the target image by using the second VBO signal line of the second number corresponding to each column of RGB data in each second transmission group, so that the TCON can control the display screen to display a correct target image.

Fig. 6 is a schematic diagram of an internal structure of an FPGA provided in an embodiment of the present application, and as shown in fig. 6, the FPGA includes a serial-to-parallel conversion decoding module, a parallel-to-serial conversion encoding module, a received data reassembly module, a sent data reassembly module, a data detection comparison module, and a data read/write module. The serial-parallel conversion decoding module is used for performing serial-parallel conversion on each column of RGB data, and converting each column of RGB data sent by the SOC into parallel digital signals from serial signals; the parallel-serial conversion coding module is used for performing parallel-serial conversion on data, converting parallel digital signals of each row of RGB data into serial signals and sending the serial signals to TCON for display; the received data recombination module is used for rearranging and combining each row of RGB data sent by the SOC to form a target image; the sending data recombination module is used for re-splitting the target image and sending each column of RGB data after splitting to the TCON; the image processing module is used for processing the image to realize the effects of enhancing the image quality and the like; the data detection comparison module is used for generating a test image and determining the corresponding relation between the serial number and the column of the VBO signal line; and the data read-write module is used for receiving the parameters configured by the MCU after being electrified, configuring the parameters and receiving the read-write of the internal data of the FPGA through the upper computer.

In order to enable the FPGA to store a corresponding relationship between a second number of a second VBO signal line and a column, and further improve accuracy of image transmission, on the basis of the foregoing embodiments, in an embodiment of the present application, a process of determining the corresponding relationship between the second number of the second VBO signal line and the column includes:

sending third test RGB data of the generated second test image to the TCON, enabling the TCON to carry out sequencing according to the received third test RGB data to obtain a predicted image, and sending the predicted image to the SOC; wherein the third test RGB data of each column in the second test image are different, and the second test image comprises a second preset number of columns;

receiving fourth test RGB data of each column of pixel points of the prediction image, which are sent by the SOC through the first VBO signal line;

and for each column of fourth test RGB data, determining a third target column corresponding to the column of fourth test RGB data in the second test image, and correspondingly storing the third target column and a second number of a second VBO signal line for transmitting the column of fourth test RGB data.

In the embodiment of the application, the FPGA generates a second test image, and sends each column of third test RGB data of the second test image to the TCON. Since the corresponding relationship between the second number and the column of the second VBO signal line is applicable to all the second transmission groups, in order to save transmission resources, in this embodiment of the present application, the second test image may be formed by one second transmission group, that is, the number of columns included in the second test image is the same as the number of second VBO signal lines.

For example, the pin with the serial number of 1 of the FPGA is responsible for sending the RGB data of the first column of the second test image, but the RGB data received by the pin with the serial number of 1 of the TCON is the third column of the second test image, and therefore, in this embodiment, each column of RGB data received by the TCON is referred to as fourth test RGB data. After receiving the third test RGB data of each column, the TCON sorts the third test RGB data of each column according to the sequence of the pins connected to each second VBO signal line, so as to obtain a predicted image.

In order to enable the FPGA to determine whether the predicted image determined by the TCON is pixel-scrambled, in the embodiment of the present application, the FPGA transmits the second predicted image to the TCON, and after the TCON determines the predicted image, the TCON also forwards the predicted image to the FPGA. In order to enable the predicted image received by the FPGA to be consistent with the predicted image determined by the TCON, in the embodiment of the application, the TCON sends the predicted image to the SOC through the upper computer and then sends the predicted image to the FPGA through the SOC.

In the embodiment of the application, after receiving the fourth test RGB data of each column through the upper computer and the SOC, the FPGA determines, for the fourth test RGB data of each column, a third target column corresponding to the fourth test RGB data of the column in the predicted image, and correspondingly stores the third target column and a second number of a second VBO signal line transmitting the fourth test RGB data of the column.

Specifically, in the embodiment of the present application, when determining the third target column corresponding to each column of the fourth test RGB data, the FPGA may determine through one or more of the following manners:

the first method is as follows: and aiming at each column of fourth test RGB data, searching a third target column corresponding to the fourth test RGB data in the second test image according to the third test RGB data corresponding to each column of pixel points in the second test image.

Because each column of the third test RGB data of the second test image is different, the FPGA may search for a target third test RGB data having the same value as the fourth test RGB data in the second test image for each column of the fourth test RGB data, and determine a column in which the target third test RGB data is located as a third target column corresponding to the fourth test RGB data.

For example, there are 4 columns of third test RGB data in the second test image, and for a certain column of the fourth test RGB data, the FPGA determines that the numerical value of the column of the fourth test RGB data is the same as the numerical value of the third test RGB data of the third column in the second test image, and then the FPGA determines that the third column is the third target column corresponding to the fourth test RGB data.

The second method comprises the following steps: and the FPGA splices the fourth test RGB data transmitted by each second VBO signal line according to the pre-stored corresponding relation between the first number and the column of the first VBO signal line, so that the FPGA restores to obtain a predicted image determined by the TCON. The FPGA compares the predicted image with the second test image and adjusts the sequence of the fourth test RGB data in the predicted image according to the sequence of the third test RGB data in the second test image, so that the predicted image is consistent with the second test image. And for each column of fourth test RGB data, the FPGA determines the column of the fourth test RGB data where the adjusted predicted image is located, and determines the column as a third target column corresponding to the fourth test RGB data.

In addition, in this embodiment of the application, after the TCON determines the predicted image, the TCON may further control the display screen to display the predicted image, and a technician may obtain, from the FPGA, a second test image generated by the FPGA through the upper computer, and determine a correspondence between a second number of the second VBO signal line and the column according to the second test image and the predicted image. The technician writes the correspondence into the FPGA through the MCU.

In addition, when the FPGA generates the second test image, the second test image may further include two second transmission groups or a plurality of second transmission groups. In the embodiment of the present application, when the FPGA generates the second test images of the two second transmission groups, the FPGA may generate two sub-test images, which are the first sub-test image and the second sub-test image respectively. And the FPGA splices the first sub-test image and the second sub-test image to obtain a second test image. In order to improve the display effect of the image, the sub-test RGB data of one second transmission group in the first sub-test image is RGB data corresponding to white pixel points, and the sub-test RGB data of the other second transmission group in the second sub-test image is RGB data corresponding to black pixel points; the sub-test RGB data of two second transfer groups in the second sub-test image are the same, but the sub-RGB data of different columns of the same second transfer group are different.

Fig. 7 is a schematic structural diagram of the inside of a data detection and comparison module of an FPGA according to an embodiment of the present disclosure, and as shown in fig. 7, the inside of the data detection and comparison module includes a VBO RX test chart generation module, a VBO RX test chart extraction module, a VBO RX data comparison module, a VBO TX reference chart generation module, a VBO TX test chart generation module, and a chart splicing combination module. The VBO RX test graphic card generating module is used for generating a first test image, reading the first test image to the PC through the upper computer and sending the first test image to the SCO chip; the VBO RX test graphic card extraction module is used for analyzing the received second test RGB data sent by the SOC and extracting image identification information; the VBO RX data comparison module is used for comparing the second test RGB data with the first test RGB data generated by the VBO RX test graphic card generation module, automatically identifying the corresponding relation between the first number and the row of the second VBO signal line of the FPGA, and writing the corresponding relation into the received data recombination module in a register mode; the VBO TX reference image card generating module is used for generating a first sub-test image; the VBO TX detection graphic card generating module is used for generating a second sub-test image; the graphic card splicing combination module is used for splicing the first sub-test image and the second sub-test image to obtain a second test image.

Fig. 8 is a schematic diagram of a second test image of two second transmission groups according to an embodiment of the present application, as shown in fig. 8, the second test image is composed of two sub-test images, which are a first sub-test image and a second sub-test image respectively. The RGB data of the sub-test of one second transmission group in the first sub-test image is the RGB data corresponding to the white pixel points, and the RGB data of the sub-test of the other second transmission group in the second sub-test image is the RGB data corresponding to the black pixel points; the sub-test RGB data of two second transfer groups in the second sub-test image are the same, but the sub-RGB data of different columns of the same second transfer group are different.

On the basis of fig. 8, fig. 9 is a schematic diagram of a predicted image corresponding to the second test image of two second transmission groups provided in the embodiment of the present application, and as shown in fig. 9, the second column and the third column of each second transmission group of the predicted image are different from those of each second transmission group of the first test image.

Fig. 10 is a schematic diagram of a flow chart for determining a corresponding relationship between a second number and a column of a second VBO signal line according to an embodiment of the present application, where as shown in fig. 10, the process includes:

s1001: and the upper computer sends a VBO TX signal line sequence debugging command to the FPGA.

S1002: and a VBO TX reference image card generating module of the FPGA generates a first sub-test image.

S1003: and a VBO TX detection graphic card generating module of the FPGA generates a second sub-test image.

S1004: and the graph card splicing combination module splices the first sub-test image and the second sub-test image together to obtain a second test image.

S1005: and receiving fourth test RGB data of each column of pixel points of the prediction image, which are sent by the SOC through the first VBO signal line.

S1006: and for each column of fourth test RGB data, determining a third target column corresponding to the column of fourth test RGB data in the second test image, and correspondingly storing the third target column and a second number of a second VBO signal line for transmitting the column of fourth test RGB data.

In order to send RGB data to the TCON, on the basis of the foregoing embodiments, in an embodiment of the present application, the sending, to the TCON, each column of RGB data in the target image according to the second VBO signal line of the second number corresponding to each column of RGB data in each second transmission group includes:

sequencing each second transmission group according to a column of RGB data with the minimum sequence number in each second transmission group; the sequence number is the sequence of each column of RGB data in the target image;

and according to the sorting result, sequentially aiming at each second transmission group, and sending each column of RGB data in the second transmission group to the TCON according to the second VBO signal line with the second number corresponding to each column of RGB data in the second transmission group.

In this embodiment of the application, when the FPGA sends each column of RGB data in the target image to the TCON according to the second VBO signal line of the second number corresponding to each column of RGB data in each second transmission group, the FPGA sequences each second transmission group according to a column of RGB data with the smallest sequence number included in each second transmission group, so that the FPGA determines the sequencing result as the transmission sequence of each column of RGB data in each second transmission group in the corresponding second VBO signal line.

Specifically, the FPGA sends each column of RGB data in each second transmission group to the TCON according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group in sequence for each second transmission group according to the sorting result.

Fig. 11 is a schematic structural diagram of an image processing apparatus according to an embodiment of the present application, where the apparatus includes:

a receiving module 1101, configured to receive each column of RGB data sent by the system on chip SOC through a first predetermined number of first VBO signal lines, and determine each column of RGB data included in each first transmission group;

a determining module 1102, configured to determine, for each first transmission group, a first target column in which each column of RGB data in the first transmission group is located according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a correspondence relationship between a first number and a column of the first VBO signal line that is pre-stored; each first transmission group comprises the first preset number of rows of RGB data; and determining a target image according to the sequence of the first target column where each column of RGB data in each first transmission group is located and the first transmission group.

In a possible implementation manner, the determining module 1102 is specifically configured to determine, for each column of RGB data in the first transmission group, a target first VBO signal line corresponding to the column of RGB data; and determining a column corresponding to the target first number of the target first VBO signal line according to the corresponding relation, and determining the column as a first target column where the RGB data of the column is located.

In a possible implementation manner, the determining module 1102 is further configured to send the generated first test image to the SOC through an upper computer, where first test RGB data of each column in the first test image are different, and the first test image includes a first preset number of columns; sending a sending instruction carrying RGB data of each row to the SOC, and receiving second test RGB data of each row sent by the SOC through the first VBO signal lines of the first preset number; and for each column of second test RGB data, determining a second target column corresponding to the column of second test RGB data in the first test image, and correspondingly storing the second target column and a first number of a first VBO signal line for transmitting the column of second test RGB data.

In a possible implementation manner, the determining module 1102 is further configured to determine a transmission order of each RGB data in the corresponding first VBO signal line; the RGB data having the same transfer order is determined as a first transfer group.

In a possible implementation manner, the determining module 1102 is further configured to obtain a second preset number of second VBO signal lines, which are stored and connected to the FPGA and the timing controller TCON, and group each column of RGB data in the target image according to the second preset number to determine each second transmission group; determining a second VBO signal line with a second number corresponding to each column of each second transmission group in the target image according to a pre-stored corresponding relationship between the second number and the column of the second VBO signal line;

the device further comprises:

a sending module 1103, configured to send each column of RGB data in the target image to the TCON by using a second VBO signal line of a second number corresponding to each column of RGB data in each second transmission group.

In a possible implementation manner, the determining module 1102 is further configured to send third test RGB data of the generated second test image to the TCON, so that the TCON performs sorting according to the received third test RGB data to obtain a predicted image, and sends the predicted image to the SOC; each column of third test RGB data in the second test image is different, and the second test image comprises a second preset number of columns; receiving fourth test RGB data of each column of pixel points of the prediction image, which are sent by the SOC through the first VBO signal line; and for each column of fourth test RGB data, determining a third target column corresponding to the column of fourth test RGB data in the second test image, and correspondingly storing the third target column and a second number of a second VBO signal line for transmitting the column of fourth test RGB data.

In a possible implementation manner, the sending module 1103 is specifically configured to sort each second transmission group according to a column of RGB data with a minimum sequence number included in each second transmission group; the sequence number is the sequence of each column of RGB data in the target image; and according to the sorting result, sequentially aiming at each second transmission group, and sending each column of RGB data in the second transmission group to the TCON according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group.

In the embodiment of the application, the data transmission device is arranged in the FPGA of the reference monitor.

On the basis of the foregoing embodiments, an embodiment of the present application further provides an electronic device, and fig. 12 is a schematic structural diagram of the electronic device provided in the embodiment of the present application, as shown in fig. 12, including: the system comprises a processor 1201, a communication interface 1202, a memory 1203 and a communication bus 1204, wherein the processor 1201, the communication interface 1202 and the memory 1203 are communicated with each other through the communication bus 1204;

the memory 1203 stores a computer program that, when executed by the processor 1201, causes the processor 1201 to perform the steps of:

receiving each column of RGB data sent by the SOC through a first preset number of first VBO signal lines, and determining each column of RGB data contained in each first transmission group;

aiming at each first transmission group, determining a first target column of each column of RGB data in the first transmission group according to a first VBO signal line corresponding to each column of RGB data contained in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises the first preset number of rows of RGB data;

In one possible implementation, the processor is further configured to:

the RGB data having the same transmission order is determined as a first transmission group.

In one possible implementation, the processor is further configured to:

determining a second VBO signal line with a second number corresponding to each column of each second transmission group in the target image according to a pre-stored corresponding relation between the second number and the column of the second VBO signal line;

In one possible implementation, the processor is further configured to:

sending third test RGB data of the generated second test image to the TCON, enabling the TCON to carry out sequencing according to the received third test RGB data to obtain a predicted image, and sending the predicted image to the SOC; each column of third test RGB data in the second test image is different, and the second test image comprises a second preset number of columns;

In one possible implementation, the processor is further configured to:

and according to the sorting result, sequentially aiming at each second transmission group, and sending each column of RGB data in the second transmission group to the TCON according to the second VBO signal line of the second number corresponding to each column of RGB data in the second transmission group.

Since the principle of solving the problem of the electronic device is similar to that of the image processing method, the implementation of the electronic device may refer to the embodiment of the method, and repeated descriptions are omitted.

The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this is not intended to represent only one bus or type of bus. The communication interface 1202 is used for communication between the electronic apparatus and other apparatuses. The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Alternatively, the memory may be at least one memory device located remotely from the aforementioned processor.

The Processor may be a general-purpose Processor, including a central processing unit, a Network Processor (NP), and the like; but may also be a Digital instruction processor (DSP), an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like.

On the basis of the foregoing embodiments, the present invention further provides a computer-readable storage medium, in which a computer program executable by a processor is stored, and when the program is run on the processor, the processor is caused to execute the following steps:

In a possible implementation manner, the determining, according to the first VBO signal line corresponding to each column of RGB data included in the first transmission group and a correspondence relationship between a first number and a column of the first VBO signal line that is pre-stored, a first target column in which each column of RGB data in the first transmission group is located includes:

In one possible implementation, the determining of the correspondence between the first number and the column of the first VBO signal line includes:

In a possible implementation, the determining process of each first transmission group includes:

In one possible embodiment, the method further comprises:

In a possible implementation, the determining of the correspondence between the second number and the column of the second VBO signal line includes:

In a possible implementation manner, the sending, to the TCON, each column of RGB data in the target image according to the second VBO signal line of the second number corresponding to each column of RGB data in each second transmission group includes:

Since the principle of solving the problem of the computer-readable storage medium is similar to that of the image processing method, the implementation of the computer-readable storage medium can be referred to as an embodiment of the method, and repeated details are omitted.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. An image processing method is applied to a Field Programmable Gate Array (FPGA), and is characterized by comprising the following steps of:

2. The method of claim 1, wherein the determining the first target column of the first transmission group where the RGB data in each column is located according to the first VBO signal line corresponding to the RGB data in each column included in the first transmission group and a pre-stored correspondence relationship between a first number and a column of the first VBO signal line comprises:

3. The method of claim 1, wherein the determining the first number to column correspondence of the first VBO signal line comprises:

sending a sending instruction carrying RGB data of each column to the SOC, and receiving second test RGB data of each column sent by the SOC through the first VBO signal lines of the first preset number;

4. The method of claim 1, wherein the determining for each first transmission group comprises:

5. The method of claim 1, further comprising:

6. The method of claim 5, wherein determining the correspondence of the second number to the column of the second VBO signal line comprises:

7. The method of claim 5, wherein the sending each column of RGB data in the target image to the TCON according to the second numbered second VBO signal lines corresponding to each column of RGB data in each second transmission group comprises:

8. An image processing device applied to a Field Programmable Gate Array (FPGA), the device comprising:

the receiving module is used for receiving each column of RGB data sent by the system-on-chip SOC through a first VBO signal lines with a first preset number and determining each column of RGB data contained in each first transmission group;

the determining module is used for determining a first target column where each column of RGB data in each first transmission group is located according to a first VBO signal line corresponding to each column of RGB data included in the first transmission group and a pre-stored corresponding relation between a first number and the column of the first VBO signal line; each first transmission group comprises the first preset number of rows of RGB data; and determining a target image according to the sequence of the first target column where each column of RGB data in each first transmission group is located and the first transmission group.

9. A reference monitor, characterized in that it comprises an FPGA for performing the steps of the image processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that it stores a computer program which, when being executed by a processor, carries out the steps of the image processing method according to any one of claims 1 to 7.