CN115589248A

CN115589248A - Air interface signal uplink processing method, downlink processing method and electronic equipment

Info

Publication number: CN115589248A
Application number: CN202211184481.7A
Authority: CN
Inventors: 申为科; 王彦宁
Original assignee: Feiteng Technology Guangzhou Co ltd; Phytium Technology Co Ltd
Current assignee: Feiteng Technology Guangzhou Co ltd; Phytium Technology Co Ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2023-01-10

Abstract

The application provides an air interface signal uplink processing method, a downlink processing method and electronic equipment, and the method comprises the following steps: the antenna feed system divides uplink air interface signals in a target bandwidth to obtain N groups of sub-signals; the N signal processing units respectively perform physical layer processing on the N groups of sub-signals; the N signal processing units respectively write the N groups of sub-signals processed in the same batch into N first type storage intervals of a first type target storage segment; each signal processing unit corresponds to one first-class storage interval respectively, and the first-class target storage segment is any one first-class storage segment; and the controller processes the sub-signals stored in the M first-type storage segments to complete the uplink transmission of the air interface signals. The N groups of sub-signals respectively correspond to the N groups of signal processing units, and the N groups of sub-signals are respectively processed by the N groups of signal processing units so as to reduce the calculation force requirement of a single signal processing unit and further reduce the equipment cost.

Description

Air interface signal uplink processing method, downlink processing method and electronic equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to an uplink processing method and a downlink processing method for an air interface signal, and an electronic device.

Background

With the development of society and the advancement of science, communication becomes an indispensable part of people's life and work. Data transmission based on communication, such as voice data, video data, text data and the like, plays a great role in improving the quality of life and improving the work efficiency. The communication fields include a wired communication field and a wireless communication field. With the rapid development and popularization of satellite technology, the popularization degree of applications in the wireless communication field is higher, and a large number of low-frequency channels are occupied.

With the development of the wireless communication field, the wireless communication field gradually extends to high-frequency communication, and a high-frequency area has richer spectrum resources, which is more beneficial to the transmission of high data. For example, in satellite communication, high frequency signals are used, that is, channels with bandwidth of 1GHz or higher are used for transmission. However, a higher channel bandwidth means a higher computational effort for the signal processing unit and also means an increase in the product cost.

How to overcome the above problems becomes a difficult point to be concerned by those skilled in the art.

Disclosure of Invention

An object of the present application is to provide an uplink processing method, a downlink processing method, and an electronic device for an air interface signal, so as to at least partially improve the above problems.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in a first aspect, an embodiment of the present application provides an air interface signal uplink processing method, which is applied to a satellite base station, where the satellite base station includes an antenna feed system, N signal processing units, a first memory, and a controller, where the first memory is provided with M first-class memory segments, and each first-class memory segment is provided with N first-class memory sections, and the method includes: the antenna feeder system divides uplink air interface signals in a target bandwidth to obtain N groups of sub-signals; the N signal processing units respectively perform physical layer processing on the N groups of sub-signals; the N signal processing units respectively write the N groups of sub-signals processed in the same batch into N first-class storage sections of a first-class target storage segment; each signal processing unit corresponds to a first type storage interval, and the first type target storage segment is any one first type storage segment; and the controller processes the sub-signals stored in the M first type storage segments to complete the uplink transmission of the air interface signals.

The N groups of sub-signals respectively correspond to the N groups of signal processing units, and the N groups of sub-signals are respectively processed by the N groups of signal processing units so as to reduce the calculation force requirement of a single signal processing unit and further reduce the equipment cost.

Optionally, the method further comprises: determining whether the last first type target storage segment completes data writing; after the last first-class target storage segment finishes data writing, screening out new first-class target storage segments from the M first-class storage segments according to a preset sequence; and the new first type target storage segment is the first type storage segment which is arranged behind the last first type target storage segment and is in a non-writing unread state. Communication data can not be lost, and the function of guaranteeing the integrity of the data is achieved.

Optionally, the N signal processing units respectively perform physical layer processing on the N groups of sub-signals, and the N signal processing units respectively perform 5G physical layer processing on the N groups of sub-signals.

Optionally, the step of performing, by the N signal processing units, 5G physical layer processing on the N groups of sub-signals respectively includes: the N signal processing units respectively carry out background noise removal processing on the N groups of sub-signals; after the bottom noise removing processing, the N signal processing units respectively carry out interference removing processing on the N groups of sub-signals; after the interference removing processing, the N signal processing units respectively decode the N groups of sub-signals.

The method comprises the following steps: the N signal processing units respectively perform background noise removal processing on the N groups of sub-signals; after the bottom noise removing processing, the N signal processing units respectively carry out interference removing processing on the N groups of sub-signals; after the interference removing processing, the N signal processing units respectively decode the N groups of sub-signals. The interference of the bottom noise signal and the interference signal to the communication can be avoided, and the communication quality is improved.

Optionally, the step of processing, by the controller, the sub-signals stored in the M first-type memory segments includes: the controller reads the data in the first type of memory segment which is in a write-in unread state according to a preset sequence; and the controller transmits the read data to a core network. So as to ensure that the data is smoothly uploaded to the core network.

Optionally, the first-class memory segment is provided with a number identification bit and a state identification bit, where the number identification bit represents a bit number of the first-class memory segment in a preset sequence corresponding to M first-class memory segments, and the state identification bit represents a current state of the first-class memory segment, where the current state includes a write-in unread state and a non-write-in unread state.

In a second aspect, an embodiment of the present application provides a downlink processing method for air interface signals, where the method is applied to a satellite base station, and the satellite base station includes an antenna feeder system, N signal processing units, a first memory, and a controller, where the first memory is provided with M second-type memory segments, and each of the second-type memory segments is provided with N second-type memory sections, and the method includes: the controller writes the core network data into N second type storage intervals of the second type target storage section; wherein, the second type target memory segment is any one of the second type memory segments; the N signal processing units perform physical layer processing on data in N second type storage intervals of a second type storage segment in a write-in unread state according to a preset sequence; the N signal processing units output and transmit the processed data to the antenna feeder system; each signal processing unit corresponds to one second-type storage interval respectively; and the antenna feeder system carries out downlink transmission on the received data.

Optionally, the method further comprises: the controller determines whether the last second type target memory segment completes data writing; after the last second-type target storage segment finishes data writing, screening out new second-type target storage segments from the M second-type storage segments by the controller according to a preset sequence; and the new second type target storage segment is the second type storage segment which is arranged behind the last second type target storage segment and is in a non-writing unread state firstly.

Optionally, the step of performing physical layer processing on the data in the N second-type storage sections of the second-type storage segment in the write-unread state by the N signal processing units according to a preset sequence includes: and the N signal processing units encode the data in the N second-type storage sections of the second-type storage segment in the write-in unread state according to a preset sequence.

Optionally, the step of performing downlink transmission on the received data by the antenna feeder system includes: the antenna feed system performs digital-to-analog conversion on the received data to obtain a downlink air interface signal; and the antenna feed system sends the downlink air interface signal after the digital-to-analog conversion to a target terminal.

In a third aspect, an embodiment of the present application provides an electronic device, including an antenna feeder system, N signal processing units, a first memory, and a controller, where the first memory is provided with M first-type storage segments and/or M second-type storage segments, each of the first-type storage segments is provided with N first-type storage intervals, and each of the second-type storage segments is provided with N second-type storage intervals;

the electronic device executes the above uplink processing method for the air interface signal and/or the above downlink processing method for the air interface signal.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic connection diagram of an electronic device provided in an embodiment of the present application;

fig. 2 is a schematic diagram illustrating division of storage intervals in a first storage according to an embodiment of the present disclosure;

fig. 3 is a diagram illustrating a communication example of a satellite base station according to an embodiment of the present disclosure;

fig. 4 is a flowchart illustrating an uplink processing method for an air interface signal according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating air interface signal segmentation according to an embodiment of the present application;

fig. 6 is a flowchart of an uplink processing method for an air interface signal according to an embodiment of the present application;

fig. 7 is a schematic flowchart of a sub-step S102A according to an embodiment of the present application;

fig. 8 is a schematic flowchart of a sub-step S104 according to an embodiment of the present disclosure;

fig. 9 is a flowchart illustrating a downlink processing method for an air interface signal according to an embodiment of the present application;

fig. 10 is a flowchart of an air interface signal downlink processing method according to an embodiment of the present application;

fig. 11 is a schematic flowchart of a sub-step S302 according to an embodiment of the present application;

fig. 12 is a flowchart illustrating a sub-step of S304 according to an embodiment of the present application.

In the figure: 10-antenna feed system, 20-signal processing unit; 30-a first memory; and 40, a controller.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, and may for example be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

In order to overcome the problem of high computational power requirement caused by high-frequency communication (for example, transmission by using a channel with a bandwidth of 1GH or higher), the embodiment of the application provides an electronic device, and the electronic device can be a satellite base station or an on-board 5G base station. Referring to fig. 1, fig. 1 is a schematic connection diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 1, the electronic device includes an antenna feeder system 10, N signal processing units 20, a first memory 30, and a controller 40.

As shown in fig. 1, the antenna feed system 10, the N signal processing units 20, the first memory 30, and the controller 40 are sequentially connected. The antenna feed system may include an antenna structure and a feed line structure, and may transmit and receive data. The Signal Processing unit 20 may be, but is not limited to, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), and a Digital Signal Processor (DSP). The controller 40 may be, but is not limited to, a Central Processing Unit (CPU). The first memory 30 may be, but is not limited to, a memory.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating division of memory intervals in a first memory according to an embodiment of the present disclosure. As shown in fig. 2, the first memory is provided with M first-class memory segments and/or M second-class memory segments, each first-class memory segment is provided with N first-class memory sections, and each second-class memory segment is provided with N second-class memory sections.

Where M is greater than or equal to 2, N is greater than or equal to 2, and M may not be equal to N.

Fig. 2 shows a first type of memory segment as an example, and a corresponding second type of memory segment is the same. In fig. 2, M is 3 and n is 3, but this is not limitative. As shown in fig. 2, the number of the signal processing units 20 is 3, each first-type storage segment is provided with 3 first-type storage sections, and each signal processing unit 20 corresponds to one first-type storage section. For example, the signal processing unit No. 120 corresponds to the 1 st first class storage section in all the first class storage segments, the signal processing unit No. 2 corresponds to the 2 nd first class storage section in all the first class storage segments, and the signal processing unit No. 3 20 corresponds to the 3 rd first class storage section in all the first class storage segments.

It should be understood that each signal processing unit 20 corresponds to a storage section of the second type, and the same applies to the correspondence relationship between the storage sections of the first type.

Alternatively, the signal processing unit 20 may write the processed data into the corresponding first-type storage section, or process the data in the corresponding second-type storage section.

In a possible implementation manner, the electronic device provided in the embodiment of the present application is a satellite base station, and the satellite base station may communicate with other terminals. Referring to fig. 3, fig. 3 is a diagram illustrating a satellite base station communication example according to an embodiment of the present disclosure. As shown in fig. 3, the satellite base station may interact with a terrestrial base station, a gateway station, or various types of terminals (e.g., satellite phones), etc. through 5G wireless signals. The 5G wireless signal may be an air interface with a bandwidth of 1GHz.

The electronic device provided by the embodiment of the application adopts a signal division mode, and performs division processing on signals through the plurality of signal processing units 20, and performs transmission and scheduling of wireless communication in a high-level data combination mode, so as to overcome the problem that the calculation force requirement of high-frequency communication is too high. Specifically, the electronic device provided in this embodiment may execute the following uplink processing method and/or downlink processing method for an air interface signal.

It should be understood that the structure shown in fig. 1 is merely a structural schematic diagram of a portion of an electronic device, which may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1. The components shown in fig. 1 may be implemented in hardware, software, or a combination thereof.

The method for processing an uplink of an air interface signal provided in this embodiment of the present application may include, but is not limited to, being applied to the electronic device shown in fig. 1, and referring to fig. 4, the method for processing an uplink of an air interface signal may include: s101, S102, S103, and S104, which are described in detail below:

s101, the antenna feeder system divides uplink air interface signals in a target bandwidth to obtain N groups of sub-signals.

Optionally, the antenna feed system 10 performs filtering processing on all received signals to obtain uplink air interface signals within the target bandwidth. It should be understood that the uplink air interface signal includes all signals received by the antenna feeder system within the target bandwidth. The uplink air interface signal may include 5G signals from different transmitting terminals, and the frequencies of signals corresponding to different transmitting terminals are different. The target bandwidth is, for example, but not limited to, 1GHz or greater than 11GHz.

If a signal processing unit 20 is used to process the uplink air interface signal in the target bandwidth, the signal processing unit 20 needs to have a strong computational power to support the processing efficiency. In the scheme of the application, the uplink air interface signal is divided to obtain N groups of sub-signals, the N groups of sub-signals belong to different sub-frequency bands respectively, no cross frequency exists between the different sub-frequency bands, and the different sub-frequency bands are combined together to form the target bandwidth. The N groups of sub-signals respectively correspond to the N groups of signal processing units 20, and the N groups of sub-signals are respectively processed by the N groups of signal processing units 20, so as to reduce the computational power requirement of a single signal processing unit 20.

Referring to fig. 5, fig. 5 is a schematic diagram of an air interface signal division according to an embodiment of the present disclosure. Fig. 5 illustrates the target bandwidth as 1GHz and N as 3, but the target bandwidth is not limited to this. As shown in fig. 5, the uplink air interface signal is divided into 3 groups of sub-signals, and the 3 groups of sub-signals belong to 3 groups of sub-frequency bands, for example, as shown in fig. 5, a first sub-frequency band (sub-freq 1) is 400MHz, a second sub-frequency band (sub-freq 2) is 400MHz, and a third sub-frequency band (sub-freq 3) is 200MHz. The 3 groups of sub-bands correspond to the signal processing unit No. 120, the signal processing unit No. 2 20, and the signal processing unit No. 3, respectively.

And S102, the N signal processing units respectively carry out physical layer processing on the N groups of sub-signals.

It should be understood that the signal processing unit 20 is a physical layer unit, and may perform physical layer processing, such as decoding processing, on the N groups of sub-signals in a one-to-one manner.

S103, the N signal processing units respectively write the N groups of sub signals processed in the same batch into N first type storage intervals of the first type target storage segment.

Each signal processing unit 20 corresponds to a first-type storage interval, and the first-type target storage segment is any one first-type storage segment. For example, the signal processing unit No. 120 writes the processed data into the first type 1 storage section, the signal processing unit No. 2 20 writes the processed data into the first type 2 storage section, and the signal processing unit No. 3 20 writes the processed data into the first type 3 storage section.

It will be appreciated that each of the first type storage intervals is of limited length, so that the divided sub-signals need to be processed in batches. When the uplink air interface signal is directly processed by one FPGA (signal processing unit 20), the corresponding bandwidth is a target bandwidth, for example, 1Ghz, and the computing power requirement for a single FPGA is too high, and the corresponding cost is higher, whereas in the solution of the present application, each signal processing unit 20 only needs to correspond to 400Mhz or less, so that the computing power requirement for the signal processing unit is reduced, and the corresponding equipment cost is lower.

And S104, the controller processes the sub-signals stored in the M first-type storage segments to complete the uplink transmission of the air interface signals.

Optionally, the controller may upload the processed data to the core network.

To sum up, an embodiment of the present application provides an air interface signal uplink processing method, including: the antenna feed system divides uplink air interface signals in a target bandwidth to obtain N groups of sub-signals; the N signal processing units respectively perform physical layer processing on the N groups of sub-signals; the N signal processing units respectively write the N groups of sub-signals processed in the same batch into N first type storage intervals of a first type target storage segment; each signal processing unit corresponds to one first-class storage interval respectively, and the first-class target storage segment is any one first-class storage segment; and the controller processes the sub-signals stored in the M first-class storage sections to complete the uplink transmission of the air interface signals. The N groups of sub-signals respectively correspond to the N groups of signal processing units, and the N groups of sub-signals are respectively processed by the N groups of signal processing units so as to reduce the calculation force requirement of a single signal processing unit and further reduce the equipment cost.

It should be understood that the first memory 30 is provided with M first-type memory segments, and the data after each batch processing by the signal processing unit 20 is written into the corresponding first-type target memory segments. Determining which of the M first-type memory segments directly affects the order of writing data as the first-type target memory segment will not facilitate the correctness of the data merging process by the subsequent controller 40 when the writing order relationship is disordered. Therefore, the sequence of writing data into the signal processing unit 20 affects the quality of uplink communication of air interface signals. In order to facilitate determining the first type of target storage segment, the embodiments of the present application further provide a possible implementation manner, please refer to the following.

The first-class storage segments are provided with number identification bits and state identification bits, the number identification bits represent bit times or serial numbers of the first-class storage segments in a preset sequence corresponding to the M first-class storage segments, the state identification bits represent current states of the first-class storage segments, and the current states comprise a write-in unread state and a non-write-in unread state.

Optionally, an information indicator is added to the first type of memory segment as a number identification bit and a state identification bit. Each first type memory segment is reserved with an 8bit (such as a head bit) for indicating relevant information of the first type memory segment, such as a sequence number and a current state of the first type memory segment. Specifically, please refer to table 1 below, table 1 is used to show the content corresponding to the reserved 8 bits.

TABLE 1

Optionally, on the basis of table 1, regarding how to determine the first type target storage segment, the embodiment of the present application further provides a possible implementation manner, please refer to the following specifically.

Optionally, it is assumed that the last first-class target storage segment is the ith first-class storage segment, where i is greater than or equal to 1 and less than or equal to M, and i represents the sorting order number of the first-class storage segment. And after the data writing of the ith first-type storage segment is finished, directly taking the (i + 1) th first-type storage segment as a new first-type target storage segment, and taking the No. 1 first-type storage segment as a new first-type target storage segment when i is equal to M.

However, the method for determining the first-class target storage segment still has a defect, and specifically, after the data writing in the i-th first-class storage segment is completed, the current state of the i + 1-th first-class storage segment may be that the data is not written, that is, the controller 40 has not performed the uplink processing on the data in the i + 1-th first-class storage segment. At this time, if the i +1 th first storage segment is directly used as a new first target storage segment, the content in the i +1 th first storage segment needs to be erased, and then new content is written, which may result in data loss.

To avoid the situation of data loss, a possible implementation manner is further provided in this embodiment of the present application, please refer to fig. 6, where fig. 6 is one of flow diagrams of an air interface signal uplink processing method provided in this embodiment of the present application. As shown in fig. 6, the method for uplink processing of an air interface signal further includes: s201, S202, and S203, which are specifically described below:

s201, determining whether the last first-class target storage segment completes data writing. If yes, executing S202; if not, S203 is executed.

Alternatively, the signal processing unit 20 may determine whether to complete the data writing based on the amount of data written in the current batch.

Alternatively, assuming that the last first-class target memory segment is the i-th first-class memory segment, the signal processing unit 20 may obtain the current state of the i-th first-class memory segment, where the current state may further include a writing state, a writing unread state, and a non-writing unread state.

The writing state indicates that the data processed by the signal processing unit 20 is currently being written into the ith storage segment and data writing is not completed. After the data write is completed, its state may be modified to a write unread state, indicating that the data write has been completed. After the controller 40 extracts or reads the i-th first-class memory segment, the state of the i-th first-class memory segment may be modified to a non-written-unread state or a written-read state, which indicates that the contents therein may be erased. Obtaining the current state of the ith first type memory segment may determine whether the data writing is completed.

When the process is finished, determining a new first type target storage segment, namely executing S202; otherwise, the step S201 is repeatedly executed for a first preset time interval until the data writing is completed.

S202, after the last first-class target storage segment finishes data writing, screening out new first-class target storage segments from the M first-class storage segments according to a preset sequence.

The new first type target storage segment is the first type storage segment which is arranged behind the last first type target storage segment and is in a non-writing unread state.

Optionally, assuming that the last first-type target storage segment is the ith first-type storage segment, it is determined whether the current state of the (i + 1) th first-type storage segment is a write-unread state.

The ith first-class storage segment is a current first-class target storage segment, i is more than or equal to 1 and less than or equal to M, and when i +1 is more than M, the (i + 1) th first-class storage segment is a 1 st first-class storage segment.

If not, determining the (i + 1) th first-class storage segment as a new first-class target storage segment.

It should be understood that when the (i + 1) th first-class memory segment is not in the write-unread state, indicating that the data therein has been extracted by the controller 40 or no valid data is stored therein, it may be erased, and then it is used as a new first-class target memory segment, which does not result in loss of communication data, and plays a role in guaranteeing data integrity.

If yes, i = i +1, and repeatedly determining whether the current state of the i +1 th first-class memory segment is in a write unread state or not until the current state of the i +1 th first-class memory segment is not in the write unread state.

S203, waiting for a first preset time interval.

Alternatively, the first preset time interval may be adaptively set according to a size of a storage space of the first class of storage segments.

It should be noted that, regarding how to determine the new first type target storage segment, the steps shown in fig. 6 may be executed by one signal processing unit 20, and after determining the execution result, that is, after determining the new first type target storage segment, the new first type target storage segment is broadcast to other signal processing units 20.

Optionally, the signal in this application is a 5G signal, and on this basis, for the content in S102, this application embodiment further provides a possible implementation manner, please refer to the following, where S102 includes: S102A.

S102A, the N signal processing units respectively carry out 5G physical layer processing on the N groups of sub-signals.

Optionally, the uplink air interface signal further includes a bottom noise signal and an interference signal, where the bottom noise signal and the interference signal may cause interference to communication, and reduce communication quality. In order to overcome this problem, the embodiments of the present application further provide a possible implementation manner, please refer to the following.

For the content in S102A, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 7, in which S102A includes: S102A-1, S102A-2, and S102A-3, which are described in detail below:

S102A-1, N signal processing units respectively carry out background noise removing processing on the N groups of sub-signals.

S102A-2, after the background noise removing processing, the N signal processing units respectively carry out interference removing processing on the N groups of sub signals.

S102A-3, after the interference removing processing, the N signal processing units respectively decode the N groups of sub-signals.

It should be understood that, by using the decoding result after the processing in the steps shown in fig. 7, it will be avoided that the noise-floor signal and the interference signal will cause interference to the communication, and the communication quality will be improved.

On the basis of fig. 4, regarding how the controller 40 processes the data in the first memory 30, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 8, where S104 includes: s104-1 and S104-2, which are specifically set forth below:

s104-1, the controller reads the data in the first type memory segment which is in the non-read writing state according to a preset sequence.

Wherein, the preset sequence may be a numbering sequence of the M first-type memory segments. Optionally, the higher layer protocol processing unit (controller 40) periodically reads data from the memory (first storage 30) according to a timing sequence (different subcarrier spacing may cause the timing spacing to be different, for example, 500us per slot for 30KHz subcarrier), for example, one read cycle per 500 us.

Alternatively, the controller 40 (CPU) acquires the preset read sequence by the first 4 bits. And writing and reading are carried out according to the sequence during writing, and if a certain first-class storage segment is in a writing unread state, the memory block number is jumped to carry out reading and writing operation on the next first-class storage segment. The last 4 bits indicate the information status of the memory (as shown in table 1 above).

Optionally, the controller 40 performs merging processing on the resources according to resource blocks of N sub-bands (sub-freq) through a higher layer protocol stack, that is, performs merging processing on the data read from the first class storage segment. Optionally, the higher layer protocol stack performs scheduling processing separately according to N independent resource blocks during the scheduling processing. And the application layer is used for merging and splitting data.

And S104-2, the controller sends the read data to a core network.

Optionally, the controller 40 processes the read Data through a Radio Link Control Protocol (RLC) and a Packet Data Convergence Protocol (PDCP), and then sends the processed Data to the core network.

Optionally, the core network includes multiple network elements, and the necessary network elements include AMF, SMF, UDM, AUSF, and UPF. The network element equipment for direct connection between the 5G base station and the core network includes an AMF (access management for the user) and a UPF (user plane data processing for the user).

The uplink processing method for the air interface signal provided in the embodiment of the present application, through signal segmentation processing, ensures that the data processing real-time performance of the physical layer is improved, and reduces the cost of the signal processing unit. A signal processing unit with high specification computation power can be decomposed into three or more parallel units for signal processing.

The method for downlink processing of an air interface signal provided in this embodiment of the present application may include, but is not limited to, being applied to the electronic device shown in fig. 1, and referring to fig. 9, the implementation steps of the method for downlink processing of an air interface signal may include: s301, S302, S303, and S304, which are described in detail below:

s301, the controller writes the core network data into N second type storage intervals of the second type target storage segment.

The second type target storage segment is any one second type storage segment.

The controller 40 obtains core network Data through a Radio Link Control (RLC) Protocol and a Packet Data Convergence Protocol (PDCP). And after the core network data is obtained, processing the core network data in the MAC layer, and writing the data of a processing hand into N second-type storage intervals of the second-type target storage segment.

Optionally, the processing procedure of the controller 40 includes resource allocation of data written in N second-type storage intervals of the second-type target storage segment, where a preset value of a scheme subsystem is set by air interface segmentation when the resource is allocated, and resources in adjacent intervals are not scheduled.

When the MAC layer processes user data, the principle that resource allocation is performed on VPRBs (virtual Physical resource blocks) by REs is followed according to the principle that the most basic REs (resource elements) are used as the most basic units, and each VPRB corresponds to a PRB (Physical resource block) resource on an air interface (12 contiguous 15/30/60/120/240KHz subcarriers in a frequency domain, and 14 contiguous OFDM symbols in a time domain).

S302, the N signal processing units perform physical layer processing on data in the N second type storage sections of the second type storage segment in the write-in unread state according to a preset sequence.

It should be understood that the data in the N second-type storage sections are respectively subjected to physical layer processing by the N groups of signal processing units 20 to reduce the computational power requirement for a single signal processing unit 20. Optionally, referring to the content in S102, the physical layer processing of the response is performed in S302, which is not described herein again.

And S303, outputting and transmitting the processed data to an antenna feeder system by the N signal processing units.

Each signal processing unit corresponds to one second-class storage interval respectively.

And S304, the antenna feed system carries out downlink transmission on the received data.

For example to the ground base station, gateway station and various types of terminals shown in figure 3.

Optionally, the second-class memory segment is provided with a number identification bit and a state identification bit, the number identification bit represents a bit number or a sequence number of the second-class memory segment in a preset sequence corresponding to the M second-class memory segments, the state identification bit represents a current state of the second-class memory segment, and the current state includes a write-in unread state and a non-write-in unread state.

Optionally, regarding how to determine the second type of target storage segment, an embodiment of the present application further provides a possible implementation manner, please refer to fig. 10, where the method for downlink processing of an air interface signal further includes: s401, S402, and S403, which are specifically described below:

s401, the controller determines whether the last second type target memory segment completes data writing. If yes, go to S402; if not, S403 is executed.

Optionally, the same as S201, which is not described herein again.

S402, after the last second-type target storage segment completes data writing, the controller screens out new second-type target storage segments from the M second-type storage segments according to a preset sequence.

Optionally, assuming that the last second-type target memory segment is the i-th second-type memory segment, it is determined whether the current state of the i + 1-th second-type memory segment is a write-unread state.

The ith second-type storage segment is a current second-type target storage segment, i is more than or equal to 1 and less than or equal to M, and when i +1 is more than M, the (i + 1) th second-type storage segment is a 1 st second-type storage segment.

If not, determining the (i + 1) th second-class storage segment as a new second-class target storage segment.

It should be understood that when the i +1 th second-type memory segment is not in the write-unread state, indicating that the data therein has been extracted by the controller 40 or no valid data is stored therein, it can be erased, and then it is used as a new second-type target memory segment, which will not result in communication data loss, and thus, the function of guaranteeing data integrity is achieved.

If yes, i = i +1, and repeatedly determining whether the current state of the i +1 th second-class memory segment is in a write unread state or not until the current state of the i +1 th second-class memory segment is not in the write unread state.

And S403, waiting for a second preset time interval.

Alternatively, the second preset time interval may be adaptively set according to the size of the storage space of the first class of storage segments.

On the basis of fig. 9, as for the content in S302, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 11, where S302 includes: s302-1, specifically comprising the following steps:

s302-1, the N signal processing units carry out encoding processing on data in N second type storage sections of the second type storage segment in a write-in unread state according to a preset sequence.

On the basis of fig. 9, for the content in S301, the embodiment of the present application further provides a possible implementation manner, please refer to fig. 12, where S301 includes: s301-1 and S301-2, the following is specifically set forth:

s301-1, the antenna feed system performs digital-to-analog conversion on the received data to obtain a downlink air interface signal.

Optionally, the feed system combines the received data, and performs digital-to-analog conversion on the combined data. The digital signal is converted into an analog signal by digital-to-analog conversion.

And S301-2, the antenna feed system sends the downlink air interface signal after the digital-to-analog conversion to the target terminal.

Optionally, the downlink air interface signal is sent to the target terminal through the antenna structure, and the target terminal may be a ground base station, a gateway station, and various types of terminals shown in fig. 3.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. An air interface signal uplink processing method is applied to a satellite base station, the satellite base station includes an antenna feeder system, N signal processing units, a first memory and a controller, the first memory is provided with M first-class memory segments, each first-class memory segment is provided with N first-class memory sections, and the method includes:

the antenna feeder system divides uplink air interface signals in a target bandwidth to obtain N groups of sub-signals;

the N signal processing units respectively perform physical layer processing on the N groups of sub-signals;

the N signal processing units respectively write the N groups of sub-signals processed in the same batch into N first-class storage sections of a first-class target storage segment;

each signal processing unit corresponds to a first type storage interval, and the first type target storage segment is any one first type storage segment;

and the controller processes the sub-signals stored in the M first type storage segments to complete the uplink transmission of the air interface signals.

2. The uplink processing method for air interface signals according to claim 1, further comprising:

determining whether the last first type target storage segment completes data writing;

after the last first-class target storage segment finishes data writing, screening out new first-class target storage segments from the M first-class storage segments according to a preset sequence;

and the new first-class target storage segment is the first-class storage segment which is arranged behind the last first-class target storage segment and is in a non-writing unread state.

3. The uplink processing method for air interface signals according to claim 1, wherein the step of performing physical layer processing on the N groups of sub-signals by the N signal processing units respectively includes:

and the N signal processing units respectively carry out 5G physical layer processing on the N groups of sub-signals.

4. The air interface signal uplink processing method according to claim 3, wherein the step of performing, by the N signal processing units, 5G physical layer processing on the N groups of sub-signals respectively includes:

the N signal processing units respectively perform background noise removal processing on the N groups of sub-signals;

after the bottom noise removing processing, the N signal processing units respectively carry out interference removing processing on the N groups of sub-signals;

after the interference removing processing, the N signal processing units respectively decode the N groups of sub-signals.

5. The uplink processing method for air interface signals according to claim 1, wherein the step of processing, by the controller, the sub-signals stored in the M first-type memory segments includes:

the controller reads the data in the first type of memory segment which is in a write-in unread state according to a preset sequence;

and the controller transmits the read data to a core network.

6. The uplink processing method for an air interface signal according to claim 2 or 5, wherein the first-class memory segment is provided with a number identification bit and a state identification bit, the number identification bit indicates a bit number of the first-class memory segment in a preset sequence corresponding to M first-class memory segments, the state identification bit indicates a current state of the first-class memory segment, and the current state includes a write-in unread state and a non-write-in unread state.

7. A downlink processing method of air interface signals is characterized in that the downlink processing method is applied to a satellite base station, the satellite base station comprises an antenna feeder system, N signal processing units, a first memory and a controller, the first memory is provided with M second-type storage sections, and each second-type storage section is provided with N second-type storage sections, and the method comprises the following steps:

the controller writes the core network data into N second-type storage intervals of a second-type target storage segment;

wherein, the second type target memory segment is any one of the second type memory segments;

the N signal processing units perform physical layer processing on data in N second type storage intervals of a second type storage segment in a write-in unread state according to a preset sequence;

the N signal processing units output and transmit the processed data to the antenna feeder system;

each signal processing unit corresponds to a second type storage interval respectively;

and the antenna feeder system carries out downlink transmission on the received data.

8. The downlink processing method for air interface signals according to claim 7, wherein the method further comprises:

the controller determines whether the last second-type target memory segment completes data writing;

after the last second-type target storage segment finishes data writing, screening out new second-type target storage segments from the M second-type storage segments by the controller according to a preset sequence;

and the new second type target storage segment is the second type storage segment which is arranged behind the last second type target storage segment and is in a non-writing unread state firstly.

9. The downlink processing method for air interface signals according to claim 7, wherein the step of performing physical layer processing on the data in the N second-type storage sections of the second-type storage segment in the write-unread state by the N signal processing units according to a preset order includes:

and the N signal processing units carry out coding processing on the data in the N second-class storage intervals of the second-class storage segment in the write-in unread state according to a preset sequence.

10. The downlink processing method for air interface signals according to claim 7, wherein the step of sending the received data by the antenna feeder system in a downlink manner includes:

the antenna feed system performs digital-to-analog conversion on the received data to obtain a downlink air interface signal;

and the antenna feed system transmits the downlink air interface signal after the digital-to-analog conversion to a target terminal.

11. An electronic device is characterized by comprising an antenna feed system, N signal processing units, a first memory and a controller, wherein the first memory is provided with M first-class memory segments and/or M second-class memory segments, each first-class memory segment is provided with N first-class memory intervals, and each second-class memory segment is provided with N second-class memory intervals;

the electronic device performs the uplink processing method for the air interface signal according to any one of claims 1 to 6 and/or the downlink processing method for the air interface signal according to any one of claims 7 to 10.