CN115587369A

CN115587369A - Safety detection device for BIOS (basic input output System) and EC (embedded logic controller) firmware

Info

Publication number: CN115587369A
Application number: CN202211310278.XA
Authority: CN
Inventors: 王世鹏
Original assignee: Ziguang Computer Technology Co Ltd
Current assignee: Ziguang Computer Technology Co Ltd
Priority date: 2022-10-25
Filing date: 2022-10-25
Publication date: 2023-01-10

Abstract

The invention discloses a safety detection device of BIOS and EC firmware, comprising a safety module, a CPU, an EC chip, an EC flash memory, a BIOS chip and a change-over switch circuit; the change-over switch circuit is respectively connected with the safety module, the CPU, the EC chip, the EC flash memory and the BIOS chip and is a composite circuit consisting of a plurality of change-over switches; when the computer is started, the switch circuit sequentially controls the circuit between the safety module and the BIOS chip and the circuit between the safety module and the EC flash memory to be conducted according to the first control instruction of the safety module in a preset sequence, so that the safety module sends out SPI signals to sequentially verify the BIOS chip and the EC flash memory. The technical scheme provided by the invention realizes the safety detection of the BIOS chip and the EC chip of the computer firmware before the computer is started.

Description

Safety detection device for BIOS (basic input output System) and EC (embedded control Unit) firmware

Technical Field

The invention relates to the technical field of computers, in particular to a safety detection device for BIOS (basic input output System) and EC (embedded logic) firmware.

Background

The computer is used as a common device in daily life and office work, a large amount of data are stored in the computer, and the computer needs to be properly stored, but various attacking means are infinite at present, and great harm is brought to the safety of a personal computer. The software layers of an operating system, a network and the like are protected by a firewall, antivirus software and the like, the security is relatively high, the protection of computer firmware and the like is weak, and if hackers write attack codes into the computer firmware, the hackers can invade the computer by the codes in the remote control firmware.

To this end, patent document CN110750794A discloses a BIOS secure boot method and system, where the system uses a switch connected between a BIOS chip and a CPU, and connects an SPI end of a security module with the switch, as shown in fig. 1, the switch includes three signal ends and a control end, where one main signal end may be conducted with two other slave signal ends, the switch receives a control instruction through the control end, and selects one of the two slave signal ends to be conducted with the main signal end according to the control instruction, so as to implement line switching. The safety module sends a control instruction to the control end of the change-over switch through the power management module, and commands the change-over switch to conduct a circuit between the BIOS chip and the CPU or conduct a circuit between the BIOS chip and the safety module. When the computer is started, the safety module firstly commands the change-over switch to disconnect the circuit between the BIOS chip and the CPU, and switches on the circuit between the BIOS chip and the SPI end of the safety module, so that the safety module sends out an SPI signal to verify the BIOS chip, if the BIOS is verified to be free of problems, the safety module then commands the change-over switch to disconnect the circuit between the BIOS chip and the safety module, the circuit between the BIOS chip and the CPU is switched on, the CPU is powered on, the BIOS is started to enter a starting process, if the BIOS is verified to be defective, the computer is not started, and the risk that an attack code is remotely controlled to attack the computer due to the fact that the BIOS is started firstly when the computer is started is avoided through the method.

However, the computer does not only have a BIOS firmware, but also includes an Embedded Controller (EC), if a hacker writes an attack code into the EC firmware, security detection on the EC is not performed, and the BIOS chip and the EC chip still have a risk of being attacked, and the BIOS chip and the EC chip need to be sequentially detected, but the security monitoring system provided by the above file can only detect a BIOS firmware.

Disclosure of Invention

In view of this, the embodiment of the present invention provides a security detection apparatus for BIOS and EC firmware, so as to implement security detection on both BIOS chip and EC chip of computer firmware before booting the computer.

According to a first aspect, an embodiment of the present invention provides a security detection apparatus for BIOS and EC firmware, including a security module, a CPU, an EC chip, an EC flash memory, a BIOS chip, and a switch circuit; the change-over switch circuit is respectively connected with the safety module, the CPU, the EC chip, the EC flash memory and the BIOS chip and is a composite circuit consisting of a plurality of change-over switches; when a computer is started, the change-over switch circuit sequentially controls a circuit between the security module and the BIOS chip and a circuit between the security module and the EC flash memory to be conducted according to a first control instruction of the security module in a preset sequence, so that the security module sends out SPI signals to sequentially verify the BIOS chip and the EC flash memory, and if the verification is passed, the change-over switch circuit simultaneously conducts the circuit between the CPU and the BIOS chip and the circuit between the EC chip and the EC flash memory according to a second control instruction of the security module, so that the EC chip and the CPU are respectively started through information in the EC flash memory and the BIOS chip.

Optionally, the change-over switch circuit includes a first change-over switch, a second change-over switch and a third change-over switch, where the first change-over switch, the second change-over switch and the third change-over switch each include a control end, a master signal end, a first slave signal end and a second slave signal end; the control ends of the first change-over switch, the second change-over switch and the third change-over switch are all connected with a control instruction end of the security module, a main signal end of the first change-over switch is connected with an SPI end of the security module, a first slave signal end of the first change-over switch is connected with a second slave signal end of the second change-over switch, a second slave signal end of the first change-over switch is connected with a second slave signal end of the third change-over switch, a first slave signal end of the second change-over switch is connected with the CPU, a main signal end of the second change-over switch is connected with the BIOS chip, a first slave signal end of the third change-over switch is connected with the EC chip, and a main signal end of the third change-over switch is connected with the EC flash memory; when the control ends of the first change-over switch, the second change-over switch and the third change-over switch receive a first level signal sent by a control command end of the safety module, the main signal end and the first slave signal end are conducted, and when the control ends of the first change-over switch, the second change-over switch and the third change-over switch receive a second level signal sent by the control command end of the safety module, the main signal end and the second slave signal end are conducted.

Optionally, the control instruction end of the security module includes a first instruction end and a second instruction end, the first instruction end is connected with the control end of the first switch, and the second instruction end is connected with the control ends of the second switch and the third switch, respectively.

Optionally, when the computer is started, the first control instruction output by the security module includes a first sub-instruction and a second sub-instruction output in a preset order, where the first sub-instruction is that the first instruction end outputs a first level signal, and the second instruction end outputs a second level signal; the second sub-instruction is that the first instruction end outputs a second level signal, and the second instruction end outputs the second level signal.

Optionally, the CPU is a type of a soar D2000, and the safety detection device further includes a level shift chip, where the level shift chip is connected between the CPU and the second switch.

Optionally, the model of the level conversion chip is san bang micro SGM4562.

Optionally, the safety detection device further includes a first pull-up resistor, a second pull-up resistor, and a third pull-up resistor, where the first pull-up resistor, the second pull-up resistor, and the third pull-up resistor are respectively connected to control terminals of the first switch, the second switch, and the third switch, and are connected to a preset voltage signal.

Optionally, the model of the first, second and third switches is a philips TPW3257-TS3R.

Optionally, the security module is a TPCM chip.

The technical scheme provided by the application has the following advantages:

according to the technical scheme, the safety module is connected with a change-over switch circuit which is formed by compositely connecting a plurality of change-over switches, so that a CPU, an EC chip, an EC flash memory and a BIOS chip are all connected with the change-over switch circuit, when a computer is started, the safety module can firstly and sequentially conduct a circuit between the safety module and the BIOS chip and a circuit between the safety module and the EC flash memory by controlling the change-over switch circuit, so that the safety module sequentially conducts safety verification on instruction programs in the BIOS chip and the EC flash memory, if the safety verification is passed, the safety module controls the change-over switch circuit to conduct the circuit between the CPU and the BIOS chip and conduct the circuit between the EC chip and the EC flash memory at the same time, the system is powered on and started on the CPU at the moment, starting can be realized on the premise that safety verification is conducted on both BIOS firmware and EC firmware, and the starting safety of the computer is further ensured.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:

fig. 1 shows a schematic diagram of a diverter switch in the prior art;

FIG. 2 is a schematic diagram of a BIOS and EC firmware security detection device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another embodiment of a security detection apparatus for BIOS and EC firmware;

the numbers in the figures are as follows:

01-a safety module, 02-a CPU, 03-an EC chip, 04-an EC flash memory, 05-a BIOS chip, 06-a change-over switch circuit, 07-a level conversion chip, S1-a first change-over switch, S2-a second change-over switch, S3-a third change-over switch, R0-a first pull-up resistor, R1-a second pull-up resistor and R2-a third pull-up resistor.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.

Referring to fig. 2, in an embodiment, a security detection apparatus for BIOS and EC firmware specifically includes a security module 01, a CPU02, an EC chip 03, an EC flash memory 04, a BIOS chip 05, and a switch circuit 06, where the switch circuit 06 is connected to the security module 01, the CPU02, the EC chip 03, the EC flash memory 04, and the BIOS chip 05 respectively, and is a composite circuit composed of a plurality of switches.

In this embodiment, a plurality of switches are arranged to be connected according to a preset structure, so as to obtain a composite-formed switch circuit 06, and to connect a security module 01, a CPU02, an EC chip 03, an EC flash memory 04, and a BIOS chip 05, where the security module 01 is configured to send a control instruction and an SPI signal to the switch circuit 06, the control instruction is configured to control the switch circuit 06 to select two elements from the above elements according to a preset logic and to turn on a line therebetween, and the SPI signal is configured to perform security verification on a command program preset in the BIOS chip 05 or the EC flash memory 04, and to identify whether or not an internal command program is modified by an attack code.

When the computer is started, the change-over switch circuit 06 sequentially controls the line between the security module 01 and the BIOS chip 05, the line between the security module 01 and the EC flash memory 04 to be conducted and other lines are not conducted according to a first control instruction of the security module 01, when the lines are conducted, the security module 01 sends out an SPI signal twice to sequentially perform security verification on instruction programs in the BIOS chip 05 and the EC flash memory 04, if the verification is passed, the security module 01 sends out a second control instruction to control the change-over switch circuit 06 to simultaneously conduct the line between the CPU02 and the BIOS chip 05 and the line between the EC chip 03 and the EC flash memory 04 and control the CPU02 to start power-on and start so that the EC chip 03 and the CPU02 are respectively started through information inside the EC flash memory 04 and the BIOS chip 05. Therefore, the safety detection device provided by the embodiment realizes the starting on the premise that the BIOS firmware and the EC firmware are both subjected to safety verification, and further ensures the starting safety of the computer.

Specifically, as shown in fig. 3, in an embodiment, the switch circuit 06 includes a first switch S1, a second switch S2 and a third switch S3, and the first switch S1, the second switch S2 and the third switch S3 each include a control terminal SEL, a master signal terminal a, a first slave signal terminal B1 and a second slave signal terminal B2; control ends SEL of the first change-over switch S1, the second change-over switch S2 and the third change-over switch S3 are all connected with a control instruction end of the safety module 01, so that the first change-over switch S3, the second change-over switch S2 and the third change-over switch S3 can respond to a control instruction sent by the safety module 01 to achieve circuit switching. The main signal end A of the first switch S1 is connected with the SPI end of the security module 01, so that the SPI signal of the security module 01 is divided into two parts through the first switch S1, and the purpose of respectively checking the BIOS chip 05 and the EC flash memory 04 for two times is achieved. In order to further achieve the purpose, in this embodiment, the first slave signal terminal B1 of the first switch S1 and the second slave signal terminal B2 of the second switch S2 are connected, and the second slave signal terminal B2 of the first switch S1 and the second slave signal terminal B2 of the third switch S3 are connected. Then, the first slave signal terminal B1 of the second switch S2 is connected to the CPU02, the master signal terminal a of the second switch S2 is connected to the BIOS chip 05, the first slave signal terminal B1 of the third switch S3 is connected to the EC chip 03, and the master signal terminal a of the third switch S3 is connected to the EC flash memory 04.

Wherein, the control logic of the change-over switch is: when the control terminals SEL of the first switch S1, the second switch S2 and the third switch S3 receive a first level signal sent by a control instruction terminal of the security module 01, the main signal terminal a and the first slave signal terminal B1 are all turned on, and when the control terminals SEL of the first switch S1, the second switch S2 and the third switch S3 receive a second level signal sent by the control instruction terminal of the security module 01, the main signal terminal a and the second slave signal terminal B2 are all turned on.

Based on the connection relationship of the switch circuit 06, the control instruction end of the slave security module 01 includes a first instruction end GPIO1 and a second instruction end GPIO2, wherein the first instruction end GPIO1 is connected to the control end SEL of the first switch S1, and the second instruction end GPIO2 is connected to the control ends SEL of the second switch S2 and the third switch S3, respectively.

Based on the above-mentioned overall circuit structure and the control logic of the switch, the embodiment of the present invention further provides a security detection instruction running in the security module 01, and the purpose of respectively verifying the BIOS chip 05 and the EC flash memory 04 by the security module 01 can be achieved by running the security detection instruction, and the specific steps of the security module 01 running the security detection instruction are as follows:

the safety module 01 sends a first control instruction, the first control instruction is divided into two parts, the first part (a first sub-instruction) is that the safety module 01 sends a first level signal to the first switch S1, and sends a second level signal to the second switch S2 and the third switch S3 at the same time, so that the main signal end a of the first switch S1 is conducted with the first slave signal end B1, and the second switch S2 and the third switch S3 are both conducted with the main signal end a and the second slave signal end B2. The SPI signal of the security module 01 can reach the second switch S2 through a line between the master signal terminal a and the first slave signal terminal B1 of the first switch S1, and then reach the BIOS chip 05 through a line between the second slave signal terminal B2 and the master signal terminal a of the second switch S2, so that the program code in the BIOS chip 05 is verified, and meanwhile, the line between the security module 01 and the EC flash memory 04 is in a disconnected state, and the line between the EC flash memory 04 and the EC flash memory 03 is also in a disconnected state, so that the working logic of the security module 01 cannot be affected by the situation that the BIOS chip 05 and the EC flash memory 04 verify at the same time.

Similarly, the other part (the second sub-command) of the first control command is that the security module 01 sends a second level signal to the first switch S1, and sends the second level signal to the second switch S2 and the third switch S3 at the same time, at this time, the second switch S2 and the third switch S3 are both the master signal terminal a and the second slave signal terminal B2 are turned on, and since the first switch S1 and the second slave signal terminal B2 are turned on, the security module 01 can send an SPI signal to the third switch S3 through the first switch S1 to verify the command program in the EC flash memory 04.

The first sub-instruction and the second sub-instruction are sequentially executed according to a preset sequence, in this embodiment, the preset sequence may be that the first sub-instruction is executed first and then the second sub-instruction is executed, or vice versa, as long as the BIOS chip 05 and the EC flash memory 04 satisfy the condition of sequential verification, which is not particularly limited in this embodiment.

And finally, if the verification is not passed, the starting-up process is not executed, the safety of the computer is further ensured, if the verification is passed, the safety module 01 sends a second control instruction to the three change-over switches, the second control instruction comprises that a first level signal is sent to the second change-over switch S2 and the third change-over switch S3, so that the second change-over switch S2 and the third change-over switch S3 are both the main signal end A and the first slave signal end B1, namely the BIOS chip 05 is connected with the CPU02, the EC chip 03 and the EC flash memory 04, and the computer power supply powers on the CPU02 again, so that the computer can normally work. In addition, at this time, the second control instruction sent by the security module 01 to the first switch S1 may be the first level signal or the second level signal, and since both the second switch S2 and the third switch S3 are in an off state with the first switch S1 at this time, no matter what kind of signal is received by the first switch S1, the security module 01 is not connected with any one of the BIOS chip 05 and the EC flash memory 04, so that the logic stability of the circuit is ensured.

Through the circuit connection relation and the control logic, the security detection device for the BIOS and the EC firmware provided by the embodiment of the invention can divide the SPI signal of the security module 01 into two parts only by the mutual cooperation of the three change-over switches, and the security module 01 sequentially performs security verification on the instruction programs in the BIOS chip 05 and the EC flash memory 04 according to a certain sequence, and after the verification is completed, the security module 01 can conduct the BIOS chip 05 and the CPU02 by controlling the two change-over switches, so that the EC chip 03 and the EC flash memory 04 are conducted, and the computer can be normally powered on to work. The computer has the advantages that fewer elements are used, the circuit is easy to build, the detection of the BIOS and the EC firmware is completed, the scheme implementation cost is low, the difficulty is low, the safe startup can be ensured no matter the attack code is in the BIOS or the EC firmware, and the safety of the computer is further ensured.

In the embodiment of the invention, the first, second and third switches S3 are selected from the Schrep TPW3257-TS3R, the chip is packaged by TSSOP, the small package occupies small area of the main board, and the SOP package is convenient for rework debugging and has high autonomous controllability.

Specifically, in an embodiment, in order to apply the safety monitoring device provided by the embodiment of the present invention to the soar platform, when the model of the CPU02 is the soar D2000, the safety monitoring device provided by the embodiment of the present invention further includes a level conversion chip 07, and the level conversion chip 07 is connected between the CPU02 and the second switch S2. Considering that the soar D2000 processor is 1.8V level IO, in order to adapt the safety monitoring device of the present embodiment to the soar platform, the level conversion chip 07 is adopted to convert the level into a general 3.3V level, and the general 3.3V level is connected to the second switch S2. In the embodiment of the invention, the saint nation micro SGM4562 can be adopted for the level conversion chip 07, and the autonomous controllability is stronger.

Specifically, as shown in fig. 3, in an embodiment, the safety detection device further includes a first pull-up resistor R0, a second pull-up resistor R1, and a third pull-up resistor R2, wherein the first pull-up resistor R0, the second pull-up resistor R1, and the third pull-up resistor R2 are respectively connected to the control terminals SEL of the first switch S1, the second switch S2, and the third switch S3, and are connected to the preset voltage signal. Specifically, in this embodiment, the preset voltage signal is 3.3V, and the purpose is to default that the CPU02 and the BIOS chip 05 are not connected and the EC chip 03 and the EC flash memory 04 are not connected before the computer is turned on by presetting the 3.3V signal to the three switches, so as to avoid direct start of the computer system due to the SPI conduction caused by a short circuit, thereby further ensuring the security of the computer.

Specifically, in an embodiment, the security Module 01 adopted in the embodiment of the present invention is a Trusted Platform Control Module (TPCM), the Module is a PCIe X8 standard-sized plug-in card, a self-defined signal is provided, an FPGA chip is used on the card, the TPCM adds a root-of-trust Control function on the basis of TCM to implement combination of password and Control, thereby implementing active Control of the TPCM on the entire Platform, and the TPCM can be used to establish and guarantee a Trusted source point, and provide a series of Trusted computing functions such as Trusted Platform Control, integrity measurement, secure storage, trusted report, and cryptographic service.

Through the above components, according to the technical scheme provided by the application, the security module 01 is connected with a switch circuit 06, the switch circuit 06 is formed by compositely connecting a plurality of switches, so that the CPU02, the EC chip 03, the EC flash memory 04 and the BIOS chip 05 are all connected with the switch circuit 06, when the computer is started, the security module 01 can sequentially conduct a line between the security module 01 and the BIOS chip 05 and a line between the security module 01 and the EC flash memory 04 by controlling the switch circuit 06, so that the security module 01 sequentially conducts instruction programs in the BIOS chip 05 and the EC flash memory 04, if the security verification passes, the security module 01 then controls the switch circuit 06 to conduct the line between the CPU02 and the BIOS chip 05 and the line between the EC chip 03 and the EC flash memory 04 at the same time, and the system powers on the CPU02 to start, so that the computer can be started on the premise that the security verification is conducted on both the BIOS firmware and the EC firmware, and the security of the computer is further ensured.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A safety detection device for BIOS and EC firmware is characterized by comprising a safety module, a CPU, an EC chip, an EC flash memory, a BIOS chip and a change-over switch circuit;

the change-over switch circuit is respectively connected with the safety module, the CPU, the EC chip, the EC flash memory and the BIOS chip and is a composite circuit consisting of a plurality of change-over switches;

when a computer is started, the change-over switch circuit sequentially controls a circuit between the safety module and the BIOS chip and a circuit between the safety module and the EC flash memory to be conducted according to a first control instruction of the safety module in a preset sequence, so that the safety module sends out an SPI signal to sequentially verify the BIOS chip and the EC flash memory, and if the verification is passed, the change-over switch circuit simultaneously conducts the circuit between the CPU and the BIOS chip and the circuit between the EC chip and the EC flash memory according to a second control instruction of the safety module, so that the EC chip and the CPU are respectively started through information in the EC flash memory and the BIOS chip.

2. The safety detection device according to claim 1, wherein the switch circuit comprises a first switch, a second switch and a third switch, each of the first switch, the second switch and the third switch comprises a control terminal, a master signal terminal, a first slave signal terminal and a second slave signal terminal;

the control ends of the first change-over switch, the second change-over switch and the third change-over switch are all connected with a control instruction end of the safety module, a main signal end of the first change-over switch is connected with an SPI end of the safety module, a first slave signal end of the first change-over switch is connected with a second slave signal end of the second change-over switch, a second slave signal end of the first change-over switch is connected with a second slave signal end of the third change-over switch, a first slave signal end of the second change-over switch is connected with the CPU, a main signal end of the second change-over switch is connected with the BIOS chip, a first slave signal end of the third change-over switch is connected with the EC chip, and a main signal end of the third change-over switch is connected with the EC flash memory;

when the control ends of the first change-over switch, the second change-over switch and the third change-over switch receive a first level signal sent by a control command end of the safety module, the main signal end and the first slave signal end are conducted, and when the control ends of the first change-over switch, the second change-over switch and the third change-over switch receive a second level signal sent by the control command end of the safety module, the main signal end and the second slave signal end are conducted.

3. The safety detection device according to claim 2, wherein the control command end of the safety module comprises a first command end and a second command end, the first command end is connected with the control end of the first switch, and the second command end is respectively connected with the control ends of the second switch and the third switch.

4. The security detection apparatus according to claim 3, wherein when the computer is powered on, the first control command output by the security module includes a first sub-command and a second sub-command output in a predetermined sequence, the first sub-command is that the first command terminal outputs a first level signal, and the second command terminal outputs a second level signal; the second sub-instruction is that the first instruction end outputs a second level signal, and the second instruction end outputs the second level signal.

5. The safety detection device according to claim 2, wherein the CPU is a type of a soar D2000, and the safety detection device further comprises a level shift chip connected between the CPU and the second switch.

6. The security detection apparatus of claim 5, wherein the level shift chip is model Saint Pont micro SGM4562.

7. The safety detection device according to claim 2, further comprising a first pull-up resistor, a second pull-up resistor, and a third pull-up resistor, wherein the first pull-up resistor, the second pull-up resistor, and the third pull-up resistor are respectively connected to control terminals of the first switch, the second switch, and the third switch, and are connected to a preset voltage signal.

8. The safety detecting device according to claim 2, wherein the model of the first switch, the second switch and the third switch is scheimpflug TPW3257-TS3R.

9. The security detection apparatus of claim 1, wherein the security module is a TPCM chip.