CN115580585B - Balanced arbitration method based on arbiter - Google Patents

Balanced arbitration method based on arbiter Download PDF

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CN115580585B
CN115580585B CN202211442271.3A CN202211442271A CN115580585B CN 115580585 B CN115580585 B CN 115580585B CN 202211442271 A CN202211442271 A CN 202211442271A CN 115580585 B CN115580585 B CN 115580585B
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arbiter
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CN115580585A (en
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请求不公布姓名
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Muxi Integrated Circuit Nanjing Co ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/50Queue scheduling
    • H04L47/62Queue scheduling characterised by scheduling criteria
    • H04L47/625Queue scheduling characterised by scheduling criteria for service slots or service orders
    • H04L47/6275Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/24Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2425Traffic characterised by specific attributes, e.g. priority or QoS for supporting services specification, e.g. SLA
    • H04L47/2433Allocation of priorities to traffic types
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/50Queue scheduling
    • H04L47/62Queue scheduling characterised by scheduling criteria
    • H04L47/629Ensuring fair share of resources, e.g. weighted fair queuing [WFQ]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to the technical field of arbiters, in particular to an equalizing arbitration method based on an arbiter, wherein a first input channel of the arbiter is cascaded with a random ordering module, and the random ordering module comprises a plurality of second input and output channels, wherein the number of the second input and output channels is equal; the second input channel of the random ordering module shares a plurality of data sources; the random ordering module is used for generating random numbers, the number of bits of the random numbers is the same as that of the second output channels, and each bit of random number sequentially corresponds to one second output channel; moving the random number according to the sorting algorithm, and correspondingly moving the arrangement sequence of the second output channels when the random number moves, wherein the sequence of the second output channels after movement is the priority sequence of random output of the data source; outputting the corresponding data sources to an input channel of an arbiter according to the priority order of random output for arbitration; because the priority is random, the probability of each output channel outputting the data source is basically the same, and the aim of fair arbitration is achieved.

Description

Balanced arbitration method based on arbiter
Technical Field
The invention relates to the technical field of arbiters, in particular to an equalizing arbitration method based on an arbiter.
Background
The arbiter is mainly used for authorizing which data source is priority based on the corresponding priority when multiple data sources send out requests simultaneously, and the currently commonly used arbiter is divided into a fixed priority arbiter and a polling arbiter. In addition to the fixed arbiter, some of the current arbiters or polling arbiters with fixed priority are combined to obtain an overall arbitration module for a certain purpose, for example, for a purpose of selecting signals according to a certain rule, but the arbitration module after the combination is as a whole, and the arbitration priority of the arbitration module corresponds to the priority of the fixed arbiter. Whether the priority of the arbiter is fixed at present or the arbitration priority is equal to an arbitration module with fixed priority, because the priority of each channel is fixed, the channel with high priority is in tension, the channel with low priority works in idle condition, the fairness of the channel authorization is poor, and the corresponding input channel is unbalanced, so that the overall working efficiency is low.
Disclosure of Invention
In order to solve the technical problems, the invention aims to provide an equalizing arbitration method based on an arbiter, which adopts the following technical scheme:
an equalizing arbitration method based on an arbiter, wherein a first input channel of the arbiter is cascaded with a random ordering module, the random ordering module comprises a plurality of second input channels and a plurality of second output channels, wherein the number of the second input channels is equal to that of the second output channels; a plurality of second input channels of the random ordering module share a plurality of data sources; the random ordering module is used for generating random numbers, wherein the number of bits of the random numbers is the same as the number of the second output channels, and each bit of random number sequentially corresponds to one second output channel; moving the random number according to the sorting algorithm, and correspondingly moving the arrangement sequence of the second output channels when the random number moves, wherein the sequence of the second output channels after movement is the priority sequence of random output of the data source; and outputting the corresponding data sources to the input channels of the arbiter according to the priority order of the random output for arbitration.
The invention has the following beneficial effects:
according to the embodiment of the invention, the random sorting module is added between the input channel and the data source of the arbiter, the random sorting module is utilized to generate random numbers, the random numbers are utilized to be mapped with the data source of the input random module one by one, the random numbers are moved through the sorting algorithm to obtain the priority of the output channel of the random sorting module, the priority is the random priority, the corresponding data source is output according to the priority, and the probability of outputting the data source by each output channel is basically the same because the priority is the random priority, and the probability of inputting the data source by the input channel of the arbiter is basically the same because the output channel of the random sorting module is the input channel of the arbiter, so that the aim of fair arbitration is achieved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions and advantages of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of an arbiter according to one embodiment of the present invention;
fig. 2 is a schematic diagram of an arbitration system according to another embodiment of the present invention.
Detailed Description
In order to further describe the technical means and effects adopted by the present invention to achieve the preset purpose, the following detailed description refers to specific embodiments, structures, features and effects of an arbiter-based equalization arbitration method according to the present invention with reference to the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" means that the embodiments are not necessarily the same. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
Example 1
The following specifically describes a specific scheme of an equalizing arbitration method based on an arbiter provided by the invention with reference to the accompanying drawings.
An arbiter-based equalization arbitration method, the method comprising: the random ordering module is used for generating a random number sequence, wherein the random ordering module is cascaded with a first input channel and a random ordering module of the arbiter, and comprises a plurality of second input channels and a plurality of second output channels, wherein the number of the second input channels is equal to the number of the second output channels; a plurality of first input channels of the random ordering module share a plurality of data sources; the number of bits of the random numbers contained in the random number sequence is the same as the number of the second output channels, and each bit of random number sequentially corresponds to one second output channel; moving the random number according to the sorting algorithm, and correspondingly moving the arrangement sequence of the second output channels when the random number moves, wherein the sequence of the second output channels after movement is the priority sequence of random output of the data source; and outputting the corresponding data sources to the input channels of the arbiter according to the priority order of the random output for arbitration.
Specifically, in order to achieve the purpose of fair arbitration, a random ordering module is added at the input end of the arbiter, and for convenience of description, the input channel and the output channel of the random ordering module are respectively called a second input channel and a second output channel, wherein all the second input channels of the random ordering module share a plurality of data sources, and the probability that each output channel outputs a certain data source is the same. The function of the random ordering module is to determine the arbitration order for each group of data sources using the priority of the second output channel. Wherein the random ordering module comprises a random number generator for generating random numbers. Wherein the sorting algorithm comprises a bubbling sorting algorithm, a selection sorting algorithm, an insertion sorting algorithm and the like.
Referring to FIG. 1, as an example, a 4-input 4-output random ordering module is connected to a 4-input arbiter, a random number generator adopts an LFSR random number generator to generate 16-bit random numbers R15:0 as an example, and the number of bits of the random numbers is taken according to the number of output channels, and as the number of the output channels of the random ordering module is 4, the lower 4 bits R3:0 in the random numbers are taken, although in other embodiments, the upper 4 bits of the random numbers can be taken; the low 4-bit random number R3:0 is mapped with 4 output channels one by one, and all 1 in the random number are shifted right for example according to a sorting algorithm. The method for right shifting all 1 s in the random number specifically comprises the following steps: for 4 output channels of the random ordering module: and if the 8-bit random number R7:0 generated by the random number generator is 10111100, the lower four-bit random number R3:0 is taken to obtain 1100, the lower four-bit random number R3:0 and 4 output channels are mapped one by one to obtain that the corresponding random number R3 of the A channel is 1, the corresponding random number R2 of the B channel is 1, the corresponding random number R1 of the C channel is 0, and the corresponding random number R0 of the D channel is 0, namely the arrangement sequence of the random number 1100 corresponding to the initial second input channel is ABCD. And (3) using an bubbling sequencing bit sequence, namely right shifting all 1 in the random numbers according to the bubbling sequencing algorithm, wherein the result of the random numbers is 0011, and the arrangement sequence of the second output channels is CDAB when the second channels are correspondingly shifted in the random number shifting process.
It should be noted that, in other embodiments, the random number generator may also generate 10-bit random numbers, and the number of bits of the random numbers generated by the random number generator may be set according to requirements.
Preferably, the random number is moved using the following ordering algorithm: dividing the random number sequence into a plurality of subgroups by taking two adjacent elements as a group, comparing the two elements in the subgroups, and exchanging the positions of the two elements when the exchanging conditions are met to obtain a first arrangement sequence of the random numbers; comparing adjacent elements between adjacent subgroups in the first arrangement sequence of the random numbers, and exchanging the positions of the two elements when the exchange condition is met to obtain a second arrangement sequence of the random numbers; comparing two elements in the small group in the second arrangement sequence of the random numbers, and exchanging the positions of the two elements when the exchange condition is met to obtain a third arrangement sequence of the random numbers; comparing adjacent elements between adjacent subgroups in the third arrangement sequence of the random numbers, and exchanging the positions of the two elements when the exchange condition is met to obtain a fourth arrangement sequence of the random numbers; the fourth permutation of the random numbers is a desired permutation of the random numbers. Specifically, taking the high-order random number larger than the low-order random number as the exchange condition, the low-order random number R3:0 is 1100, the current arrangement sequence of the second output channel is ABCD, and 4 rounds of exchange operation are needed in total; the first round is: dividing the low 4 into two groups of random numbers R3:0, wherein R3 and R2 are divided into one group, R1 and R0 are divided into one group, comparing the sizes of the elements in R3 and R2, because R3 and R2 are respectively corresponding to 11, the element in R3 is equal to the element in R2, the exchange condition is not satisfied and the exchange is not performed; comparing R1 and R0, because the elements in R1 and R0 are corresponding to 00, the element in R1 is equal to the element in R0, the exchanging condition is not satisfied and the exchanging is not performed; thus, in the first round of swapping operation, the first permutation R3:0 of the random numbers obtained is 1100. The second round of exchanging operation is to compare adjacent elements between adjacent subgroups, R2 and R1 are adjacent elements between adjacent subgroups for R3 and R2, R1 and R0, so comparing the sizes of elements in R2 and R1, because the first arrangement sequence of random numbers R3:0 is 1100, wherein R2 and R1 are 1 and 0 respectively, the elements in R2 are larger than the elements in R1, satisfying the exchanging condition, exchanging the elements in the random numbers and simultaneously exchanging the arrangement sequence of the second output channel, obtaining R2 and R1 as 0 and 1 respectively, and simultaneously exchanging positions B and C after exchanging; therefore, in the second round of exchanging operation, the second permutation order R3:0 of the obtained random numbers is 1010, and the permutation order of the second channels is ACBD. For the third round of exchange operation, comparing the sizes of random numbers in the small group, and exchanging the random numbers meeting the exchange conditions, wherein the principle of the third round of exchange operation is the same as that of the first round of exchange operation; because the second arrangement order R3:0 of random numbers is 1010, the elements in two groups R3 and R2, R1 and R0 are respectively compared, the element in R3 is larger than the element in R2, the element in R1 is larger than the element in R0, both groups meet the exchange condition, the third arrangement order R3:0 of random numbers obtained after exchange is 0101, and the arrangement order of the second output channel is CADB. For the exchange operation of the fourth wheel, comparing the sizes of adjacent elements between adjacent subgroups and exchanging the elements meeting the exchange conditions, wherein the principle of the exchange operation of the fourth wheel is the same as that of the exchange operation of the second wheel; because the third arrangement sequence of random numbers is 0101, after elements in R2 and R1 adjacent to each other between adjacent subgroups are compared, the fourth arrangement sequence R3:0 of the obtained random numbers is 0011 after the exchange conditions are satisfied and the exchange is performed, the arrangement sequence of the corresponding second output channels is CDAB, and the arrangement sequence CDAB of the second output channels is the priority sequence of the data source output by the second output channels. In the next adjacent period, the random number generator regenerates the random number, and again takes the low four bits R3:0 of the random number, the low four bits and the arrangement sequence CDAB of the second output channel in the previous period are mapped one by one, and the random number and the arrangement sequence of the second output channel are exchanged according to the same ordering algorithm, so that the priority sequence of the second output channel output data source in each period is obtained.
In other embodiments, the swap condition may also be that the higher random number is smaller than the lower random number, i.e. 0 is all right shifted.
Because the random number generated by the random number generator is random, the generated random number is mapped with the second input channel one by one, the sequence of the second output channel obtained after the random number is ordered according to the ordering algorithm is also random, and the sequence of the second output channel is used as the priority sequence, so that the priority is random priority sequence. And because the second output channel of the random ordering module is cascaded with the first input channel of the arbiter, the data source input into the arbiter is a random data source. For the same second output channel, the priorities of adjacent periods have no dependency and are in random priority order, so that the aim of fair arbitration can be achieved.
It should be noted that, the priority may be set to an ascending order according to the arrangement order of the second output channels, for example, the arrangement order of the second output channels is CADB, and then the priority order corresponding to the second output channels is sequentially raised according to the order of CADB, where the priority of the B channel is highest, and the priority of the C channel is lowest. In other embodiments, the priority may be set in descending order according to the arrangement order of the second output channels, and the priority may be flexibly set according to needs.
Preferably, in practical applications, hundreds of data sources are involved, and the more candidate data sources of the arbiter, the more logic complexity the arbiter implements, the slower the overall circuit speed. In order to improve the arbitration speed of the arbiter, the data sources can be grouped according to a preset data amount, the grouping rule can be set according to the need, the number N of the second input channels in the random ordering module is divided into N groups by sharing a plurality of data sources, after the data sources are grouped, each group of data sources is input into a corresponding second input channel, the priority of each group of data sources is acquired according to the ordering module, and each group of data sources is sent into the corresponding arbiter for arbitration according to the priority sequence; for example, grouping 100 data sources, and grouping the data sources into 4 groups according to a preset data quantity of 25, wherein every 25 data sources are consecutive; wherein, the preset data volume can be set according to the requirement; other groupings may be employed in other embodiments. Or circularly distributing the data sources to the corresponding second input channels according to the arrangement sequence of the data sources, namely sequentially distributing the 1 st to 4 th data sources to the 4 second input channels, sequentially distributing the 5 th to 8 th data sources to the 4 second input channels, and so on; after being input into the random ordering module, the random numbers in the random ordering module are output randomly.
As an example, the data source may be data or a request of a CPU or a GPU, for example, for a random ordering module of a 4-input 4-output channel, where the data source includes 4 CPUs, each CPU has an independent identity, the transmitted data packet includes the identity of the corresponding CPU, and each CPU generates a large number of data packets. The data packets generated by each CPU are sent to any one of the second input channels of the random ordering module according to a certain sequence. For example, for CPU1, CPU2, CPU3, and CPU4, since the second input channels of the random order module share the data source, any one of the second input channels can receive the data packets of CPU1, CPU2, CPU3, and CPU4, and the probability of receiving the data packets of the corresponding CPU is the same.
In summary, in the embodiment of the present invention, a random sorting module is added between an input channel and a data source of an arbiter, a random number is generated by using the random sorting module, a one-to-one mapping is performed between the random number and the data source input to the random module, and the random number is moved by a sorting algorithm to obtain the priority of the output channel of the random sorting module, where the priority is a random priority, and the corresponding data source is output according to the priority.
After the priority ordering is performed on the multiple data sources through the random ordering module, the multiple data sources are input into the arbiter, and because all output channels in the current arbiter are mutually independent, an instruction that the arbiter simultaneously grants two or more output channels to output the same data source in the same clock cycle appears, and at the moment, a system returns two processed data to the same data source simultaneously, so that a system error can occur.
Example two
A second embodiment provides an arbitration system, including: m storage units, a random ordering module P and an arbiter A; the arbiter A comprises M preprocessing modules and M sub-arbiters, and the M sub-arbiters form an arbitration sequence A= { A according to the order of the arbitration priority from high to low 1 ,A 2 ,…,A i ,…,A M },A i For the ith sub-arbiter in A, the value range of i is 1 to M. Preferably, the sub-arbiter is a poll arbiter.
Further, the M storage units share multiple data sources. Optionally, the data source is a CPU, GPU, or other processor. Preferably, the data source is a CPU. Optionally, the sharing of the data source is implemented by sharing the data source via a bus. Optionally, the storage unit is a memory or a cache of the processor.
Further, the random ordering module P includes M input channels and M output channels q= { Q 1 ,Q 2 ,…,Q j ,…,Q M }, wherein Q j For the j-th output channel, each input channel is connected with a memory unit, Q j Through a preprocessing module Y i Connector arbiter A i Priority is higher than A i The outputs of the first i-1 sub-arbiters of (a) are respectively connected with Y i Forming a cascade structure; wherein the priority order of the output channel Q of P is equal to the arbitration priority order of the sub-arbiter in a. The random ordering module P is the same as the random ordering module in the first embodiment, and will not be described again.
Further, a preprocessing module Y i Acquiring priority higher than A according to cascade structure i The output result of the i-1 sub-arbiter is granted to the data source and is derived from Q j Excluding authorized data sources from the output results of (a) to obtain A i Is input to the computer. Y is Y i For giving priority to higher than A i The result of all sub-arbiters grant is processed, excluding the granted data source, in order to achieve the effect of mutual exclusion of the output results of all sub-arbiters in the arbiter a, i.e. the data source that has been granted by the sub-arbiter with high priority cannot be granted again by the sub-arbiter with low priority in order of priority, preventing data errors.
Specifically, realize the following Q j The output result of (2) has a relatively large number of circuits for excluding authorized data sources. Preferably, the preprocessing module Y i Comprising i-1 inverting inputs and a connection Q j I-1 reverse input ends and the forward input ends are respectively used as the input of the AND gate circuit, and the comprehensive output of the AND gate circuit is Y i Is provided.
Preferably, the preprocessing module Y i Comprising cascaded i-1 sub-processing units, each sub-processing unit comprising a sub-processor unit having a higher priority than A i A first input end connected with the output of the arbiter, a second input end connected with the output of the previous stage sub-processing unit, and an output end connected with the input of the next stage sub-processing unit; the data of the first input end and the data of the second input end are used as the input of an AND gate circuit after passing through an inverting circuit, and the output of the AND gate is the output end of the current sub-processing unit.
Further, the cascade of i-1 sub-processing units of the cascade is in the same order as the arbiter. I.e. highest priority arbiter cascade Y i First sub-processing unit of (a), high priority arbiter cascade Y i And so on. It should be noted that the cascade sequence is a data stream, i.e. Q j The output data is forwarded along the circuit through the first sub-processing unit and so on, after the last sub-processing unit the data flows into the sub-arbiter to which the current output channel is connected. Referring to FIG. 2, taking a 4 output channel as an example, the arbiter includes 4 sub-arbiters { A } with arbitration priorities ranging from high to low 1 ,A 2 ,A 3 ,A 4 Each output channel is connected with a sub-arbiter, and the input of each sub-arbiter is also connected with a preprocessing module, such as sub-arbiter A 4 Connected pretreatment module Y 4 ,Y 4 Including cascaded i-1 sub-processing units { Y } 4,1 ,Y 4,2 ,…,Y 4,k ,…,Y 4,4 },Y 4,k Is Y 4 The kth sub-processing unit of (a); wherein Y is 4,k And the kth arbiter A k Is connected with the output end of the power supply.
Preferably, the random sorting module P is configured to generate random numbers, where the number of bits of the random numbers is the same as the number of the second output channels, and each bit of random number corresponds to one second output channel in sequence; moving the random number according to the sorting algorithm, and correspondingly moving the arrangement sequence of the second output channels when the random number moves, wherein the sequence of the second output channels after movement is the priority sequence of random output of the data source; and outputting the corresponding data sources to the input channels of the arbiter according to the priority order of the random output for arbitration. The method for obtaining the output channel priority by the random ordering module P is the same as that of the random ordering module in the first embodiment, and will not be described again.
In summary, in the arbitration system provided in the second embodiment, the arbitration results of all the sub-arbiters with high priority are cascaded to the next sub-arbiter, the arbitration results are excluded from the results output by the output channels of the random ordering module, and the input of the next sub-arbiter is obtained, so that the authorized data sources cannot appear in the arbitration results of the next sub-arbiter, that is, the overall output result of the arbiter is achieved, and different output channels of the arbiter are authorized to different data sources. Meanwhile, the priority level randomly generated by the random sequencing module is combined, so that the aim of fair arbitration is fulfilled.
It should be noted that: the sequence of the embodiments of the present invention is only for description, and does not represent the advantages and disadvantages of the embodiments. And the foregoing description has been directed to specific embodiments of this specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (10)

1. An arbiter-based equalization arbitration method, the method comprising:
the random ordering module is used for generating a random number sequence, wherein the random ordering module is cascaded with first input channels of an arbiter with fixed priority, and comprises a plurality of second input channels and a plurality of second output channels, wherein the number of the second input channels is equal to the number of the second output channels; a plurality of second input channels of the random ordering module share a plurality of data sources;
the number of bits of the random numbers contained in the random number sequence is the same as the number of the second output channels, and each bit of random number sequentially corresponds to one second output channel; moving the random number according to the sorting algorithm, and correspondingly moving the arrangement sequence of the second output channels when the random number moves, wherein the sequence of the second output channels after movement is the priority sequence of random output of the data source; in the next adjacent period, the random number generator regenerates the random number, the random number and the arrangement sequence of the second output channels in the previous period are mapped one by one again, the random number and the arrangement sequence of the second output channels are exchanged according to the same ordering algorithm, and the priority sequence of the second output channels in each period is obtained by pushing the same; and outputting the corresponding data sources to the input channels of the fixed-priority arbiter according to the priority order of the random output for arbitration.
2. The method of arbiter-based equalization arbitration of claim 1, wherein the step of moving the random number according to the ranking algorithm comprises: dividing the random number sequence into a plurality of subgroups by taking two adjacent elements as a group, comparing the two elements in the subgroups, and exchanging the positions of the two elements when the exchanging conditions are met to obtain a first arrangement sequence of the random numbers; comparing adjacent elements between adjacent subgroups in the first arrangement sequence of the random numbers, and exchanging the positions of the two elements when the exchange condition is met to obtain a second arrangement sequence of the random numbers; comparing two elements in the small group in the second arrangement sequence of the random numbers, and exchanging the positions of the two elements when the exchange condition is met to obtain a third arrangement sequence of the random numbers; comparing adjacent elements between adjacent subgroups in the third arrangement sequence of the random numbers, and exchanging the positions of the two elements when the exchange condition is met to obtain a fourth arrangement sequence of the random numbers; the fourth permutation of the random numbers is a desired permutation of the random numbers.
3. The method of claim 2, wherein the switching condition is that the high random number is greater than the low random number.
4. The method of claim 2, wherein the switching condition is that the high random number is smaller than the low random number.
5. The method of claim 1, wherein the ranking algorithm is a bubbling ranking algorithm, a selection ranking algorithm, or an insertion ranking algorithm.
6. The method of claim 1, wherein the priority order is in ascending or descending order.
7. The arbiter-based equalization arbitration method of claim 1, wherein a plurality of data sources shared by a plurality of second input channels of the random ordering module are grouped; after the data sources are grouped, inputting each group of data sources into a corresponding second input channel, and acquiring the priority of each group of data sources by a sequencing module, and sending each group of data sources into a corresponding arbiter for arbitration according to the priority order; the number of packets of the data source is equal to the number of second input channels.
8. The method of claim 7, wherein the packets of the data source are grouped according to a predetermined data size.
9. The method of claim 1, wherein the data sources are cyclically allocated to the corresponding second input channels in the order of the data sources.
10. The method of claim 1, wherein the data source is a CPU or GPU data or request.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6240075B1 (en) * 1999-01-25 2001-05-29 Trw Inc. Satellite communication routing arbitration techniques
US6718422B1 (en) * 1999-07-29 2004-04-06 International Business Machines Corporation Enhanced bus arbiter utilizing variable priority and fairness
US7073005B1 (en) * 2002-01-17 2006-07-04 Juniper Networks, Inc. Multiple concurrent dequeue arbiters
CN100550832C (en) * 2005-11-15 2009-10-14 华为技术有限公司 A kind of arbitration implementation method of switching network
US7752369B2 (en) * 2008-05-09 2010-07-06 International Business Machines Corporation Bounded starvation checking of an arbiter using formal verification
CN101667164A (en) * 2009-09-18 2010-03-10 黄以华 On-chip bus arbiter and processing method thereof
US8370553B2 (en) * 2010-10-18 2013-02-05 International Business Machines Corporation Formal verification of random priority-based arbiters using property strengthening and underapproximations
CN105022717B (en) * 2015-06-04 2018-11-27 中国航空无线电电子研究所 The network-on-chip arbitration method and arbitration unit of additional request number priority
CN111666139B (en) * 2020-05-26 2022-11-11 中国人民解放军国防科技大学 Scheduling method and device for MIMO multi-service-class data queue
CN113971144B (en) * 2021-10-27 2024-04-16 合肥学院 Dynamic mixed lottery method for multiprocessor priority arbitration
CN114564424B (en) * 2022-03-10 2023-04-25 上海壁仞智能科技有限公司 Arbiter and electronic device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
多优先级通用路由仲裁器的设计实现;周刚华,邹德财,卢晓春;《小型微型计算机系统》;593-597 *
随机争用仲裁器;杨晶鑫,张文龙;《计算机工程》;161-162、220 *

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