CN1155785A

CN1155785A - Flip-flop circuit

Info

Publication number: CN1155785A
Application number: CN 96112083
Authority: CN
Inventors: G·隆布雷施基; M·加利纳里; M·莫雷利
Original assignee: Magneti Marelli SpA; SGS Thomson Microelectronics SRL
Current assignee: STMicroelectronics SRL; Marelli Europe SpA
Priority date: 1995-11-07
Filing date: 1996-11-06
Publication date: 1997-07-30

Abstract

A flip-flop circuit able to commute in correspondence with any logic transition of the input signal using a flip-flop and a logic gate of the EXNOR type receiving at its input a signal and the inverted output of the flip-flop. To the output of the EXNOR gate is connected a set-reset flip-flop which allows a reset to be effected after each commutation of the circuit in order to prepare it for the next transition.

Description

Flip-flop circuit

Present invention relates in general to trigger the logical circuit of type.More particularly the present invention relates to change the structure of the flip-flop circuit of changing,, all need to reset after each conversion in order to make arrangements in advance to change next time according to any logic of input signal.

The present invention can be advantageously used in a kind of like this monolithic integrated circuit, in this integrated circuit, exist any logic of one or several signal to change the problem that (from 0 to 1 and from 1 to 0) all provides a pulse afterwards, this application need all resets after each conversion, and utilizes the Minimum Area on the integrated circuit.

Preferred circuit with this function is unknown in the present technique field, therefore in order to obtain desired result, generally adopts two D type FFD triggers (Fig. 1) that have reset terminal, and wherein each D type FFD trigger is made of 24 transistors.The logical circuit of this structure is illustrated in Fig. 1, and the circuit diagram of FFE trigger is shown in Fig. 2 simultaneously.

As shown in the figure, input signal IN (conversion of this signal is to need to detect) is added to the input end of clock CP of two D type FFD triggers.Input signal IN is anti-phase by a logic inverter INV, is added on one of them FFD trigger.The data input pin D of two FFD triggers links to each other with high logic value (supply voltage V+).Two output Q of FFD trigger with or relation link to each other so that the output signal OUT of circuit is provided.This circuit further provides a reseting input signal RST, and it is in parallel with two the RESET input CD of FFD trigger, and its mode is for making the output OUT of output Q and circuit reset after detecting input signal IN variation.

D type FFD trigger (with reference to Fig. 2) is to the rising edge sensitivity of the input signal of terminal CP, utilizing needs to detect the signal IN of its conversion as the clock signal on the terminal CP of a FFD trigger, and identical signal IN is added on the 2nd FFD trigger after anti-phase, and the output terminals A by two FFD triggers is with B's or be connected and can detect its each logic and change.

Specifically,, and need to produce a pulse that detects any conversion of signals, need so the number of used FFD trigger be multiply by 2n if the number of switching signal equals n.This can see from Fig. 3.It should be noted, detect n input signal IN1, IN2---INn if desired, need 2n FFD trigger so.

The custom circuit (Fig. 1) that has described function under the situation of individual signals is made of 54 transistors.The waveform of each signal as shown in Figure 4, simultaneously truth table is as follows:

????RST	???IN	???OUT
????RST	???IN	???OUT	????L	????X	????L
????H	??L-＞H	????H	????L	????X	????L
????H	??L-＞H	????H	????H	??H-＞L	????H

Wherein very naturally, L represents low logic level or 0, and H represents high logic level or 1, and the X representative is unimportant.

Preparing the state of conversion next time in order to export OUT set, the output OUT that is in high logic level after described input signal IN changes must turn back to low logic level by the reset signal RST that the outside provides, otherwise, will ignore conversion next time because output OUT does not change its state.

Therefore, although the circuit structure of prior art has solved the problem that realizes described function, still have technical problem.In fact these circuit structures need use a large amount of transistors, thereby need the surface area of a large amount of integrated circuits, so reduced integrated level, have increased cost.

The purpose of this invention is to provide a kind of flip-flop circuit, it has solved above-mentioned all problems satisfactorily.

This purpose of the present invention is to change and the triggering type logical circuit of converted output signal realizes that this circuit is characterised in that and comprises by a kind of so any logic according to an input signal:

-have a trigger of the data input pin that receives described signal,

Realize that next XOR type logic function is the combinational circuit of inverted logic function for-one, have the first input end and second input that links to each other with the inverting input of described trigger that receive described signal, and

The trigger of-one set-restoration type has the RESET input that links to each other with the output of described combinational circuit.

By the detailed description of non-restrictive example being done below in conjunction with accompanying drawing, further advantage of the present invention and feature will become very clear, in the accompanying drawing:

Fig. 1,2,3 and 4 is prior aries, and has been described;

Fig. 5 is the circuit diagram of the possible embodiment of device of the present invention;

Fig. 6 is one group of Descartes's time diagram of the operation of explanation device of the present invention;

Fig. 7 is similar to Fig. 5, represents an embodiment with device of two inputs of the present invention;

Fig. 8 is similar to Fig. 6, is one group of Descartes's time diagram of the circuit operation of key diagram 7;

Fig. 9 represents an embodiment of the device of the n of having an of the present invention input; And

Figure 10 represents another embodiment with device of 3 inputs of the present invention.

A possible embodiment of flip-flop circuit of the present invention for example as shown in Figure 5.As can be seen from the figure, this circuit is quite simple, by five logical AND not gate N1, N2, N3, N4, N5, and an XNOR gate E, the trigger FFRS of logic inverter INV and set-restoration type forms.

Can see that four NAND gate N1, N2, N3, N4 and not gate INV constitute a trigger.This trigger N1, N2, N3, N4 and INV receive the signal IN that wants to detect its variation at its data input pin.In addition, signal IN is applied to biconditional gate E.The output of biconditional gate E links to each other with the set input of set-restoration type trigger FFRS, so that after the variation that detects signal IN, makes the output OUT of circuit be set.Second input of biconditional gate E links to each other with the reversed-phase output of representing with I7 of trigger N1, N2, N3, N4 and INV, so that the variation of other type that can detection signal IN.The RESET input of trigger FFRS links to each other with the input RST that resets of circuit, so that after the variation that detects signal IN, makes the output OUT of circuit be reset.In addition, the output of representing with I22 of biconditional gate E links to each other with the input of another NAND gate N5, and the output of this NAND gate links to each other with the permission input of trigger N1, N2, N3, N4 and INV.The other input of another NAND gate N5 links to each other with an input PW-ON, and this input applies the signal of the power supply existence of indication circuit.

The operation principle of circuit is as follows.At first initialization (or resetting) (signal RST=1 and signal PW-ON=0), the output OUT of FFRS trigger is in logic level 0, node I7 (reversed-phase output of trigger N1, N2, N3, N4 and INV) is in the complementary logic level with respect to input signal IN simultaneously, the conversion of this input signal IN is (if the IN=0 that needs detection, I7=1 then, if IN=1, then I7=0).In addition, node I22 (output of gate E) is in logic level 0.

When the circuit energized (corresponding to resetting), signal PW-ON stably is in logic level 1.Input RST becomes 0 when being in first logical transition of signal IN, XNOR gate E has two signals that logic level is identical at its input, therefore node I22 changes to logic level 1 from logic level 0, the output OUT fetch logic level 1 of trigger FFRS, this trigger is made of two logic OR not gate (not shown).

At this moment, take to node I7 with respect to signal IN through the signal on the node I22 of logic gate delay and be complementary logic level, make the conversion next time of circuit ready-to-receive signal IN.Therefore, node I22 provides the pulse as the result of any variation of input signal IN level, and the duration of its pulse is by determining the time of delay of gate.

In order to obtain duration and the corresponding to output signal of each conversion, trigger FFRS is driven by signal RST.When this signal RST when logic level 0 changes to logic level 1, because the signal on the output OUT of the conversion fetch logic level 1 of signal IN turns back to logic level 0.Next trigger FFRS prepares the new variation of receiving inputted signal IN.

The oscillogram of the various signals that obtain is shown in Fig. 6.Circuit among the embodiment that had just described is made of 40 transistors.

This viewpoint of area from the integrated circuit that uses, big more with the number that produces the corresponding to signal of the necessary variation of pulse, the present invention is just favourable more, in fact, do not need to duplicate entire circuit, and only need duplicate the part of representing with RIL in the frame of broken lines that is included in Fig. 5.Referring to Fig. 7, the figure shows a embodiment with two input signal IN1 and IN2.

Under the situation that two signal IN1 and IN2 are arranged, they can be changed or conversion separately together, the output of biconditional gate with or relation be connected with each other, so any conversion of one or two input all produces a pulse, it makes the output of trigger FFRS get 1, thereby the output OUT of circuit gets 1.Therefore, needn't under the situation of two inputs, duplicate total as above-mentioned prior art.

Relevant with Fig. 7 circuit waveform is shown in Fig. 8.Can see also that from this figure the voltage on the node I143 (it makes the output of trigger FFRS get 1) is a pulse, it produces when each conversion of one or two input IN1 and IN2, exports the state of OUT simultaneously and is determined by signal RST.

With reference to Fig. 7, if use De Morgan rule, as actual represented,, replace biconditional gate so with XOR gate X by replacing or door with NAND gate N6, just can optimize the number of gate.

Fig. 9 represents an embodiment of the similar circuit of circuit of of the present invention and Fig. 7, and input signal IN1, IN2---INn are wherein arranged, and their variation is to need to detect.

Figure 10 represents another embodiment with circuit of three input IN0, IN1 and IN2 of the present invention.From this figure, can see how utilizing signal RST after conversion, to make the output OUT of circuit be 0 and three trigger N1, N2, N3, N4 and INV are resetted.

The truth table of the circuit with single input signal IN shown in Figure 5 is as follows:

???RST	???IN	???OUT
???RST	???IN	???OUT	????L	????X	????L
????H	??L-＞H	????H	????L	????X	????L
????H	??L-＞H	????H	????H	??H-＞L	????H

The advantage of circuit of the present invention is to adopt a kind of like this circuit, and this circuit realization has the function of a pair of reset flip-flop of minimum area.

From the circuit diagram of Fig. 3 and 9 as can be seen, the number of the signal of required its conversion of detection is many more, and advantage is many more.Following table is the comparison of doing with regard to used transistor between according to prior art constructions and the scheme with 1,2 and 3 input of the present invention:

Prior art	The present invention
Prior art	The present invention	Transistorized number	Transistorized number
????????56	????????36	Transistorized number	Transistorized number
????????56	????????36	???????174	????????98
???????290	???????158	???????174	????????98

5 inputs of 3 inputs of 1 input

Obviously, keeping under the constant situation of invention principle, do not depart from the scope of the present invention, the details of structure and embodiment can revise on the basis that has illustrated widely, for example under situation shown in Figure 10, after input conversion, utilize input signal RST to make to be output as 0 and " renewal " trigger N1, N2, N3, N4 and INV.

Claims

1. any logic according to an input signal (IN) changes and the triggering type logical circuit of converted output signal (OUT) is characterized in that comprising:

-have a trigger (N1, N2, N3, N4 and INV) of the data input pin that receives described signal (IN),

Realize that next XOR type logic function is the combinational circuit (E) of inverted logic function for-one, have second input that the first input end that receives described signal (IN) links to each other with inverting input with described trigger (N1, N2, N3, N4 and INV), and

The trigger of-one set-restoration type (FFRS) has the RESET input that links to each other with the output of described combinational circuit (E).

2. according to the logical circuit of claim 1, it is characterized in that described combinational circuit comprises an XNOR type gate (E).

3. according to the logical circuit of claim 1, according to a plurality of input signals (IN1, IN2,---, INn) any logic change and converted output signal (OUT) is characterized in that comprising:

-a plurality of triggers (N1, N2, N3, N4 and INV), each its input receive described a plurality of input signal (IN1, IN2,---, INn) in one,

-one realize XOR type logic function next be the inverted logic function combinational circuit (X N6), has manyly to input, and described many each to input are to having:

-receive described a plurality of signals (IN1, IN2,---, INn) in one first input end,

-second input that links to each other with the reversed-phase output of corresponding trigger (N1, N2, N3, N4 and INV),

An output that links to each other with the described set input of described set-reset flip-flop (FFSR).

4. according to the logical circuit of claim 3, it is characterized in that described combinational circuit comprises a plurality of XNOR gates, each has:

And a logic sum gate, receive the output of described a plurality of XNOR gates at its input, and have an output that links to each other with the described set input of described set-reset flip-flop (FFSR).

5. according to the logical circuit of claim 3, it is characterized in that described combinational circuit comprises a plurality of exclusive or logic gates (X), each has:

And the gate (N6) with non-type, receive the output of described a plurality of XOR gate at its input, and have an output that links to each other with the described set input of described set-reset flip-flop (FFSR).

6. according to any one logical circuit of claim 1 to 5, it is characterized in that it comprises a feedback circuit (N5), it is with described combinational circuit (E; X, N6) output links to each other with the permission input of described trigger (N1, N2, N3, N4 and INV), its purpose is after once changing, and makes described trigger (N1, N2, N3, N4 and INV) ready to the new variation of described input signal (IN).

7. according to the logical circuit of claim 6, it is characterized in that described feedback circuit comprises the gate (N5) that realizes the inverted logic function, its input and described combinational circuit (E; X, output N6) links to each other, and its output links to each other with the described permission input of described trigger (N1, N2, N3, N4 and INV).

8. according to the logical circuit of claim 7, it is characterized in that having described gate (N5) right and wrong type and described combinational circuit (E; X, first input end that output N6) links to each other and reception expression are used for the described logical circuit of initialization when energising to second input of the signal (PW-ON) of described power logic circuitry.

9. according to any one logical circuit of claim 1 to 8, it is characterized in that it comprises the RESET input (RST) that links to each other with the input of described set-reset flip-flop (FFRS), so that allow the state of described set-reset flip-flop (FFRS) after conversion, to reset.

10. according to any one logical circuit of claim 1 to 9, it is characterized in that described trigger (N1, N2, N3, N4 and INV) produces the signal of the input that constitutes restoration type or D flip-flop.