CN115576609A - RISC-V based IoT (Internet of things) Internet of things hardware architecture system - Google Patents
RISC-V based IoT (Internet of things) Internet of things hardware architecture system Download PDFInfo
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Abstract
The invention discloses an IoT (Internet of things) hardware architecture system based on RISC-V (reduced instruction set computer-graphics), which is characterized in that a processor designed based on an RISC-V instruction set is more suitable for an embedded IOT (input/output) module, and the problem of compatibility is avoided when the instruction set of the RISC-V processor is added, so a large number of circuits can be saved in the processing design, meanwhile, the coupling problem of an internal communication module of the IOT equipment is unified by adding an external communication protocol module, different communication protocol modules can be better compatible, different communication protocols can be better added or deleted according to a service scene, and the later research, development and maintenance cost is greatly reduced.
Description
Technical Field
The invention relates to the technical field of internet of things, in particular to an IoT internet of things hardware architecture system based on RISC-V.
Background
RISC-V (pronounced "risk-five") is an open source Instruction Set Architecture (ISA) based on the Reduced Instruction Set (RISC) principle. Compared to most instruction sets, the RISC-V instruction set is free to be used for any purpose, allowing anyone to design, manufacture, and sell RISC-V chips and software without the need to purchase expensive architectural licenses like ARM.
RISC-V is a modular architecture, where different parts can be chained together in a modular fashion, in an attempt to meet a variety of different applications through a unified set of architectures. Because the IoT scenario is very extensive and fragmented, requiring the chip to be designed for thousands of application cases that connect the world in many different ways, the scalable architecture becomes a key to terminal operations. Compared with different series of incompatible ARM, RISC-V has the advantage of being capable of flexibly expanding an instruction set, can add a special instruction, can expand operation resources required by an edge operation device, can realize complex AI calculation with ultra-low power consumption, and is beneficial to promoting architecture innovation to achieve higher energy efficiency. The RISC-V instruction set architecture has the advantages of low power consumption, low cost, open source, modularization, simplicity, small area, high speed and the like, and is very fit with the fragmentization and customizability characteristics of IoT scene requirements.
Disclosure of Invention
The invention provides an IOT hardware architecture system based on RISC-V, which solves the problems of low power consumption, compatibility with different communication protocols and low cost of IOT equipment, and simultaneously solves the problem of difficult programming expansion of the traditional MCU by applying a processor designed based on the RISC-V instruction set to the IOT equipment end because the RISC-V instruction set has independent expansibility and good compatibility.
The invention achieves the above purpose through the following technical scheme:
an IoT Internet of things hardware architecture system based on RISC-V comprises an instruction set processor based on RISC-V, a unified communication protocol interface module and different communication protocol modules;
the processor based on the RISC-V instruction set is used for processing and executing the instruction compiled from the high-level language, and realizes the communication and control of different communication protocol modules by calling a unified communication protocol interface;
the processor based on the RISC-V instruction set is connected with the communication protocol interface module and is used for realizing the control coordination of different communication protocol modules, and simultaneously calculating and processing the data returned by the communication protocol modules to realize the application under different scenes.
Further, the processor based on RISC-V instruction set comprises: the system comprises an instruction fetching module, an execution module, an access storage module, a data storage module and an external communication protocol module.
The execution module comprises an instruction delivery module, a budget unit and an instruction writing module, and is responsible for acquiring and executing the instructions and writing related subsequent instructions;
the execution module is connected with the instruction fetching module, the instruction fetching module is connected with the access storage module, the access storage module is respectively connected with the data storage module and the peripheral communication protocol module, the peripheral communication protocol module is connected with the communication protocol interface module, and the communication protocol interface module is connected with different communication modules.
The instruction fetching module is used for partially decoding the instruction and then delivering the instruction to the execution module;
the execution module is used for decoding the instruction from the instruction fetching module, dispatching the instruction to different operation units for execution and writing back the operation result to the register;
the arithmetic unit is used for being responsible for specific instruction execution and arithmetic and sending a result to a specified unit.
The access storage module is used for arbitrating the instructions to be accessed and stored and determining a memory and a peripheral accessed by the instructions;
the data storage module is used for storing data information which needs to be accessed and stored by the instruction.
The peripheral communication protocol module communicates with different external wireless transmission modules in a unified way through a communication protocol interface module;
the peripheral communication module is used for communicating with different communication modules (wifi, bluetooth and Zigbee).
The further scheme is that the different communication modules comprise a wifi module, a bluetooth module, a Zigbee module and the like, and if new hardware communication protocol modules are added in the follow-up process, the management is added at the same place.
The invention has the beneficial effects that:
the processor designed based on the RISC-V instruction set has low power consumption and small area, is more suitable for the embedded IOT module, and avoids the problem of compatibility when the instruction set of the RISC-V processor is arranged, thereby saving a large number of circuits in the processing design and greatly reducing the power consumption and the area. Meanwhile, the coupling problem of the internal communication module of the IOT equipment is unified by adding the external communication protocol module, different communication protocol modules can be better compatible, different communication protocols can be better increased or deleted according to a service scene, and the later research and development maintenance cost is greatly reduced.
In the field of IOT modules, compared with a traditional ARM instruction set MCU, the IOT module can be better modularized under the condition of low power consumption.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the embodiments or the drawings needed to be practical in the prior art description, and obviously, the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a block diagram of the present invention.
Fig. 2 is a detailed view of the inventive frame.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without any inventive step, are within the scope of the present invention.
In any embodiment, as shown in fig. 1, an IoT internet of things hardware architecture system based on RISC-V of the present invention includes: the system comprises an instruction set processor based on RISC-V, a unified communication protocol interface module and different communication protocol modules;
the processor based on the RISC-V instruction set is used for processing and executing the instruction compiled from the high-level language, and realizes the communication and control of different communication protocol modules through the calling of a unified communication protocol interface;
the processor based on the RISC-V instruction set is connected with the communication protocol interface module and used for realizing the control coordination of different communication protocol modules, and simultaneously calculating and processing the data returned by the communication protocol modules, thereby realizing the application under different scenes.
In one embodiment, as shown in fig. 1-2, an IoT internet of things hardware architecture system based on RISC-V of the present invention includes an instruction set processor based on RISC-V, a unified communication protocol interface module, and different communication protocol modules;
the processor based on the RISC-V instruction set is used for processing and executing the instruction compiled from the high-level language, and realizes the communication and control of different communication protocol modules by calling a unified communication protocol interface;
the processor based on the RISC-V instruction set is connected with the communication protocol interface module and is used for realizing the control coordination of different communication protocol modules, and simultaneously calculating and processing the data returned by the communication protocol modules, thereby realizing the application under different scenes.
The RISC-V instruction set based processor comprises: the system comprises an instruction fetching module, an execution module, an access storage module, a data storage module and an external communication protocol module. The execution module comprises an instruction delivery module, a budget unit and an instruction writing module, and is responsible for acquiring and executing the instruction and writing related subsequent instructions; the execution module is connected with the instruction fetching module, the instruction fetching module is connected with the access storage module, the access storage module is respectively connected with the data storage module and the peripheral communication protocol module, the peripheral communication protocol module is connected with the communication protocol interface module, and the communication protocol interface module is connected with different communication modules.
The instruction fetching module is used for partially decoding the instruction and then delivering the instruction to the execution module;
the execution module is used for decoding the instruction from the instruction fetching module, dispatching the instruction to different operation units for execution and writing back the operation result to the register; the arithmetic unit is used for taking charge of specific instruction execution and arithmetic and sending the result to the appointed unit. The data storage module is used for storing data information required to be accessed and stored by the instruction.
The access storage module is used for arbitrating the instructions to be accessed and stored and determining a memory and a peripheral accessed by the instructions; the access storage module is responsible for reading or writing input from the internal data storage module, reading an instruction to be executed, reading the data storage module through the access storage module to obtain the instruction, delivering the instruction to the instruction-taking module, transmitting the instruction to the execution module, and delivering the instruction to the operation unit module through the instruction delivery module to perform specific execution.
The peripheral communication protocol module communicates with different external wireless transmission modules in a unified way through the communication protocol interface module; the peripheral communication module is used for communicating with different communication modules (wifi, bluetooth and Zigbee). The peripheral communication protocol module is responsible for writing in of external input, and when data are acquired through the communication protocol interface, the peripheral communication protocol module is responsible for analyzing the data, delivering the data to the access storage module, and transmitting the data to the data storage module for storage through the access storage module.
The different protocol obtaining modules carry out data transmission through the unified communication protocol interface, meanwhile, the different communication protocol modules can be added or deleted at any time according to the service requirements, and only the internal self-defined communication protocol interface needs to be connected when the communication module is newly added, and the corresponding interface is realized. The different communication modules comprise a wifi module, a Bluetooth module, a Zigbee module and the like, and if new hardware communication protocol modules are added in the follow-up process, the modules are managed and added at the same place.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims. It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition. In addition, any combination of the various embodiments of the present invention can be made, and the same should be considered as the disclosure of the present invention as long as the idea of the present invention is not violated.
Claims (7)
1. An RISC-V based IoT (Internet of things) hardware architecture system is characterized by comprising an instruction set processor based on RISC-V, a unified communication protocol interface module and different communication protocol modules;
the processor based on the RISC-V instruction set is used for processing and executing the instruction compiled from the high-level language, and realizes the communication and control of different communication protocol modules through the calling of a unified communication protocol interface;
the processor based on the RISC-V instruction set is connected with the communication protocol interface module and used for realizing the control coordination of different communication protocol modules, and simultaneously calculating and processing the data returned by the communication protocol modules, thereby realizing the application under different scenes.
2. The RISC-V based IoT Internet of things hardware architecture system of claim 1,
the RISC-V instruction set based processor comprises: the system comprises an instruction fetching module, an execution module, an access storage module, a data storage module and an external communication protocol module.
3. The RISC-V based IoT Internet of things hardware architecture system of claim 2, wherein the execution module comprises three parts, namely an instruction delivery module, a budget unit and an instruction writing module, which are responsible for instruction acquisition, execution and writing of related subsequent instructions;
the execution module is connected with the instruction fetching module, the instruction fetching module is connected with the access storage module, the access storage module is respectively connected with the data storage module and the peripheral communication protocol module, the peripheral communication protocol module is connected with the communication protocol interface module, and the communication protocol interface module is connected with different communication modules.
4. The RISC-V based IoT Internet of things hardware architecture system of claim 3, wherein the instruction fetch module is configured to partially decode the instruction and deliver it to the execution module;
the execution module is used for decoding the instruction from the instruction fetching module, dispatching the instruction to different operation units for execution and writing back the operation result to the register;
the arithmetic unit is used for taking charge of specific instruction execution and arithmetic and sending the result to the appointed unit.
5. The RISC-V based IoT Internet of things hardware architecture system of claim 2, wherein the access memory module is configured to arbitrate the instructions to be accessed, and to determine the memory and peripheral devices to which the instructions are accessed;
the data storage module is used for storing data information required to be accessed and stored by the instruction.
6. The RISC-V based IoT Internet of things hardware architecture system of claim 2, wherein the peripheral communication protocol modules communicate uniformly to external diverse wireless transport modules through communication protocol interface modules;
the peripheral communication module is used for communicating with different communication modules.
7. The RISC-V based IoT internet of things hardware architecture system recited in claim 1, wherein the different communication modules comprise wifi module, bluetooth module, zigbee module.
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