CN115567701A - Detection method of high-bandwidth 3 video processing circuit of suspension management system - Google Patents
Detection method of high-bandwidth 3 video processing circuit of suspension management system Download PDFInfo
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- CN115567701A CN115567701A CN202211064695.0A CN202211064695A CN115567701A CN 115567701 A CN115567701 A CN 115567701A CN 202211064695 A CN202211064695 A CN 202211064695A CN 115567701 A CN115567701 A CN 115567701A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The invention discloses a detection method of a high-bandwidth 3 video processing circuit of a pendant management system, which is characterized in that a DA chip is used for simulating an input signal, an SPI interface is used for controlling a switching signal of a multi-channel video cross-point switch chip to a test output end, and an AD chip is used for testing the output signal so as to detect whether the high-bandwidth 3 video processing circuit is abnormal or not. The method can realize the detection of the high-bandwidth 3 video processing circuit of the pendant management system, thereby improving the reliability of the pendant management system.
Description
Technical Field
The invention belongs to the technical field of airplane hangar management, and particularly relates to a detection method of a high-bandwidth 3 video processing circuit.
Background
The high-bandwidth 3 is one of the electrical interfaces of the aircraft hangings, the corresponding characteristic impedance is 75 ohms, the high-bandwidth 3 is used for transmitting signals to be monochrome grating composite video signals, and the high-bandwidth 3 video signals of each hanging point of the aircraft are transmitted to the aircraft cockpit display for displaying after being switched by the hangings management system.
The high-bandwidth 3 video processing circuit is usually composed of a multi-channel video cross-point switch chip, and is used for realizing the switching operation from multi-video input to multi-video output. The multi-channel video cross-point switch chip is a non-blocking multi-channel video cross-point switch with buffer input and output, and the input and output impedance is 75 ohms. The chip can be controlled through the SPI interface, and the switching function from any input channel to any output channel can be realized.
Problems such as SPI interface communication failure, power supply abnormity, chip faults and the like can occur in the using process of the high-bandwidth 3 video processing circuit, and the function of the suspended object management system is directly influenced.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a detection method of a high-bandwidth 3 video processing circuit of a suspension management system, wherein a DA chip is used for simulating an input signal, an SPI interface is used for controlling a switching signal of a multi-channel video cross-point switch chip to a test output end, and an AD chip is used for testing the output signal so as to detect whether the high-bandwidth 3 video processing circuit is abnormal. The method can realize the detection of the high-bandwidth 3 video processing circuit of the pendant management system, thereby improving the reliability of the pendant management system.
The technical scheme adopted by the invention for solving the technical problem comprises the following steps:
step 1: the high-bandwidth 3 video processing circuit comprises an FPGA, a DA chip, an AD chip, a multi-channel video cross-point switch chip and a bus transceiver;
step 2: the test port selects an IN port and an OUT port which are not used by a multi-channel video cross-point switch chip;
and step 3: the power-on system enters a test mode, and the FPGA controls the DA chip to simulate and generate a signal with the voltage of 1V;
and 4, step 4: the FPGA controls the IN port to be switched to the OUT port through the SPI;
and 5: the FPGA controls the AD chip, the voltage of an OUT port of the multichannel video cross-point switch chip is tested, when the OUT port does not detect 1V voltage, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through a bus; when the voltage of 1V is detected, the detection flow enters the next step;
step 6: the FPGA controls the IN port to be switched off from the OUT port through the SPI interface;
and 7: the FPGA controls the AD chip to test the voltage of an OUT port of the multi-channel video cross-point switch chip, and when the OUT port does not detect 1V voltage, the detection flow enters the next step; when the voltage of 1V is detected, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through a bus;
and step 8: with a 1 V is the step length, the analog generated voltage value of the DA chip is sequentially reduced, when the signal voltage is adjusted once, the FPGA controls the multichannel video cross point switch chip and the AD to complete the on-off test and the off-off test once, before the voltage is reduced to 0V, if the test signal voltage is normal, the high-bandwidth 3 video switching circuit works normally, the circuit test is completed, and the FPGA reports the test passing information through a bus;
and step 9: after the test is finished, the FPGA enters a normal working mode, and the input port video is adjusted to the corresponding output port according to the system requirement.
Further, the multi-channel video crosspoint switch chip is MAX9675ECQ +.
Further, said a 1 ＝0.1。
The invention has the following beneficial effects:
the method can realize the detection of the high-bandwidth 3 video processing circuit of the pendant management system, thereby improving the reliability of the pendant management system.
Drawings
Fig. 1 is a block diagram of a high bandwidth 3 video processing detection circuit according to the present invention.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the drawings.
The invention provides a detection method of a high-bandwidth 3 video processing circuit of a suspension management system, which comprises the steps of simulating an input signal through a DA (digital-analog) chip, controlling a switching signal of a multi-channel video cross-point switch chip to a test output end through an SPI (serial peripheral interface), and testing the output signal through an AD (analog-digital) chip to detect whether the high-bandwidth 3 video processing circuit is abnormal or not.
A detection method for a high-bandwidth 3 video processing circuit of a suspension management system comprises the following steps:
step 1: the high-bandwidth 3 video processing circuit comprises an FPGA, a DA chip, an AD chip, a multi-channel video cross-point switch chip and a bus transceiver;
step 2: the test port selects an IN port and an OUT port which are not used by a multi-channel video cross-point switch chip;
and step 3: the power-on system enters a test mode, and the FPGA controls the DA chip to simulate and generate a signal with the voltage of 1V;
and 4, step 4: the FPGA controls the IN port to be switched to the OUT port through the SPI;
and 5: the FPGA controls the AD chip, the voltage of an OUT port of the multichannel video cross-point switch chip is tested, when the OUT port does not detect 1V voltage, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through a bus; when the voltage of 1V is detected, the detection flow enters the next step;
step 6: the FPGA controls the IN port to be switched off from the OUT port through the SPI interface;
and 7: the FPGA controls the AD chip to test the voltage of an OUT port of the multi-channel video cross-point switch chip, and when the OUT port does not detect 1V voltage, the detection flow enters the next step; when the voltage of 1V is detected, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through a bus;
and 8: with a 1 V is the step length, the analog generated voltage value of the DA chip is reduced in sequence, when the signal voltage is adjusted once, the FPGA controls the multi-channel video cross point switch chip and the AD to complete the on-off test and the off-off test once, before the voltage is reduced to 0V, if the test signal voltage is normal, the high-bandwidth 3 video switching circuit works normally, the circuit test is completed, and the FPGA reports the test passing information through the bus;
and step 9: after the test is finished, the FPGA enters a normal working mode, and the input port video is adjusted to the corresponding output port according to the system requirement.
The specific embodiment is as follows:
the embodiment comprises the following steps: a high bandwidth 3 video control management unit for realizing the switching control of the high bandwidth 3 video; a high bandwidth 3 detection unit capable of generating test stimuli while monitoring the output signal.
Fig. 1 is a detection schematic block diagram of a high-bandwidth 3 video processing circuit, where an FPGA controls a DA chip, the high-bandwidth 3 processing circuit, and an AD chip to detect the high-bandwidth 3 video processing circuit, and the specific detection flow is as follows:
as shown IN fig. 1, the present invention takes a 4-channel video input to 2-channel video output circuit as an example, the selected multi-channel video crosspoint switch chip is MAX9675ECQ +, MAX9675ECQ + is a 16#16 video crosspoint switch, and supports 16-channel video input to 16-channel video output, the high bandwidth 3 video processing circuit of the present invention uses 4-channel input plus 2-channel output, and the test port selects the unused IN5 and OUT3 ports.
And the power-on system enters a test mode, and the FPGA controls the DA chip to simulate and generate a signal with the voltage of 1V.
The FPGA controls the IN5 interface to be switched to the OUT3 interface through the SPI.
The FPGA controls the AD chip to test the voltage of the OUT3 output end of the MAX9675ECQ +, when the OUT3 does not detect 1V voltage, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through the bus. When the voltage of 1V is detected, the detection flow proceeds to the next step.
The FPGA controls the connection and disconnection of the interfaces IN5 to OUT3 through the SPI interface.
The FPGA controls the AD chip to test the voltage of the OUT3 output end of the MAX9675ECQ +, and when the OUT3 does not detect the voltage of 1V, the detection flow enters the next step. When the voltage of 1V is detected, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through the bus.
And the FPGA controls the DA to adjust the voltage value of the generated signal to be 0.9V, and the operation is repeated to test whether the signal can be normally switched on or not.
And sequentially reducing the signal voltage value output by the DA chip by taking 0.1V as a step length, controlling the MAX9675ECQ + and the AD chip by the FPGA to complete a cut-on test and a cut-off test every time the signal voltage is adjusted, wherein before the voltage is reduced to 0V, if the test signal voltage is normal, the high-bandwidth 3 video switching circuit works normally, the circuit test is completed, and the FPGA reports test passing information through a bus.
After the test is finished, the FPGA enters a normal working mode, and the input interface video is adjusted to the corresponding output interface according to the system requirement.
Claims (3)
1. A detection method for a high-bandwidth 3 video processing circuit of a suspension management system is characterized by comprising the following steps:
step 1: the high-bandwidth 3 video processing circuit comprises an FPGA, a DA chip, an AD chip, a multi-channel video cross-point switch chip and a bus transceiver;
step 2: the test port selects an IN port and an OUT port which are not used by a multi-channel video cross-point switch chip;
and step 3: the power-on system enters a test mode, and the FPGA controls the DA chip to simulate and generate a signal with the voltage of 1V;
and 4, step 4: the FPGA controls the IN port to be switched to the OUT port through the SPI;
and 5: the FPGA controls the AD chip, the voltage of an OUT port of the multichannel video cross-point switch chip is tested, when the OUT port does not detect 1V voltage, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through a bus; when the voltage of 1V is detected, the detection flow enters the next step;
step 6: the FPGA controls the IN port to be switched off from the OUT port through the SPI interface;
and 7: the FPGA controls the AD chip to test the voltage of an OUT port of the multi-channel video cross-point switch chip, and when the OUT port does not detect 1V voltage, the detection flow enters the next step; when the voltage of 1V is detected, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports fault information through a bus;
and 8: with a 1 V is the step length, the analog generated voltage value of the DA chip is reduced in sequence, when the signal voltage is adjusted once, the FPGA controls the multi-channel video cross point switch chip and the AD to complete the on-off test and the off-off test once, before the voltage is reduced to 0V, if the test signal voltage is normal, the high-bandwidth 3 video switching circuit works normally, the circuit test is completed, and the FPGA reports the test passing information through the bus;
and step 9: after the test is finished, the FPGA enters a normal working mode, and the input port video is adjusted to the corresponding output port according to the system requirement.
2. The method as claimed in claim 1, wherein the multi-channel video cross-point switch chip is MAX9675ECQ +.
3. The method for detecting high-bandwidth 3 video processing circuit of hanging object management system according to claim 1, wherein a is 1 ＝0.1。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211064695.0A CN115567701A (en) | 2022-08-29 | 2022-08-29 | Detection method of high-bandwidth 3 video processing circuit of suspension management system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211064695.0A CN115567701A (en) | 2022-08-29 | 2022-08-29 | Detection method of high-bandwidth 3 video processing circuit of suspension management system |
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| Publication Number | Publication Date |
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| CN115567701A true CN115567701A (en) | 2023-01-03 |
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| CN202211064695.0A Pending CN115567701A (en) | 2022-08-29 | 2022-08-29 | Detection method of high-bandwidth 3 video processing circuit of suspension management system |
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| CN (1) | CN115567701A (en) |
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- 2022-08-29 CN CN202211064695.0A patent/CN115567701A/en active Pending
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