CN115567069A

CN115567069A - Local area internet receiver circuit

Info

Publication number: CN115567069A
Application number: CN202211469619.8A
Authority: CN
Inventors: 陈奇辉; 罗冰祺; 孙园杰; 马绍宇; 盛云
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2023-01-03
Anticipated expiration: 2042-11-22
Also published as: CN115567069B

Abstract

The application provides a local area internet receiver circuit, which comprises a comparison module, a driving module and an interference detection and adjustment module; the comparison module comprises a first input end and a first output end, and the first input end is coupled with the LIN bus; the driving module comprises a second input end and a second output end, the second input end is coupled with the first output end, and the second output end outputs a LIN output signal; the interference detection and adjustment module comprises a third input end, a fourth input end and a third output end, wherein the third input end is coupled with the LIN bus and receives an LIN input signal; the fourth input end is coupled with the working power supply; the third output end is coupled with the first input end, detects and judges whether the LIN input signal and/or the working power supply are interfered, and provides the adjusting voltage to the first input end when the LIN input signal and/or the working power supply are interfered. The local area internet receiver circuit has good anti-interference performance, and can avoid the circuit from being interfered to output wrong LIN output signals.

Description

Local area internet receiver circuit

Technical Field

The present application relates to the field of integrated circuit design technologies, and in particular, to a local area interconnect network receiver circuit.

Background

An existing LIN (Local Interconnect Network) receiver circuit generally uses a hysteresis comparator as a main component of the circuit, and the hysteresis comparator has a high threshold voltage and a low threshold voltage. When an LIN input signal received by the LIN receiver circuit from an LIN bus is larger than a high threshold voltage (recessive level for short in the industry), an LIN output signal of the LIN receiver circuit is at a high level; when the LIN input signal is < low threshold voltage (dominant level for short in the industry), the LIN output signal is low. However, when the LIN input signal is disturbed, there is a possibility that the LIN output signal will be erroneous. Moreover, the high threshold voltage and the low threshold voltage of the hysteresis comparator are derived from the working power supply, and when the working power supply is disturbed, the high threshold voltage and the low threshold voltage are also influenced and changed, so that the hysteresis comparator outputs a wrong comparison result, and further the LIN outputs a wrong signal.

Disclosure of Invention

Based on the foregoing background defects, an object of the present application is to provide a local interconnect network receiver circuit to solve the technical problem of the prior art that an LIN input signal is interfered to cause an LIN output error signal.

In order to achieve the above object, the present application provides a local area interconnect network receiver circuit, comprising:

the comparison module comprises a first input end, a power supply end and a first output end, wherein the first input end is coupled with the LIN bus and receives an LIN input signal; the power supply end is coupled with a working power supply;

a driving module including a second input terminal and a second output terminal, the second input terminal being coupled to the first output terminal, the second output terminal outputting a LIN output signal;

the interference detection and adjustment module comprises a third input end, a fourth input end and a third output end, wherein the third input end is coupled with the LIN bus and receives the LIN input signal; the fourth input end is coupled with a working power supply; the third output end is coupled with the first input end, detects and judges whether the LIN input signal and/or the working power supply are interfered or not, and provides an adjusting voltage for the first input end when the LIN input signal and/or the working power supply are interfered.

Further, the interference detection and adjustment module comprises a subtractor, a first comparator and an adjustment circuit;

the subtracter comprises a first subtraction input end, a second subtraction input end and a subtraction output end, wherein the first subtraction input end receives the LIN input signal, the second subtraction input end is connected with the working power supply, and the subtracter generates a detection signal after carrying out subtraction processing on the LIN input signal and the working power supply and outputs the detection signal from the subtraction output end;

the first comparator comprises a first comparison input end, a second comparison input end and a first comparison output end, the first comparison input end is connected with the subtraction output end, the second comparison input end receives a first comparison threshold, and the first comparator generates a first judgment signal and outputs the first judgment signal from the first comparison output end;

the adjusting circuit comprises an enabling end, an adjusting input end and an adjusting output end, wherein the enabling end is coupled with the first comparison output end and used for receiving an enabling signal, and the adjusting input end receives the adjusting voltage;

the enable signal comprises two states, when the enable signal is in a first state, the adjusting circuit provides the adjusting voltage for the first comparison input end, and when the enable signal is in a second state, the adjusting circuit does not output.

Further, the local area interconnect network receiver circuit further includes a first filter circuit, and the first filter circuit is connected in series between the LIN bus and the comparison module.

Further, the interference detection and adjustment module further includes a second comparator and an and gate circuit, the second comparator includes a third comparison input terminal, a fourth comparison input terminal and a second comparison output terminal, the third comparison input terminal is used as a fifth input terminal, the fifth input terminal is connected between the first filter circuit and the comparison module, the fourth comparison input terminal receives a second comparison threshold, and the second comparator generates a second determination signal and outputs the second determination signal from the second comparison output terminal;

the AND gate circuit comprises a first AND gate input end, a second AND gate input end and an AND gate output end, the first comparison output end is connected with the first AND gate input end, the second comparison output end is connected with the second AND gate input end, and the AND gate output end outputs a decision signal to the enabling end.

Further, the and gate circuit further includes a third and gate input terminal, the third and gate input terminal is coupled to the first output terminal and configured to receive a driving signal, and the first output terminal outputs the driving signal to the driving module.

Further, the interference detection adjusting module further comprises a first delayer and a second delayer;

the first delayer comprises a first delay input end and a first delay output end, and the first delay input end is connected with the first comparison output end; the first delay output end is connected with the input end of the second AND gate;

the second delayer comprises a second delay input end and a second delay output end, the second delay input end is connected with the output end of the AND gate, and the second delay output end is connected with the adjustment input end;

the comparison module comprises a main comparator and a second filter circuit, the main comparator comprises a fifth comparison input end, a comparison power supply end, a sixth comparison input end and a third comparison output end, the fifth comparison input end is the first input end, the comparison power supply end is the power supply end, the sixth comparison input end receives a main threshold value, and the third comparison output end outputs a main judgment signal;

the second filter circuit comprises a first filter input end and a first filter output end, the first filter input end is connected with the third comparison output end and used for receiving the main judgment signal, and the first filter output end is connected with the second input end and used for outputting a driving signal.

Further, the main comparator is a hysteresis comparator, and the main threshold includes a high threshold voltage and a low threshold voltage.

Further, the driving module comprises an MOS transistor and a phase inverter, the phase inverter comprises an inverting input end and an inverting output end, the inverting input end is the second input end, the inverting output end is connected with the gate of the MOS transistor, the source electrode of the MOS transistor is grounded, and the drain electrode of the MOS transistor serves as the second output end to output the LIN output signal.

Furthermore, the driving module further comprises a pull-up resistor, one end of the pull-up resistor is connected with the drain electrode of the MOS transistor, and the other two ends of the pull-up resistor are connected with an external power supply.

Further, the external power supply is 3V or 5V.

One of the above technical solutions has the following advantages or beneficial effects:

compared with the prior art, the local area internet receiver circuit comprises a comparison module, a driving module and an interference detection and adjustment module; the comparison module comprises a first input end, a power supply end and a first output end, wherein the first input end is coupled with the LIN bus and receives an LIN input signal; the power supply end is coupled with the working power supply; the driving module comprises a second input end and a second output end, the second input end is coupled with the first output end, and the second output end outputs a LIN output signal; the interference detection and adjustment module comprises a third input end, a fourth input end and a third output end, wherein the third input end is coupled with the LIN bus and receives an LIN input signal; the fourth input end is coupled with the working power supply; the third output end is coupled with the first input end, detects and judges whether the LIN input signal and/or the working power supply are interfered, and provides the adjusting voltage to the first input end when the LIN input signal and/or the working power supply are interfered. Whether the LIN input signal and/or the working power supply are/is interfered is judged through the interference detection and adjustment module, when the LIN input signal and/or the working power supply are/is interfered, the interference detection and adjustment module provides the adjustment voltage for the comparison module, the output of the comparison module is ensured to be normal, and therefore the LIN output signal output by the local area internet receiver circuit is kept normal. The local area internet receiver circuit provided by the embodiment of the application has good anti-interference performance, and can avoid outputting wrong LIN output signals after the local area internet receiver circuit is interfered.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for assisting the understanding of the present application, and are not particularly limited to the shapes, the proportional sizes, and the like of the respective members in the present application. Those skilled in the art, having the benefit of the teachings of this application, may select various possible shapes and proportional sizes to implement the present application, depending on the particular situation. In the drawings:

fig. 1 is a schematic structural diagram of a local area interconnect network receiver circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic waveform diagram of signals in an embodiment of a local area interconnect network receiver circuit of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, an embodiment of the present invention provides a local area interconnect network receiver circuit, including: a comparison module 10 and a drive module 20; the comparison module 10 has a first input terminal, a power supply terminal, and a first output terminal, the first input terminal being coupled to the LIN BUS LIN _ BUS and receiving a LIN input signal; the power supply end is coupled with the working power supply VBAT; the driving module 20 has a second input terminal coupled to the output terminal of the comparing module 10 and a second output terminal outputting a LIN output signal RXD; the local area interconnect network receiver circuit further includes an interference detection and adjustment module 30, the interference detection and adjustment module 30 has a third input end, a fourth input end and a third output end, the first input end is coupled to the LIN BUS LIN _ BUS to receive the LIN input signal, the fourth input end is coupled to the working power supply VBAT, the third output end is coupled to the first input end of the comparison module 10 to detect and determine whether the LIN input signal and/or the working power supply VBAT are interfered, and if the interference is detected, the adjustment voltage VREF is provided to the comparison module 10 through the first input end.

The power end of the comparison module 10 can be directly connected with the working power supply VBAT; the operating voltage VDD may be generated by the operating power VBAT through a voltage divider circuit and then connected to the operating voltage VDD. The fourth input terminal of the interference detection and adjustment module 30 may be directly connected to the working power supply VBAT, or may be connected to the working power supply VBAT via a voltage divider circuit or a sampling circuit. When the LIN input signal and the working power supply VBAT are not disturbed, the comparison module 10 and the driving module 20 can work normally, and the LIN output signal RXD is kept normal. When the LIN input signal and/or the working power supply VBAT are/is interfered, and the interference detection and adjustment module 30 detects the interference, the adjustment voltage VREF is provided to the comparison module 10 through the first input end, so that the outputs of the comparison module 10 and the driving module 20 are ensured to be normal, and the LIN output signal RXD is kept normal. The specific value of the adjusting voltage VREF may be set according to actual conditions, and may be the same as the operating voltage VDD of the comparing module 10, for example.

In some embodiments, the comparison module 10 includes a master comparator 11, the master comparator 11 is a hysteresis comparator, the master comparator 11 has a fifth comparison input terminal, a comparison power terminal, a sixth comparison input terminal and a third comparison output terminal, the fifth comparison input terminal is used as a first input terminal of the comparison module 10, the sixth comparison input terminal is connected to a master threshold VTH, and the master threshold VTH has a high threshold voltage and a low threshold voltage VTH (L) (as shown in fig. 2); the comparison power source terminal is used as a power source terminal of the comparison module 10 and is coupled to the operating voltage VDD. When the LIN input signal is larger than a high threshold voltage (recessive level for short), the LIN output signal RXD is at a high level; VTH (L) (dominant level for short) when the LIN input signal < low threshold voltage, the LIN output signal RXD is low. However, when the LIN input signal and/or the operating power supply VBAT are disturbed, the LIN output signal RXD may be erroneous.

Specifically, for the LIN input signal, when the LIN input signal is greater than the high threshold voltage, if the received interference is a low-voltage pulse, and the duration of the low-voltage pulse is usually long, it is easy to make the LIN output signal RXD go wrong (because the LIN output signal RXD should be originally high level, hereinafter referred to as high, but actually is low level, hereinafter referred to as low); if the interference is high-voltage pulse, because the LIN output signal RXD should be high originally and actually high, the LIN output signal will not go wrong; when the LIN input signal < the low threshold voltage VTH (L), if the interference is a low voltage pulse, the LIN output signal will not fail because the LIN output signal RXD should be originally low and actually low; if the interference is high voltage pulse, the LIN output signal RXD may theoretically be erroneous, but actually, because the high voltage pulse generally has a short duration and is affected by other internal circuits, such as a filter circuit, the final LIN output signal RXD is also not erroneous. For the working power supply VBAT, if the interference is low-voltage pulse, the whole circuit can not work due to power loss at the moment, so that the situation can be not considered; the LIN output signal RXD may also be erroneous if the interference is a high voltage pulse. Therefore, in general, the conditions of low-voltage pulse interference occurring when the LIN input signal is greater than the high threshold voltage and high-voltage pulse interference occurring in the operating power supply VBAT are mainly considered.

In some embodiments, the interference detection adjustment module 30 includes a subtractor 31, a first comparator 32 and an adjustment circuit 35,

the subtracter 31 comprises a first subtraction input end, a second subtraction input end and a subtraction output end, wherein the first subtraction input end receives a LIN input signal, the second subtraction input end is connected with a working power supply VBAT, and the subtracter 31 subtracts the LIN input signal and the working power supply VBAT to generate a detection signal LIN _ SENS which is output from the subtraction output end;

the first comparator 32 includes a first comparison input terminal, a second comparison input terminal and a first comparison output terminal, the first comparison input terminal is connected to the subtraction output terminal, the second comparison input terminal receives the first comparison threshold VTH1, and the first comparator 32 generates a first determination signal NP and outputs the first determination signal NP from the first comparison output terminal;

the adjusting circuit 35 includes an enable terminal, an adjusting input terminal and an adjusting output terminal, the enable terminal is coupled to the first comparing output terminal for receiving the enable signal EN _ NP, and the adjusting input terminal receives the adjusting voltage VREF;

the enable signal EN _ NP has two states, and when the enable signal EN _ NP is in the first state, the adjusting circuit 35 provides the adjusting voltage VREF to the first comparing input terminal, and when the enable signal EN _ NP is in the second state, the adjusting circuit 35 has no output.

In an embodiment, the subtractor 31 subtracts the LIN input signal and the working power VBAT to generate the detection signal LIN _ SENS, and when neither the LIN input signal nor the working power VBAT is interfered, the detection signal LIN _ SENS is lower than the first comparison threshold VTH1, the first determination signal NP is at a low level, and accordingly, the enable signal EN _ NP is at a low level, and the adjustment circuit 35 has no output, that is, the interference detection and adjustment module 30 has substantially no influence on the entire local area interconnect network receiver circuit. When any one of the LIN input signal and the working power supply VBAT is interfered, for example, low-voltage pulse interference occurs on the LIN input signal or high-voltage pulse interference occurs on the working power supply VBAT, the value of the detection signal LIN _ SENS becomes larger and higher than the first comparison threshold VTH1, and the first judgment signal NP is at a high level; correspondingly, the enable signal is a high level EN _ NP, and the trigger adjusting circuit 35 provides the adjusting voltage VREF to the comparing module 10 through the first input terminal, so that the output of the comparing module 10 is kept normal, thereby ensuring that the output of the entire lan receiver circuit is kept normal.

In some embodiments, the local interconnect network receiver circuit further comprises a first filter circuit 40, the first filter circuit 40 being connected in series between the LIN BUS LIN _ BUS and the comparison module 10; the interference detection and adjustment module 30 further includes a second comparator 33 and an and-gate circuit 34, the second comparator 33 includes a third comparison input terminal, a fourth comparison input terminal and a second comparison output terminal, the third comparison input terminal is used as a fifth input terminal of the interference detection and adjustment module 30 and is connected between the first filter circuit 40 and the comparison module 10, the fourth comparison input terminal receives a second comparison threshold VTH2, and the second comparator 33 generates a second determination signal MD and outputs the second determination signal MD from the second comparison output terminal;

the and gate circuit 34 includes a first and gate input terminal, a second and gate input terminal, and an and gate output terminal, the first comparison output terminal is connected to the first and gate input terminal, the second comparison output terminal is connected to the second and gate input terminal, and the and gate output terminal outputs the decision signal NP _ DET to the enable terminal.

In some embodiments, the first filter circuit 40 is an RC filter circuit in a specific embodiment, and is connected between the LIN BUS LIN _ BUS and the first input terminal of the comparison module 10, so as to filter noise on the LIN input signal provided on the LIN BUS LIN _ BUS to a certain extent, output the filtered signal LIN _ filter, and improve the stability of the signal; and the voltage range of the LIN input signal can be reduced from a higher high-voltage domain (such as +/-40V) to a lower low-voltage domain according to a certain proportion, so that the function of receiving signals can be completed by using a common low-voltage hysteresis comparator. The second comparator 33 compares the filtered signal LIN _ filter with a second comparison threshold VTH2, when the LIN input signal is not interfered, the filtered signal LIN _ filter is higher than the second comparison threshold VTH2, the second determination signal MD is at a low level and is provided to a second and gate input end of the and gate circuit 34, the decision signal NP _ DET output by the and gate circuit 34 is at a low level, correspondingly, the enable signal EN _ NP is at a low level, and the adjustment circuit 35 does not output; when the LIN input signal is interfered (low-voltage pulse), the filtered signal LIN _ filter becomes low and is lower than the second comparison threshold VTH2, the second determination signal MD is at a high level and is provided to the second and gate input terminal of the and gate circuit 34, at this time, the first determination signal NP is also at a high level (as before), the decision signal NP _ DET output by the and gate circuit 34 is at a high level, and accordingly, the enable signal EN _ NP is at a high level, and the trigger adjustment circuit 35 provides the adjustment voltage VREF to the first input terminal of the comparison module 10, so that the output of the comparison module 10 is kept normal, and further, the output of the entire local area internet receiver circuit is kept normal. The LIN input signal, the working power supply VBAT and the filtered signal LIN _ filter are judged at the same time, so that the accuracy of detecting the interference signal can be improved, and accurate adjustment can be timely made.

In some embodiments, the and circuit 34 further has a third and input terminal coupled to the first output terminal for receiving the driving signal CMPOD, and the first output terminal outputs the driving signal CMPOD to the driving module 20.

It can be understood that when the LIN input signal < the low threshold voltage VTH (L), the problem of pulse interference is not considered, and the driving signal CMPOD output by the comparison module 10 is at a low level and the decision signal NP _ DET output by the and circuit 34 is at a low level; correspondingly, the enable signal EN _ NP is low, and the adjusting circuit 35 has no output; when the LIN input signal is greater than the high threshold voltage, the driving signal CMPOD output by the comparison module 10 is originally at a high level, and at this time, if low-voltage pulse interference occurs on the LIN input signal and/or high-voltage pulse interference occurs on the working power supply VBAT, then both the first determination signal NP and the second determination signal MD are at a high level, so that the decision signal NP _ DET output by the and circuit 34 is at a high level, and correspondingly, the enable signal EN _ NP is at a high level, and the trigger adjustment circuit 35 provides the adjustment voltage VREF to the first input end of the comparison module 10, so that the output of the comparison module 10 is kept normal, and further, the output of the entire local area interconnect network receiver circuit is ensured to be kept normal. In this way, it is ensured that the interference detection and regulation module 30 is not affected when the LIN input signal is less than the low threshold voltage VTH (L), and the interference detection and regulation module 30 keeps the LIN output signal RXD normal by regulating if the LIN input signal and/or the operating power supply VBAT are disturbed only when the LIN input signal is greater than the high threshold voltage.

In some embodiments, the interference detection adjusting module 30 further includes a first DELAY1 and a second DELAY2, the first DELAY1 including a first DELAY input and a first DELAY output, the first DELAY input being connected to the first comparison output; the first delay output end is connected with the input end of the second AND gate;

the second DELAY2 comprises a second DELAY input end and a second DELAY output end, the second DELAY input end is connected with the output end of the AND gate, and the second DELAY output end is connected with the adjusting input end;

the comparison module 10 includes a main comparator 11 and a second filter circuit 12, the main comparator 11 includes a fifth comparison input terminal, a comparison power supply terminal, a sixth comparison input terminal and a third comparison output terminal, the fifth comparison input terminal is the first input terminal, the comparison power supply terminal is the power supply terminal, the sixth comparison input terminal receives the main threshold VTH, and the third comparison output terminal outputs the main judgment signal CMPO;

the second filter circuit 12 includes a first filter input terminal and a first filter output terminal, the first filter input terminal is connected to the third comparison output terminal for receiving the main judgment signal CMPO, and the first filter output terminal is connected to the second input terminal for outputting the driving signal CMPOD.

The second decision signal MD is delayed into the second decision delayed signal MD _ DELAY by the first DELAY1, and the decision signal NP _ DET is delayed into the enable signal EN _ NP by the second DELAY 2. The main judgment signal CMPO generates a sudden change when the LIN input signal and/or the operating power VBAT are interfered, and the second filter circuit 12 can filter the sudden change to keep the stability of the driving signal CMPOD. Referring to fig. 2, in an embodiment, a waveform diagram of a relationship between the filtered signal LIN _ filter, the low threshold voltage VTH (L), the second comparison threshold VTH2, the second determination signal MD, the second determination delay signal MD _ delay, the second determination signal MD, the decision signal NP _ DET, the enable signal EN _ NP, the main determination signal CMPO and the driving signal CMPOD is shown in fig. 2. The first delayer DELAY1 DELAYs the second determination signal MD by a first time duration D1 to obtain a second determination delayed signal MD _ DELAY, the second delayer DELAY2 DELAYs the decision signal NP _ DET by a second time duration D2 to obtain an enable signal EN _ NP, and characteristics of the second filter circuit 12 are adapted to the first delayer DELAY1 and the second delayer DELAY2, so that a glitch time of the main determination signal CMPO can be eliminated, and the obtained driving signal CMPOD can still be kept continuously and stably.

In some embodiments, the driving module 20 includes a MOS transistor Q and an inverter 21, the inverter 21 includes an inverting input terminal and an inverting output terminal, the inverting input terminal is a second input terminal, the inverting output terminal is connected to a gate of the MOS transistor Q, a source of the MOS transistor Q is grounded, and a drain of the MOS transistor Q is a second output terminal, and the LIN output signal RXD is output. When the LIN input signal and/or the operating power supply VBAT are disturbed, the driving signal CMPOD is kept stable, so the LIN output signal RXD is normally output.

When the LIN input signal is greater than the high threshold voltage, the drive signal CMPOD is at a high level, is inverted by the inverter 21, and is supplied to the gate of the MOS transistor Q, the MOS transistor Q is turned off, and the drain of the MOS transistor Q (the LIN output signal RXD) is at a high level; when the LIN input signal is less than the low threshold voltage VTH (L), the drive signal CMPOD is at a low level, is inverted by the inverter 21, and is supplied to the gate of the MOS transistor Q, the MOS transistor Q is turned on, and the drain of the MOS transistor Q (LIN output signal RXD) is at a low level. In this manner, the LIN output signal RXD may be kept in phase with the LIN input signal.

In some embodiments, the driving module 20 further includes a pull-up resistor R, one end of the pull-up resistor R is connected to the drain of the MOS transistor Q, and the other end of the pull-up resistor R is connected to an external power source. In one embodiment, the external power source is 3V or 5V.

Since the LIN output signal RXD is often provided to an external additional circuit that may not be compatible with the operating voltage used by the lan receiver circuit of the present application, connecting the external power source through the pull-up resistor R may satisfy various external practical requirements, such as the most common 3V or 5V operating voltages.

The local area internet receiver circuit that this application embodiment provided, whether receive the interference through interference detection adjusting module 30 detection judgement LIN input signal and/or working power supply VBAT, when LIN input signal and/or working power supply VBAT receive the interference, interference detection adjusting module 30 detects the interference, be about to adjust voltage VREF and provide the first input end of comparison module 10, guarantee that the output of comparison module 10 is normal, and then guarantee that the output of whole local area internet receiver circuit is normal, LIN output signal keeps normally, the local area internet receiver circuit that this application embodiment provided has good interference killing feature, can avoid local area internet receiver circuit to receive the wrong LIN output signal of output after the interference.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided would be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes. The omission in the foregoing claims of any aspect of subject matter that is disclosed herein is not intended to forego the subject matter and should not be construed as an admission that the applicant does not consider such subject matter to be part of the disclosed subject matter.

Claims

1. A local area interconnect network receiver circuit, comprising:

a driving module, including a second input terminal and a second output terminal, the second input terminal being coupled to the first output terminal, the second output terminal outputting a LIN output signal;

the interference detection and adjustment module comprises a third input end, a fourth input end and a third output end, wherein the third input end is coupled with the LIN bus and receives the LIN input signal; the fourth input end is coupled with a working power supply; the third output end is coupled with the first input end, detects and judges whether the LIN input signal and/or the working power supply is interfered, and provides an adjusting voltage to the first input end when the LIN input signal and/or the working power supply are interfered.

2. The local area interconnect network receiver circuit of claim 1, wherein said interference detection adjustment module comprises a subtractor, a first comparator, and an adjustment circuit;

the subtracter comprises a first subtraction input end, a second subtraction input end and a subtraction output end, wherein the first subtraction input end receives the LIN input signal, the second subtraction input end is connected with the working power supply, and the subtracter generates a detection signal after subtracting the LIN input signal and the working power supply and outputs the detection signal from the subtraction output end;

the adjusting circuit comprises an enabling end, an adjusting input end and an adjusting output end, wherein the enabling end is coupled with the first comparing output end and used for receiving an enabling signal, and the adjusting input end receives the adjusting voltage;

3. The local area interconnect network receiver circuit of claim 2, further comprising a first filter circuit connected in series between the LIN bus and the comparison module.

4. The local area interconnect network receiver circuit of claim 3, wherein the interference detection adjustment module further comprises a second comparator and an AND gate circuit, the second comparator comprises a third comparison input terminal, a fourth comparison input terminal and a second comparison output terminal, the third comparison input terminal is used as a fifth input terminal, the fifth input terminal is connected between the first filter circuit and the comparison module, the fourth comparison input terminal receives a second comparison threshold, and the second comparator generates a second determination signal and outputs the second determination signal from the second comparison output terminal;

5. The local area interconnect network receiver circuit of claim 4, wherein the AND circuit further comprises a third AND input coupled to the first output for receiving a driving signal, the first output outputting the driving signal to the driver module.

6. The local area interconnect network receiver circuit of claim 5, wherein said interference detection adjustment module further comprises a first delay and a second delay;

7. The local area interconnect network receiver circuit of claim 6, wherein the main comparator is a hysteretic comparator, and wherein the main threshold comprises a high threshold voltage and a low threshold voltage.

8. The local area interconnect network receiver circuit of claim 6, wherein the driving module comprises a MOS transistor and an inverter, the inverter comprising an inverting input and an inverting output, the inverting input being the second input, the inverting output being connected to a gate of the MOS transistor, a source of the MOS transistor being grounded, a drain of the MOS transistor being the second output, outputting the LIN output signal.

9. The local area interconnect network receiver circuit of claim 8, wherein the driving module further comprises a pull-up resistor, one end of the pull-up resistor is connected to the drain of the MOS transistor, and the other end of the pull-up resistor is connected to an external power source.

10. The local area internet receiver circuit of claim 9, wherein the external power supply is 3V or 5V.