CN115566053B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN115566053B
CN115566053B CN202211206726.1A CN202211206726A CN115566053B CN 115566053 B CN115566053 B CN 115566053B CN 202211206726 A CN202211206726 A CN 202211206726A CN 115566053 B CN115566053 B CN 115566053B
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barrier layer
substrate
layer
drain
semiconductor device
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CN115566053A (en
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范谦
倪贤锋
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Suzhou Han Hua Semiconductors Co Ltd
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Suzhou Han Hua Semiconductors Co Ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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Abstract

The invention discloses a semiconductor device and a preparation method thereof, comprising the following steps: a first substrate; a first barrier layer on the first substrate; the second barrier layer is positioned on the first barrier layer, and a plurality of grid electrodes are arranged on the second barrier layer at intervals along the first direction; a barrier layer over the second barrier layer and covering the gate; a channel layer and a buffer layer sequentially stacked on the barrier layer; the semiconductor device is formed with a plurality of source recesses and a plurality of drain recesses extending from the top surface down to the channel layer, each of the source recess bottom walls is provided with a source, and each of the drain recess bottom walls is provided with a drain. The projection of each drain electrode on the first substrate is overlapped with one first groove, so that the thickness of a dielectric barrier structure between the drain electrode and the grounded first substrate is increased, and the semiconductor device can bear higher voltage and is not easy to break down.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Gallium nitride (GaN), as a representative of third generation semiconductor materials, has many excellent characteristics, high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, good high temperature operation capability, and the like. Third generation semiconductor devices based on gallium nitride, such as High Electron Mobility Transistors (HEMTs), heterojunction Field Effect Transistors (HFETs), etc., have been used.
The conventional epitaxial wafer structure is generally: and the substrate is sequentially grown with a nucleation layer, a buffer layer, a channel layer and a barrier layer, and then a grid electrode, a source electrode and a drain electrode are arranged on the barrier layer. Wherein the substrate can be silicon, sapphire, silicon carbide, gallium nitride, etc.; the channel layer may comprise a iii-v semiconductor material, such as iii-N semiconductor material GaN; the barrier layer material may be AlGaN. For power device applications, the industry is currently primarily using large-sized silicon substrates for gallium nitride transistor epitaxy, mainly because of low cost and compatibility with existing semiconductor chip process lines. However, due to the different lattice constants of the silicon substrate and the channel layer, there is a larger degree of lattice mismatch between the two, which results in a decrease in crystal quality, an increase in defect density, and particularly dislocation defects penetrating through the epitaxial layer, a vertical leakage channel is formed, resulting in a decrease in breakdown voltage and a deterioration in impulse response. Therefore, epitaxial growth often requires the deposition of complex and thicker nucleation and buffer layers to accommodate the stress between the substrate and channel materials, which is detrimental to device yield improvement and heat dissipation improvement. On the other hand, in the conventional GaN transistor device, the source and drain electrodes are required to be formed on the AlGaN barrier layer, and the metal electrode is difficult to form good low-resistance ohmic contact due to the characteristics of ultra-wide forbidden band and low doping of the material, so that the on-resistance of the device is improved and the reliability is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which are used for solving the problems of low breakdown voltage and high ohmic contact resistance of the semiconductor device.
In order to solve the above technical problems, the present invention provides a semiconductor device, comprising:
a first substrate;
a first barrier layer on the first substrate;
the second barrier layer is positioned on the first barrier layer, and a plurality of grid electrodes are arranged on the second barrier layer at intervals along the first direction;
a barrier layer over the second barrier layer and covering the gate;
a channel layer and a buffer layer sequentially stacked on the barrier layer;
the semiconductor device is provided with a plurality of source grooves and a plurality of drain grooves, the source grooves and the drain grooves extend downwards from the top surface to the channel layer, the bottom wall of each source groove is provided with a source electrode, and the bottom wall of each drain groove is provided with a drain electrode;
the multiple gates, the multiple sources and the multiple drains form a multi-interdigital field effect transistor unit, and the projection of the gate of each field effect transistor unit on the first substrate is positioned between the projections of the source and the drain of the same field effect transistor unit on the first substrate.
Optionally, a plurality of first grooves are disposed above the first substrate along the first direction, the plurality of first grooves and projections of the plurality of gates on the first substrate are alternately disposed, and the first barrier layer fills the first grooves.
Optionally, a projection of each drain electrode on the first substrate overlaps one of the first grooves.
Optionally, the semiconductor device further includes:
the first dielectric layer covers the buffer layer and the inner walls of the source groove and the drain groove;
the source electrode and the drain electrode are exposed after penetrating through the first dielectric layer.
Optionally, the semiconductor device further includes:
the second dielectric layer is positioned below the barrier layer and above the second barrier layer and covers the grid electrode, and the thickness of the second barrier layer is 3-200 nm.
Optionally, the first groove has a width of 5 to 15 μm along the first direction and a depth of 0.5 to 5 μm along a second direction, the second direction being a thickness direction of the semiconductor device perpendicular to the first direction.
Optionally, the thickness of the first barrier layer along the second direction is 0.1-1 μm, and the thickness of the second barrier layer along the second direction is 0.2-0.5 μm.
Optionally, the sum of thicknesses of the first barrier layer and the second barrier layer along the second direction is not greater than 1 μm.
Based on the same inventive concept, the invention also provides a preparation method of the semiconductor device, comprising the following steps:
providing a first substrate, and forming a first barrier layer on the first substrate;
planarizing the first barrier layer;
providing a second substrate, and sequentially forming a nucleation layer, a buffer layer, a channel layer and a barrier layer on the second substrate;
a plurality of grid electrodes are arranged on the barrier layer at intervals along a first direction;
forming a second barrier layer on the barrier layer, wherein the second barrier layer covers the grid electrode;
transferring the second barrier layer, and aligning and bonding the second barrier layer to the first barrier layer;
removing the second substrate and the nucleation layer so that the buffer layer is positioned on the top surface of the semiconductor device;
forming a plurality of source grooves and a plurality of drain grooves which are etched downwards from the top surface to the channel layer on the semiconductor device, wherein a source is arranged on the bottom wall of each source groove, and a drain is arranged on the bottom wall of each drain groove;
the multiple gates, the multiple sources and the multiple drains form a multi-interdigital field effect transistor unit, and the projection of the gate of each field effect transistor unit on the first substrate is positioned between the projections of the source and the drain of the same field effect transistor unit on the first substrate.
Optionally, forming a first barrier layer on the first substrate includes:
and arranging a plurality of first grooves along the first direction on the first substrate, wherein the projections of the plurality of first grooves and the plurality of grid electrodes on the first substrate are alternately arranged, a first blocking layer is formed on the first substrate, and the first blocking layer fills the first grooves.
Optionally, a projection of each drain electrode on the first substrate overlaps one of the first grooves.
Optionally, the method further comprises:
forming a first dielectric layer, wherein the first dielectric layer covers the buffer layer and the inner walls of the source groove and the drain groove;
forming openings in the bottom wall of the source recess and the bottom wall of the drain recess;
and a source electrode and a drain electrode are respectively arranged at the openings of the bottom walls of the source electrode groove and the drain electrode groove, so that the source electrode and the drain electrode are exposed after penetrating through the first dielectric layer.
Optionally, the method further comprises:
and forming a second dielectric layer, wherein the second dielectric layer is positioned below the barrier layer and above the second barrier layer and covers the grid electrode, and the thickness of the second dielectric layer is 3-200 nm.
In summary, according to the semiconductor device and the method for manufacturing the same provided by the embodiments of the present invention, by removing the second substrate and the nucleation layer, the initial epitaxial vertical leakage channel is no longer connected to the conductive substrate, so that lateral leakage and breakdown through the substrate can be effectively prevented;
by arranging the first blocking layer and the second blocking layer on the first substrate, the material of the first blocking layer is the completely insulated first dielectric layer material, and electric leakage between the epitaxial layer and the first substrate can be effectively blocked. In particular, the projection of each drain electrode on the first substrate is overlapped with one first groove, so that the thickness of a dielectric barrier structure between the drain electrode and the grounded first substrate is increased, and the semiconductor device can bear higher voltage and is not easy to break down;
the first substrate is used as a grounding shield, a plate field structure is formed between the first substrate and the grid electrode, so that the electric field distribution of a channel between the grid electrode and the drain electrode can be effectively dispersed, the local electric field intensity can be reduced, and the breakdown voltage can be improved; the source electrode and the drain electrode are contacted with gallium nitride from one side of the channel, not from the barrier layer like a traditional transistor, on one hand, the forbidden bandwidth of the gallium nitride is small, and on the other hand, the gallium nitride with the N polar surface is contacted from the opposite direction, so that the surface treatment is facilitated to form low-resistance ohmic contact, the contact resistance can be effectively reduced, and the electrical property of the device is improved.
Further, a first dielectric layer is arranged, the first dielectric layer covers the nucleation layer, the source electrode groove and the inner wall of the drain electrode groove, and the source electrode and the drain electrode are exposed after penetrating through the first dielectric layer, so that surface electric leakage is prevented.
Drawings
In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating various aspects of the technology and devices described herein.
Fig. 1 to 11B are schematic structural views showing a method for manufacturing a semiconductor device of the present invention at some stages.
Wherein reference numerals are as follows:
2-first substrate, 3-first groove, 4-first barrier layer, 6-second substrate, 8-nucleation layer, 10-buffer layer, 12-channel layer, 14-barrier layer, 16-gate, 18-second barrier layer, 20-source groove, 22-drain groove, 24-source, 26-drain, 28-first dielectric layer, 30-second dielectric layer.
Detailed Description
The semiconductor device and the method for fabricating the same according to the present invention are described in further detail below with reference to the accompanying drawings and the embodiments, and those skilled in the art will readily appreciate that the present invention has other advantages and effects. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
The present embodiment provides a semiconductor device including the following structures:
a semiconductor device according to the present invention is shown in fig. 8A, comprising a first substrate 2, a first barrier layer 4, the first barrier layer 4 being located on the first substrate 2, a second barrier layer 18, the second barrier layer 18 being located on the first barrier layer 4, the second barrier layer 18 being provided with a plurality of gates 16 spaced apart along a first direction, a barrier layer 14, the barrier layer 14 being located above the second barrier layer 18 and covering the gates 16, a channel layer 12, a buffer layer 10 being stacked in sequence on the barrier layer 14, the semiconductor device being formed with a plurality of source recesses 20 and a plurality of drain recesses 22 extending from a top surface down to the channel layer 12, each source recess 20 being provided with a source 24, each drain recess 22 being provided with a drain 26, the plurality of gates 16, the plurality of sources 24, the plurality of drains 26 forming a multi-finger field effect transistor cell, each of the gates 16 being projected onto the same substrate 2 between the drain recesses 24 and the first substrate 2.
The material of the first substrate 2 may be silicon, sapphire, silicon carbide, gallium nitride, etc., and in this embodiment, a common conductive silicon substrate is preferably used, as the device ground, the material of the buffer layer 10 may be AlGaN or GaN, the material of the channel layer 12 may be GaN, the material of the barrier layer 14 may be AlGaN, and the material of the first barrier layer 4 may be a completely insulating dielectric layer material SiO 2 The material of the second barrier layer 18 may be a completely insulating dielectric material SiO 2 The thickness of the first barrier layer 4 along the second direction is 0.1-1 μm, the thickness of the second barrier layer 18 along the second direction is 0.2-0.5 μm, and the sum of the thicknesses of the first barrier layer 4 and the second barrier layer 18 along the second direction is preferably not more than 1 μm, which is the best technical effect.
Compared with the common structure in the background technology, the semiconductor device provided by the embodiment removes the second substrate 6, and the original epitaxial vertical leakage channel is not connected with the conductive substrate any more, so that the lateral leakage and breakdown through the substrate can be effectively prevented; by providing the first barrier layer 4 and the second barrier layer 18 on the first substrate 2, the materials of which are completely insulating dielectric layer materials, the electric leakage between the epitaxial layer and the first substrate 2 can be effectively blocked. The first substrate 2 is used as a grounding shield, and a plate field structure is formed between the first substrate and the grid electrode 16, so that the electric field distribution of a channel between the grid electrode and the drain electrode can be effectively dispersed, the local electric field intensity can be reduced, and the breakdown voltage can be improved; the source electrode and the drain electrode are contacted with gallium nitride from one side of the channel, not from the barrier layer like a traditional transistor, on one hand, the forbidden bandwidth of the gallium nitride is small, and on the other hand, the gallium nitride with the N polar surface is contacted from the opposite direction, so that the surface treatment is facilitated to form low-resistance ohmic contact, the contact resistance can be effectively reduced, and the electrical property of the device is improved.
Fig. 8B shows a semiconductor device according to the present invention, which is a further improvement over the embodiment of fig. 8A, wherein a plurality of first grooves 3 are arranged above a first substrate 2 along the first direction, the plurality of first grooves 3 are alternately arranged with projections of the plurality of gates 16 on the first substrate 2, and the first barrier layer 4 fills the first grooves 3. Namely, the first substrate 2 is etched with the first groove 3, the trapezoid groove is in a preferable shape, the utilization efficiency is high, and the trapezoid groove can also be a groove in a rectangle shape or other shapes. The width of the trapezoid groove along the first direction is 5-15 μm, and the depth of the trapezoid groove along the second direction is 0.5-5 μm, and the projection of each drain electrode 26 on the first substrate 2 is overlapped with one first groove 3, so that the thickness of a blocking structure between the drain electrode 26 and the grounded first substrate 2 is increased, and the semiconductor device can bear higher voltage and is not easy to break down.
A semiconductor device according to the present invention is shown in fig. 10A, which is a further improvement over the embodiment of fig. 8A, and further comprises a first dielectric layer 28, wherein the first dielectric layer 28 covers the buffer layer 10 and the inner walls of the source recess 20 and the drain recess 22; the source 24 and the drain 26 are exposed through the first dielectric layer 28. The first dielectric layer 28 material may be completely insulating dielectric layer material SiO 2 Or SiN x The first dielectric layer 28 can effectively prevent surface leakage and improve device reliability.
A semiconductor device according to the present invention is shown in fig. 10B, which is a further improvement over the embodiment of fig. 8B, and further includes a first dielectric layer 28, wherein the first dielectric layer 28 covers the buffer layer 10 and the inner walls of the source recess 20 and the drain recess 22; the saidThe source 24 and the drain 26 are exposed through the first dielectric layer 28. The first dielectric layer 28 material may be completely insulating dielectric layer material SiO 2 Or SiN x The first dielectric layer 28 can effectively prevent surface leakage and improve device reliability.
A semiconductor device according to the present invention is further improved as shown in fig. 11A compared to the embodiment of fig. 10A, and the semiconductor device further includes a second dielectric layer 30, where the second dielectric layer 30 is located below the barrier layer 14 and above the second barrier layer 18 and covers the gate 16, that is, the barrier layer 14 is not in direct contact with the gate 16, and the thickness of the second dielectric layer 30 is 3nm to 200nm, and the material of the second dielectric layer 30 may be silicon oxide, silicon nitride, aluminum oxide, or the like.
A further improvement of the embodiment of the present invention is shown in fig. 11B, and the semiconductor device further includes a second dielectric layer 30, where the second dielectric layer 30 is located below the barrier layer 14 and above the second barrier layer 18 and covers the gate 16, that is, the barrier layer 14 is not in direct contact with the gate 16, and the thickness of the second dielectric layer 30 is 3nm to 200nm, and the material of the second dielectric layer 30 may be silicon oxide, silicon nitride, aluminum oxide, or the like.
Example two
The embodiment provides a method for manufacturing a semiconductor device, which includes:
providing a first substrate, and forming a first barrier layer on the first substrate;
planarizing the first barrier layer;
providing a second substrate, and sequentially forming a nucleation layer, a buffer layer, a channel layer and a barrier layer on the second substrate;
a plurality of grid electrodes are arranged on the barrier layer at intervals along a first direction;
forming a second barrier layer on the barrier layer, wherein the second barrier layer covers the grid electrode;
transferring the second barrier layer, and aligning and bonding the second barrier layer to the first barrier layer;
removing the second substrate and the nucleation layer so that the buffer layer is positioned on the top surface of the semiconductor device;
forming a plurality of source grooves and a plurality of drain grooves which are etched downwards from the top surface to the channel layer on the semiconductor device, wherein a source is arranged on the bottom wall of each source groove, and a drain is arranged on the bottom wall of each drain groove;
the multiple gates, the multiple sources and the multiple drains form a multi-interdigital field effect transistor unit, and the projection of the gate of each field effect transistor unit on the first substrate is positioned between the projections of the source and the drain of the same field effect transistor unit on the first substrate.
In particular, referring to fig. 1 to 11B, schematic structural diagrams of the method for manufacturing a semiconductor device according to the present invention at some stages are shown.
As shown in fig. 1, a first substrate 2 is provided, and the material of the first substrate 2 may be silicon, sapphire, silicon carbide, gallium nitride, etc., and in this embodiment, a common conductive silicon substrate is preferably used as the ground of the device; as shown in fig. 2A, a first barrier layer 4 is deposited on the first substrate 2. Alternatively, as shown in fig. 2B, the first recess 3 is etched on the first substrate 2, and then the first barrier layer 4 is deposited. The first groove 3 may be a trapezoid groove, the width of the first groove 3 along the first direction is 5-15 μm, the depth along the second direction is 0.5-5 μm, and the first barrier layer 4 material may be SiO 2 . Planarizing the first barrier layer includes: the first barrier layer 4 is deposited by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) plasma enhanced chemical vapor deposition method or a high-temperature LPCVD (Low Pressure Chemical Vapor Deposition) low-pressure chemical vapor deposition method, and then the first barrier layer 4 is polished by adopting a CMP (Chemical Mechanical Polishing) chemical mechanical polishing method.
As shown in fig. 3, a second substrate 6 is provided, and a nucleation layer 8, a buffer layer 10, a channel layer 12, and a barrier layer 14 are sequentially formed on the second substrate 6; a plurality of gates 16 are disposed on the barrier layer 14 at intervals along a first direction. The steps of fig. 1-2A, or the steps of fig. 1-2B may be performed synchronously with the step of fig. 3, and the position information of the first grooves 3 in fig. 2B is obtained according to the position information of the gates 16, so as to form the projections of the plurality of first grooves 3 and the plurality of gates 16 on the first substrate 2 in an alternating manner.
As shown in fig. 4, a second barrier layer 18 is deposited on the barrier layer 14, the second barrier layer 18 covers the gate electrode 16, and the second barrier layer 18 is deposited by PECVD plasma enhanced chemical vapor deposition, and the temperature is controlled below 400 ℃, wherein the thickness of the second barrier layer 18 in the second direction after polishing may be 0.2-0.5 μm. Before bonding, it is critical to surface treat the wafer to activate its surface.
As shown in fig. 5A or 5B, the second barrier layer 18 is transferred so that the second substrate 6 is located on top of the semiconductor device, and the second barrier layer 18 and the first barrier layer 4 are directly bonded: the second barrier layer 18 and the first barrier layer 4 are bonded by using a thermal fusion bonding (fusion bonding) method with the second barrier layer 18 and the first barrier layer 4 as media, and van der waals forces between atoms of the second barrier layer 18 and the first barrier layer 4 can directly bond the two together. By providing the first barrier layer 4 and the second barrier layer 18 on the first substrate 2, the material is completely insulating dielectric material SiO 2 The leakage between the epitaxial layer and the first substrate 2 can be effectively blocked.
As shown in fig. 6A or 6B, the second substrate 6 is removed so that the nucleation layer 8 is located on the top surface of the semiconductor device. The nucleation layer material may be AlN, and the second substrate 6 may be removed by a method of grinding and thinning in combination with dry etching, and typically, the thinned second substrate 6 needs to be polished and ground to remove surface defects generated during the substrate removal process. The remaining second substrate 6 silicon material may be completely removed using plasma etching techniques. Since there is no need to retain silicon material and there is no concern about the etching anisotropy, only sulfur hexafluoride (SF 6) is generally used as a reaction gas to increase the etching rate, reduce the generation of polymer, and simultaneously increase the over-etching ratio to completely remove the second substrate 6. Alternatively, the nucleation layer material may be entirely removed and remain on the buffer layer 10. Compared with the common structure in the background art, the second substrate 6 is removed, and the original epitaxial vertical leakage channel is no longer connected with the conductive substrate, so that the lateral leakage and breakdown through the substrate can be effectively prevented.
As shown in fig. 7A or 7B, a plurality of source recesses 20 and a plurality of drain recesses 22 extending from the top surface down to the channel layer 12 are formed on the semiconductor device. As shown in fig. 8A or fig. 8B, a bottom wall of each source recess 20 is provided with a source 24, a bottom wall of each drain recess 22 is provided with a drain 26, and a projection of each drain 26 on the first substrate 2 overlaps with one first recess 3, so that a thickness of a dielectric barrier structure between the drain and the grounded first substrate 2 is increased, and the semiconductor device can bear higher voltage and is not easy to break down; the electrodes are placed in the channel layer 12 instead of the barrier layer 14, in combination with a suitable surface treatment process, such that the contact resistance is reduced. The first substrate 2 is used as the common ground of the device and is located under the gate electrode 16, so that the electric field distribution in the channel between the gate and the drain can be improved, and breakdown caused by too concentrated electric field can be avoided. The source electrode and the drain electrode are contacted with gallium nitride from one side of the channel, not from the barrier layer like a traditional transistor, on one hand, the forbidden bandwidth of the gallium nitride is small, and on the other hand, the gallium nitride with the N polar surface is contacted from the opposite direction, so that the surface treatment is facilitated to form low-resistance ohmic contact, the contact resistance can be effectively reduced, and the electrical property of the device is improved.
As shown in fig. 9A or fig. 9B, before the source electrode 24 and the drain electrode 26 are disposed, a first dielectric layer 28 is formed, the first dielectric layer 28 covers the buffer layer 10, and the inner walls of the source recess 20 and the drain recess 22, and the first dielectric layer 28 is made of SiO 2 Or SiN x . As shown in fig. 10A or 10B, the bottom wall of the source recess 20 and the bottom wall of the drain recess 22 are etched to form openings, and a source 24 and a drain 26 are provided at the openings of the bottom walls of the source recess 20 and the drain recess 22, respectively, so that the source 24 and the drain 26 pass through the first electrodeDielectric layer 28 is then exposed to form an ohmic contact. The first dielectric layer 28 can effectively reduce surface leakage between the source electrode 24 and the drain electrode 26, and improve device reliability.
As shown in fig. 11A or 11B, a second dielectric layer 30 may be formed over the barrier layer 14, and then a plurality of gates 16 may be disposed on the second dielectric layer 30 at intervals along a first direction. The thickness of the second dielectric layer 30 is 3 nm-200 nm, and the material of the second dielectric layer 30 may be silicon oxide, silicon nitride, aluminum oxide, etc.
The multiple gates 16, the multiple sources 24, and the multiple drains 26 form multiple interdigital fet units, and the projection of the gate of each fet unit on the first substrate 2 is located between the projections of the source and the drain of the same fet unit on the first substrate 2, that is, multiple fet units are formed.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (9)

1. A semiconductor device, comprising:
a first substrate;
a first barrier layer on the first substrate;
the second barrier layer is positioned on the first barrier layer, and a plurality of grid electrodes are arranged on the second barrier layer at intervals along the first direction;
a barrier layer over the second barrier layer and covering the gate;
a channel layer and a buffer layer sequentially stacked on the barrier layer;
the semiconductor device is provided with a plurality of source grooves and a plurality of drain grooves, the source grooves and the drain grooves extend downwards from the top surface of the device to the channel layer, the bottom wall of each source groove is provided with a source electrode, and the bottom wall of each drain groove is provided with a drain electrode;
the multiple gates, the multiple sources and the multiple drains form a multi-interdigital field effect transistor unit, and the projection of the gate of each field effect transistor unit on the first substrate is positioned between the projections of the source and the drain of the same field effect transistor unit on the first substrate;
the first barrier layer and the second barrier layer are made of completely insulating dielectric layer materials;
a plurality of first grooves are formed above the first substrate along the first direction, the first grooves and the projections of the grid electrodes on the first substrate are alternately arranged, and the first barrier layer fills the first grooves;
the projection of each drain electrode on the first substrate is overlapped with one first groove.
2. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:
the first dielectric layer covers the buffer layer and the inner walls of the source groove and the drain groove;
the source electrode and the drain electrode are exposed after penetrating through the first dielectric layer.
3. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:
the second dielectric layer is positioned below the barrier layer and above the second barrier layer and covers the grid electrode, and the thickness of the second dielectric layer is 3 nm-200 nm.
4. The semiconductor device according to claim 1, wherein a width of the first groove in the first direction is 5 to 15 μm, and a depth in a second direction, which is a thickness direction of the semiconductor device perpendicular to the first direction, is 0.5 to 5 μm.
5. The semiconductor device according to claim 4, wherein a thickness of the first barrier layer in the second direction is 0.1 to 1 μm, and a thickness of the second barrier layer in the second direction is 0.2 to 0.5 μm.
6. The semiconductor device according to claim 4, wherein a sum of thicknesses of the first barrier layer and the second barrier layer in the second direction is not more than 1 μm.
7. A method of manufacturing a semiconductor device, comprising:
providing a first substrate, and forming a first barrier layer on the first substrate;
planarizing the first barrier layer;
providing a second substrate, and sequentially forming a nucleation layer, a buffer layer, a channel layer and a barrier layer on the second substrate;
a plurality of grid electrodes are arranged on the barrier layer at intervals along a first direction;
forming a second barrier layer on the barrier layer, wherein the second barrier layer covers the grid electrode;
transferring the second barrier layer, and aligning and bonding the second barrier layer to the first barrier layer;
removing the second substrate and the nucleation layer so that the buffer layer is positioned on the top surface of the semiconductor device;
forming a plurality of source grooves and a plurality of drain grooves which are etched downwards from the top surface to the channel layer on the semiconductor device, wherein a source is arranged on the bottom wall of each source groove, and a drain is arranged on the bottom wall of each drain groove;
the multiple gates, the multiple sources and the multiple drains form a multi-interdigital field effect transistor unit, and the projection of the gate of each field effect transistor unit on the first substrate is positioned between the projections of the source and the drain of the same field effect transistor unit on the first substrate;
the first barrier layer and the second barrier layer are made of completely insulating dielectric layer materials;
forming a first barrier layer on the first substrate includes:
providing a plurality of first grooves along the first direction on the first substrate, wherein the plurality of first grooves are alternately arranged with the projections of the plurality of grids on the first substrate, a first blocking layer is formed on the first substrate, and the first blocking layer fills the first grooves;
the projection of each drain electrode on the first substrate is overlapped with one first groove.
8. The method for manufacturing a semiconductor device according to claim 7, further comprising:
forming a first dielectric layer, wherein the first dielectric layer covers the buffer layer and the inner walls of the source groove and the drain groove;
forming openings in the bottom wall of the source recess and the bottom wall of the drain recess;
and a source electrode and a drain electrode are respectively arranged at the openings of the bottom walls of the source electrode groove and the drain electrode groove so that the source electrode and the drain electrode are exposed after penetrating through the dielectric layer.
9. The method for manufacturing a semiconductor device according to claim 7, further comprising:
and forming a second dielectric layer, wherein the second dielectric layer is positioned below the barrier layer and above the second barrier layer and covers the grid electrode, and the thickness of the second dielectric layer is 3-200 nm.
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