CN115563026A - Mapping table reconstruction method and data storage device - Google Patents
Mapping table reconstruction method and data storage device Download PDFInfo
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- CN115563026A CN115563026A CN202211560631.XA CN202211560631A CN115563026A CN 115563026 A CN115563026 A CN 115563026A CN 202211560631 A CN202211560631 A CN 202211560631A CN 115563026 A CN115563026 A CN 115563026A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/063—Address space extension for I/O modules, e.g. memory mapped I/O
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a mapping table reconstruction method and data storage equipment, and belongs to the technical field of storage. The method for reconstructing the mapping table comprises the following steps: configuring a first cache and a second cache in a controller, wherein the first cache stores a mapping table from a logical address to a physical address during reconstruction, and the second cache stores the mapping table from the physical address to the logical address during reconstruction; rebuilding a mapping table from the logical address to the physical address, and outputting a flash memory block and a next block of a last block participating in the rebuilding of the mapping table from the logical address to the physical address; rebuilding the mapping table from the physical address to the logical address according to the flash memory block and the block output after rebuilding the mapping table from the logical address to the physical address; and reserving a part of the first cache and a part of the second cache which store the reconstructed mapping table, and releasing other first caches and other second caches. The method for reconstructing the mapping table can improve the efficiency of reconstructing the mapping table.
Description
Technical Field
The invention belongs to the technical field of storage, and particularly relates to a mapping table reconstruction method and data storage equipment.
Background
When the storage device is in operation, part or all of the mapping table is read from the nonvolatile memory and is temporarily stored in the volatile memory for energy efficiency. With the continuous operation of the storage device, the mapping table is updated by executing the command issued by the host or the internal command, so that the content of the mapping table temporarily stored on the volatile memory is different from the content of the mapping table in the non-volatile memory. If an abnormal power failure occurs, the contents of the mapping table may be lost. In the process of storage after power failure, due to the lack of the content of the mapping table, abnormity occurs during writing and reading.
Disclosure of Invention
The invention aims to provide a mapping table rebuilding method and data storage equipment, and solve the problem that a mapping table is lost when abnormal power failure occurs.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a mapping table reconstruction method, which at least comprises the following steps:
configuring a first cache and a second cache in a controller, wherein the first cache stores a mapping table from a logical address to a physical address during reconstruction, and the second cache stores the mapping table from the physical address to the logical address during reconstruction;
rebuilding the mapping table from the logical address to the physical address, and outputting a flash memory block and a next block of the last block participating in the rebuilding of the mapping table from the logical address to the physical address;
rebuilding the mapping table from the physical address to the logical address according to the rebuilt mapping table from the logical address to the physical address and the output flash memory block and block; and
and reserving part of the first cache and part of the second cache which store the reconstructed logical address-to-physical address mapping table and the reconstructed physical address-to-logical address mapping table, and releasing other first caches and other second caches.
In an embodiment of the present invention, when reconstructing the logical address to physical address mapping table, the method includes the following steps:
reading a logical address-to-physical address recording table in a system flash memory area to obtain physical addresses of each logical address-to-physical address mapping table; and
a physical address to logical address mapping table and corresponding physical address to logical address data structures are read in a system flash memory.
In an embodiment of the present invention, when reconstructing the logical address to physical address mapping table, the method includes the following steps:
judging whether the flash memory block information in the logical address data structure of the physical address with the operation type of being flushed back in the cache is a valid value or not; and
judging whether the flash block information in the data structure of the physical address to the logical address, the operation type of which is updated in the cache, is a valid value or not.
In an embodiment of the present invention, when reconstructing the logical address to physical address mapping table, the method includes the following steps:
when the operation type is that the flash memory block information in the data structure from the flushed back physical address to the logical address is an invalid value, and the operation type is that the flash memory block information in the data structure from the updated physical address to the logical address is an invalid value, the mapping table from the logical address to the physical address does not need to be rebuilt.
In an embodiment of the present invention, when reconstructing the logical address to physical address mapping table, the method includes the following steps:
when the operation type is that the flash memory block information from the refreshed physical address to the logical address data structure is an invalid value, and the operation type is that the flash memory block information from the updated physical address to the logical address data structure is an effective value;
reading a mapping table from a physical address to a logical address of a corresponding block in a flash memory block in a data structure of the physical address to the logical address, wherein the operation type is updated, covering the mapping table from the physical address to the logical address, the operation type of which is refreshed, in the cache by using the mapping table from the physical address to the logical address, and initializing flash memory block information and block information corresponding to the mapping table from the physical address to the logical address, which are read, into the data structure from the physical address to the logical address, the operation type of which is refreshed, in the cache by using the flash memory block information and the block information; and
and clearing the back flushing flag bits of all the entries in the mapping table from the physical address to the logical address in the cache.
In an embodiment of the present invention, when reconstructing the logical address to physical address mapping table, the method includes the following steps:
when the operation type is the flash memory block information in the data structure of the physical address to the logical address which is flushed back is the effective value, reading all physical address to logical address mapping tables in the rest blocks of the flash memory block in the data flash memory area, and sequentially placing the mapping tables in a cache after the operation type is the physical address to the logical address which is flushed back, and identifying the physical address to the logical address mapping table which is flushed back and the physical address to the logical address mapping table which follows the mapping table as the state to be flushed back.
In an embodiment of the present invention, when reconstructing the logical address to physical address mapping table, the method further includes the following steps:
judging whether the corresponding content of all mapping tables of the physical address to the logical address to be flushed back in the cache is empty, if so, indicating that the reconstruction of the mapping tables of the logical address to the physical address is completed, outputting a final flash memory block and a block, and if not, clearing the flushing flag bits of all entries in the mapping tables of the physical address to the logical address which are flushed back and all the subsequent mapping tables of the physical address to the logical address;
in the mapping table from the physical address to the logical address to be refreshed, the flash memory block information and the block information are the same as those from the physical address to the logical address table with the operation type being updated, and the flag bit is marked to be refreshed; and
and synchronously brushing all physical address to logical address mapping tables in the cache.
In one embodiment of the present invention, clearing the flag bits of all entries in the mapping table from physical address to logical address comprises the following steps:
setting a bit mask in the cache value setting unit to clear all the back-flushing flag bits;
setting the preset value in the cache value setting unit to be zero;
setting the address length in the cache value setting unit as all the range of the back flushing flag bits needing to be cleared; and
and starting a cache value setting unit, and clearing the back flushing flag bits of all the entries in the required range.
In an embodiment of the present invention, the step of flushing the flag bit of the mapping table from the physical address to the logical address with the operation type to be flushed back includes the following steps:
setting a bit mask in a cache searching unit, and comparing the bit mask and brushing back a flag bit;
setting a search value in a cache search unit, wherein the search value is a refresh flag bit;
starting a cache searching unit, and finding out all items marked with the refresh flag bit in a mapping table from the physical address to the logical address with the operation type of updating;
acquiring an address block table according to the search result; and
and marking back a mark bit in the corresponding entry of the mapping table from the target physical address to the logical address according to the address block table.
In an embodiment of the present invention, the step of synchronously flushing all mapping tables from physical addresses to logical addresses in the cache comprises the following steps:
judging whether the physical address to logical address entry corresponding to the physical address to logical address mapping table index is marked as a refresh flag bit;
reading a logical address-to-physical address mapping table from the physical address to the logical address entry and storing the mapping table in a first cache;
searching other items belonging to the mapping table from the logical address to the physical address by using a cache searching unit in all the mapping tables from the physical address to the logical address to be flushed back;
and flushing all physical address to logical address entries belonging to the logical address to physical address mapping table back to the logical address to physical address mapping table, and flushing the marks of the flushed physical address to logical address entries back to the flag bits.
In an embodiment of the present invention, the step of searching the remaining entries belonging to the logical address to physical address mapping table in all the physical address to logical address mapping tables to be flushed back by using the cache search unit includes the following steps:
setting data pre-searched in a cache search unit as physical address to logical address entries;
setting a bit mask in a cache searching unit, and only displaying the position information of a mapping table from a logical address to a physical address; and
and starting a cache search unit and storing the search result.
In an embodiment of the present invention, when reconstructing the physical address to logical address mapping table, the method includes the following steps:
acquiring flash memory block information and block information output by a mapping table from a reconstructed logical address to a physical address; and
and judging whether the flash memory block corresponding to the flash memory block information is valid or not and judging whether the block exceeds the total block number or not.
In an embodiment of the present invention, when reconstructing the physical address to logical address mapping table, the method includes the following steps:
when the flash memory block corresponding to the flash memory block information is invalid, or the flash memory block corresponding to the flash memory block information is valid and the number of the blocks exceeds the total number of the blocks;
the physical address to logical address mapping table and the physical address to logical address data structure are reset to be in a non-data state, and the reconstruction of the physical address to logical address mapping table is completed.
In an embodiment of the present invention, when reconstructing the mapping table from physical addresses to logical addresses, when the flash memory blocks corresponding to the flash memory block information are valid and the number of blocks does not exceed the total number of blocks, the method further includes the following steps:
judging whether the flash memory block information and the block information have the same data structure from the physical address to the logical address with the operation type of updating, if so, reading a page corresponding to the index from the physical address to the logical address mapping table in the data flash memory area, updating the physical address to the logical address mapping table by the logical address in the metadata of the page, and continuing the index forward until an empty page is read or the tail end of the mapping table is read; if not, the mapping table from the physical address to the logical address and the data structure from the physical address to the logical address are reset to be in a no-data state, the data structure from the physical address to the logical address is initialized by the flash block information and the block information, a page corresponding to the index from the physical address to the logical address mapping table in the data flash area is read, the mapping table from the physical address to the logical address is updated by the logical address in the metadata of the page, and the index continues to move forward until an empty page is read or the end of the mapping table is read.
The present invention also provides a data storage device having stored thereon a computer program which, when executed by a processor, implements a method of reconstructing a mapping table as described above.
As described above, in the method for reconstructing a mapping table and the data storage device provided by the present invention, in the period of reconstructing the mapping table, the first cache and the second cache are configured in the controller for use in reconstructing the mapping table, and after the mapping table is reconstructed, most of the first cache and the second cache are released for use in reading and writing, so that the reconstruction efficiency of the mapping table is improved. When the mapping table from the logical address to the physical address is rebuilt, the mapping table from the physical address to the logical address in all the blocks in the flash memory block is read, the mapping table from the physical address to the logical address is synchronously flushed back, and the rebuilding rate of the mapping table is accelerated again. The entry of the mapping table from the physical address to the logical address is configured with a back-flushing flag bit to distinguish the back-flushed entry, so that repeated back flushing is avoided, and the loss of flash memory blocks is reduced. And the cache searching unit can quickly locate the mapping table entry from the physical address which is flushed back to the logical address, thereby avoiding repeated flushing and quickening the reconstruction of the mapping table. Meanwhile, the caching unit can quickly clear the refresh flag bits of all the entries, thereby being beneficial to refreshing the entries of the mapping table from the physical address to the logical address and accelerating the reconstruction of the mapping table. The method for reconstructing the mapping table can reconstruct the mapping table and greatly accelerate the reconstruction efficiency of the mapping table.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of a data storage device according to the present application.
Fig. 2 is a structural diagram of a mapping table from a physical address to a logical address in the present application.
FIG. 3 is a diagram of a physical address to logical address data structure, and a physical address to logical address data structure and a physical address to logical address mapping table according to the present application.
Fig. 4 is a structure diagram of a mapping table of physical addresses to logical addresses configured backwards in the mapping table of physical addresses to logical addresses whose operation types are flushed back in the present application.
Fig. 5 is a schematic diagram illustrating a cache search unit searching for an entry of a mapping table from a physical address to a logical address that needs to be flushed back in the present application.
FIG. 6 is a diagram illustrating a cache search unit searching for entries that quickly locate a mapping table of physical addresses marked with a refresh flag bit to logical addresses according to the present application.
Fig. 7 is a schematic diagram of the cache value unit clearing all entries marked with the refresh flag bits in the physical address to logical address mapping table according to the present application.
Fig. 8 is a flowchart of a mapping table reconstructing method according to the present application.
FIG. 9 is a flowchart illustrating a reconstruction process of a logical address to physical address mapping table according to the present application.
FIG. 10 is a flowchart of clearing the flush back flag bits of all entries in the mapping table from physical address to logical address in the cache according to the present application.
FIG. 11 is a flow chart illustrating the operation of the present application for flushing back a flag bit for a physical address to logical address mapping table tag to be flushed back.
FIG. 12 is a flowchart illustrating the process of flushing all physical address to logical address mapping tables in the cache according to the present application.
FIG. 13 is a flowchart of the present application using a cache search unit to search all mapping tables from physical address to logical address to be flushed back for the remaining entries belonging to the mapping table from logical address to physical address.
FIG. 14 is a flowchart illustrating rebuilding of a physical address to logical address mapping table in a cache according to the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a data storage device 100 is connected to a host 200 (e.g., an information processing apparatus) via an interface and a power line. The host 200 is configured by, for example, a personal computer, a CPU core, a server connected to a network, or the like. The host 200 performs data access control on the data storage device 100, for example, by sending a write request, a read request, and a delete request to the data storage device 100, performing writing, reading, and deleting of data to the data storage device 100.
Referring to fig. 1, in an embodiment of the invention, the data storage device 100 may be, for example, a Solid State Disk (SSD). And the data storage device 100 may include a controller 110 and a nonvolatile memory unit 120. The nonvolatile memory cell 120 is a nonvolatile memory cell 120 (non-transitory memory) that does not lose data even when power is cut off, and the nonvolatile memory cell 120 may be a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a Resistive Random Access Memory (RRAM), a phase change memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or a spin transfer torque random access memory (STT-RAM). The nonvolatile memory cell 120 may include a memory cell array block connected to word lines, string select lines, ground select lines, and bit lines. Non-volatile memory unit 120 may include a super block that includes a plurality of memory blocks. The plurality of memory blocks may include a plurality of pages. The nonvolatile memory unit 120 may include a two-dimensional (2D) memory array block or a three-dimensional (3D) memory array block. Other types of non-volatile memory cells 120 may also be used. In this embodiment, a structure of a NAND flash memory is described as an example, and it is to be understood that in other embodiments, other types of nonvolatile memory cell 120 structures may be employed.
Referring to fig. 1, in one embodiment of the present invention, the nonvolatile memory unit 120 is electrically connected to the memory controller 202 and is used for storing data written by the host 200. The nonvolatile memory unit 120 has a flash block therein. The flash blocks may belong to the same memory die (die) or to different memory dies. Each flash block has a plurality of physical pages, and each physical page has at least one physical sector, wherein the physical pages belonging to the same flash block can be independently written and simultaneously erased. For example, each flash block is composed of 128 physical pages, and each physical page has 8 physical sectors (sectors). That is, in the example of 512 bytes per physical sector, the capacity of each physical page is 4 kilobytes (K). However, in one embodiment, each flash block may be made up of 64 physical pages, 256 physical pages, or any other number of physical pages.
Referring to FIG. 2, a flash block (block) is the minimum unit of erase. That is, each flash block contains the minimum number of memory cells that are erased together. The physical page is the smallest unit that is programmable. That is, the physical page is the smallest unit of written data. However, in some embodiments, the minimum unit of write data may also be a physical sector or other size. Each physical page typically includes a data bit region and a redundant bit region. The data bit region is used for storing user data, and the redundant bit region is used for storing system data (such as error checking and correcting codes).
Referring to fig. 1, in an embodiment of the invention, the nonvolatile memory unit 120 is a Multi-Level Cell (MLC) NAND flash memory module. In other embodiments, the non-volatile memory unit 120 may be a Single Level Cell (SLC) NAND flash memory module, other flash memory modules, or other memory modules with the same characteristics.
Referring to fig. 1, in an embodiment of the invention, a system flash block 121, a logical address to physical address flash block (L2P block) 122, a data flash block 123 and other flash blocks 124 are disposed in a nonvolatile memory unit 120.
Referring to fig. 1, in an embodiment of the present invention, a logical address to physical address (L2P) mapping table is stored in the logical address to physical address flash memory area 122, and each logical address to physical address mapping table stores a physical address corresponding to each logical address.
Referring to fig. 1, in an embodiment of the present invention, user data is stored in the data flash area 123. The flash memory block in each data flash area 123 may be divided into a plurality of blocks (banks), and a physical address to logical address mapping table is stored at the end of each block, and each physical address to logical address mapping table records a logical address of each 4K physical page in a block (bank). Physical address to logical address mapping table as shown in fig. 2, each physical address to logical address mapping table includes a plurality of entries, each entry including a logical address and a flush flag bit (flush bit). The flushing flag bit is used for judging whether the logical address of the corresponding entry is flushed back to the mapping table from the logical address to the physical address, so that reconstruction of the mapping table can be assisted. For example, when the flush back flag bit is 1, it indicates that the flush back flag bit exists and the logical address corresponding to the entry has been flushed back to the logical address to physical address mapping table, and when the flush back flag bit is zero, it indicates that the flush back flag bit does not exist and the logical address corresponding to the entry has not been flushed back to the logical address to physical address mapping table.
Referring to FIG. 1, in some embodiments, metadata (meta data) is appended to every 4K physical page, and the metadata includes the logical address of the 4K page.
Referring to FIG. 1, in one embodiment of the present invention, a physical address to logical address mapping table, a physical address to logical address data structure, a logical address to physical address table and other necessary data are backed up in the system flash area 121. The physical address-to-logical address mapping table is in one-to-one correspondence with the physical address-to-logical address data structure, and the physical address-to-logical address data structure records the state of the physical address-to-logical address mapping table. Each physical address to logical address mapping table needs to be flushed back into the logical address to physical address mapping table. The logical address to physical address record table records the physical address of each logical address to physical address mapping table. The logical address-to-physical address recording table records the physical address of each logical address-to-physical address mapping table. When reading the logical address to physical address record table from the system flash area 121, it can know where the logical address to physical address flash area 122 exists in the last time of the logical address to physical address mapping table.
Referring to fig. 1, in an embodiment of the invention, data is stored in the other flash memory region 124.
Referring to fig. 1, in an embodiment of the invention, a buffer 111 is disposed in the controller 110, and the buffer 111 may be a volatile memory capable of writing or reading data at a high speed, such as a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a latch, a flip-flop, or a register. When the mapping table is rebuilt, most of the cache 111 is configured to be used as a rebuilt mapping table, and when the rebuilding of the mapping table is completed, the cache 111 is released for reading and writing, so that the rebuilding rate of the mapping table is increased.
Referring to fig. 1, in an embodiment of the present invention, when the data storage device operates, the cache 111 stores a mapping table therein. The mapping tables include a most recent logical address to physical address mapping table, a physical address to logical address mapping table, and a physical address to logical address data structure.
Referring to fig. 1, in an embodiment of the present invention, a first cache is configured in the cache 111, and the latest mapping table from the logical address to the physical address is stored in the first cache. The cache 111 is configured with a second cache, wherein the second cache stores the latest mapping table from physical address to logical address, and the mapping table from physical address to logical address is configured corresponding to the data structure from physical address to logical address. As shown in FIG. 3, the second cache includes both an update and a flush back of the physical address to logical address mapping table and the physical address to logical address data structure. Each physical address to logical address data structure includes a physical address to logical address mapping table pointer, block (bank) information, flash block (block) information, a physical address to logical address mapping table index, and an operation type (op). The physical address-to-logical address mapping table pointer points to a corresponding physical address-to-logical address mapping table, the block information and the flash memory block information respectively represent a block and a flash memory block to which the corresponding physical address-to-logical address mapping table belongs, the physical address-to-logical address mapping table index represents an index of an entry in the physical address-to-logical address mapping table which is about to be operated, and the operation type (op) represents that the corresponding physical address-to-logical address mapping table is in an update operation state or a refresh operation state.
Referring to fig. 4, in some embodiments, when the operation type corresponding to the physical address to logical address mapping table is a refresh operation, a sufficient second cache is configured behind the physical address to logical address mapping table to accommodate the physical address to logical address mapping tables on all blocks, so as to perform the refresh operation of all the physical address to logical address mapping tables synchronously, thereby speeding up the rebuilding of the mapping tables.
Referring to fig. 1, in an embodiment of the present invention, a cache search unit 112 is further configured on the controller for fast searching data in the cache 111. The value to be searched, the search address, the search length, and the bit mask may be set in the cache search unit 112. The setting of the bit mask may ignore the specified bits when searching. As shown in fig. 5, the cache search unit 112 may be used in mapping table rebuilding, and when the logical address to physical address mapping table is updated by using the flushed physical address to logical address mapping table, all entries of the physical address to logical address that need to be flushed back to the logical address to physical address mapping table may be quickly found, so as to speed up the rebuilding of the mapping table. As shown in fig. 6, the cache search unit 112 may also be used in the mapping table rebuilding and the preparation step of mapping table flushing from the physical address to the logical address, and the cache search unit 112 may quickly locate the flushed entry marked with the flushing flag bit, so as to avoid repeated flushing and accelerate the speed of rebuilding the mapping table.
Referring to fig. 1 and fig. 8, in an embodiment of the present invention, a buffer setting unit 113 is further configured on the controller for setting a value on the buffer 111 quickly. The preset value, address, length and bit mask may be set by the cache set unit 113, and the bit mask may be set to skip the designated bits when setting the value. In the reconstruction of the mapping table, in the preparation step of the physical address to logical address mapping table refresh, the refresh flag bits of all entries in the physical address to logical address mapping table need to be cleared quickly to speed up the reconstruction of the mapping table.
As shown in fig. 1, the controller 110 is further provided with another unit 114, and the other unit 114 can perform functions such as garbage collection and wear leveling on the nonvolatile memory unit 120, for example.
Referring to fig. 1 to fig. 2 and fig. 8, a data storage device 100 provided by the present invention is a computer-readable storage device, and a computer program is stored on the data storage device 100, and when the computer program is executed by a processor, the computer program implements the method for reconstructing the mapping table according to the present invention. The method for reconstructing the mapping table provided by the invention comprises the following steps S101 to S107.
And S101, initializing a cache.
S102, configuring a first cache in the cache, and storing a mapping table from a logical address to a physical address when the mapping table is reconstructed.
S103, configuring a second cache in the cache, and storing a mapping table from the physical address to the logical address when the mapping table is reconstructed.
And S104, reconstructing the mapping table.
S105, withdrawing part of the first cache, and reserving part of the first cache to store the reconstructed logical address-to-physical address mapping table.
S106, a part of the second cache is reclaimed, and a reserved part of the second cache stores the reconstructed physical address-to-logical address mapping table.
And S107, using the recycled first cache and the recycled second cache as reading and writing of data and other functions.
Referring to fig. 8, in an embodiment of the invention, a data structure of the management cache is set when the cache is initialized. Before the mapping table is rebuilt, most of the caches 111 in the controller are configured as a first cache and a second cache, and are used for storing a mapping table from a physical address to a logical address and a mapping table from a logical address to a physical address, so that the rebuilding speed of the mapping table is accelerated. After the mapping table is rebuilt, the first cache and the second cache except the physical address to logical address mapping table and the logical address to physical address mapping table after the rebuilding are released, most of the caches 111 are used for reading and writing functions of the storage device, and the working performance of the storage device is guaranteed. In the application, the rebuilding of the mapping table comprises rebuilding of a mapping table from a logical address to a physical address and rebuilding of a mapping table from a physical address to a logical address, and the rebuilding of the mapping table from the logical address to the physical address is firstly carried out, and then the rebuilding of the mapping table from the physical address to the logical address is carried out.
Referring to fig. 9, in an embodiment of the invention, rebuilding the mapping table from the logical address to the physical address in the cache 111 includes steps S201 to S212.
S201, reading a logical address to physical address recording table in a system flash memory area to obtain physical addresses of each logical address to physical address mapping table.
S202, reading the mapping table from physical address to logical address and the corresponding data structure from physical address to logical address in the system flash memory.
S203, judging whether the flash block information in the data structure from the physical address to the logical address, the operation type of which is flushed back, in the cache is a valid value, if so, executing the step S207, otherwise, executing the step S204.
S204, judging whether the operation type in the cache is the flash block information from the updated physical address to the logical address data structure is a valid value, if so, executing the step S205, otherwise, executing the step S212.
In the present application, the operation type in the physical address to logical address data structure corresponding to the physical address to logical address mapping table includes an update state and a refresh state, the physical address to logical address mapping table in the update state is updated after the physical address to logical address mapping table in the refresh state is updated than the physical address to logical address mapping table in the refresh state, and when the physical address to logical address mapping table is refreshed, the physical address to logical address mapping table is refreshed from the physical address to logical address mapping table updated first. When the mapping table is rebuilt, whether the flash block information in the data structure of the physical address to the logical address with the operation type of being refreshed back is an effective value is judged firstly, and if the flash block information in the data structure of the physical address to the logical address with the operation type of being refreshed back is an effective value, the mapping table of the physical address to the logical address corresponding to the data structure of the physical address to the logical address is refreshed back. If the operation type is that the flash memory block information in the physical address to logical address data structure which is refreshed back is an invalid value, then whether the flash memory block information in the physical address to logical address data structure which is updated in the operation type is an valid value is judged, if the flash memory block information in the physical address to logical address data structure which is updated in the operation type is an valid value, then a mapping table from the physical address to the logical address corresponding to the physical address to logical address data structure is refreshed back, and if the flash memory block information in the physical address to logical address data structure which is updated in the operation type is also an invalid value, then the mapping table from the physical address to the logical address in the cache 111 does not need to be rebuilt.
S205, reading the mapping table from the physical address to the logical address of the corresponding block in the flash memory block in the data structure from the physical address to the logical address with the operation type updated, covering the mapping table from the physical address to the logical address with the operation type refreshed in the cache, and initializing the flash memory block information and the block information corresponding to the mapping table from the physical address to the logical address into the data structure from the physical address to the logical address with the operation type refreshed in the cache.
S206, clearing the back flushing flag bits of all the entries in the mapping table from the physical address to the logical address in the cache.
S207, reading all physical address to logical address mapping tables in the rest blocks of the flash memory block in the data flash memory area, sequentially placing the physical address to logical address mapping tables with the operation types of being refreshed back in the cache, and identifying the physical address to logical address mapping tables with the operation types of being refreshed back in the cache and the subsequent physical address to logical address mapping tables as states to be refreshed back.
S208, judging whether the content corresponding to the mapping table from all the physical addresses to be flushed back to the logical addresses in the cache is empty or not. If so, go to step S212, otherwise go to step S209.
S209, clearing the refresh flag bits of all the entries in the physical address to logical address mapping table with the operation type of refresh and all the following physical address to logical address mapping tables.
S210, in the mapping table from the physical address to the logical address to be refreshed, the flash memory block information and the block information are the same as those from the physical address to the logical address with the operation type being updated, and the flag bit is marked to be refreshed. The marked entry position needs to be the same as the mapping table from the physical address to the logical address, the operation type of which is updated.
In some embodiments, as shown in steps S205 to S210, before all physical address to logical address mapping tables are flushed back, the flushing flag bits of all entries in all physical address to logical address mapping tables that need to be flushed back need to be cleared, so as to facilitate the flushing back of the physical address to logical address mapping tables, but the physical address to logical address mapping tables whose operation types read by the system flash area 121 are flushed back need to be excluded. The cache unit 113 may be utilized to flush multiple physical to logical address mapping tables simultaneously.
In some embodiments, as shown in steps S205 to S210, before all the physical address to logical address mapping tables are flushed, it is necessary to determine whether the flash memory block and the block to which the physical address to logical address mapping table belongs are the same as the physical address to logical address mapping table whose operation type is updated. If the operation type is the same, the entry marked with the refresh back flag bit in the mapping table from the updated physical address to the logical address is required to be marked with the refresh back flag bit according to the operation type so as to avoid the repeated refresh back of the entry. Cache search unit 112 may be utilized to quickly find all entries marked with the swiped-back flag.
S211, synchronously refreshing all the mapping tables from the physical address to the logical address in the cache.
In some embodiments, when a physical address to logical address mapping table is flushed back, physical address to logical address mapping table entries belonging to the same logical address to physical address mapping table can be quickly found out from multiple physical address to logical address mapping tables.
S212, the reconstruction of the mapping table from the logical address to the physical address is completed, and the last flash memory block and the next block of the last block participating in the reconstruction of the mapping table from the logical address to the physical address are output.
In some embodiments, after the rebuilding of the logical address to physical address mapping table is completed, the flash block and the next block of the last block participating in the rebuilding of the logical address to physical address mapping table are output, and the physical address to logical address mapping table is rebuilt according to the flash block and the block.
As shown in fig. 10, when step S206 and step 209 are executed, step S301 to step S304 are specifically included.
S301, setting a bit mask in the cache value setting unit to clear all the back-flushing flag bits.
And S302, setting the preset value in the cache value setting unit to be zero.
S303, setting the address length in the cache value setting unit to be all the range of the back-flushing flag bits needing to be cleared.
S304, starting a cache value setting unit, and clearing the refresh zone bits of all the entries in the required range.
As shown in fig. 11, when step S210 is executed, step S401 to step S405 are specifically included.
S401, bit masks are set in the cache searching unit, and the bit masks are compared and flag bits are refreshed.
S402, setting a search value in the cache search unit, wherein the search value is a refresh flag bit.
S403, starting a cache searching unit, and finding out all entries marked with the refresh flag bit in the mapping table from the physical address to the logical address with the operation type being updated.
S404, acquiring an address block table according to the search result.
S405, according to the address block table, marking a back-flushing flag bit in the corresponding entry of the mapping table from the target physical address to the logical address.
As shown in fig. 12, when step S211 is executed, step S501 to step S505 are specifically included.
S501, judging whether a physical address to logical address entry corresponding to the physical address to logical address mapping table index is marked as a refresh flag bit, if so, executing a step S505, otherwise, executing a step S502.
S502, reading the mapping table from the physical address to the logical address of the logical address entry and storing the mapping table in a first cache.
S503, using the cache searching unit to search the mapping table of all physical addresses to logical addresses to be flushed back for the rest entries belonging to the mapping table of the logical addresses to the physical addresses.
S504, all the physical address to logical address entries belonging to the logical address to physical address mapping table are flushed back to the logical address to physical address mapping table, and the flushed physical address to logical address entry marks are flushed back to the flag bits.
And S505, increasing the index of the mapping table from the physical address to the logical address by one.
S506, judging whether the index of the mapping table from the physical address to the logical address reaches the end of the mapping table from the last physical address to the logical address, if so, ending the process, and if not, returning to the step S501.
As shown in fig. 13, when step S503 is executed, step S601 to step S604 are specifically included.
S601, setting data pre-searched in a cache search unit as physical address to logical address entries.
S602, setting a bit mask in a cache searching unit, and only displaying the position information of the mapping table from the logical address to the physical address.
And S603, starting a cache searching unit.
And S604, accessing the search result.
In an embodiment of the present invention, the rebuilding the mapping table from the physical address to the logical address in the cache includes steps S701 to S709.
S701, acquiring the flash memory block information and the block information output by the mapping table from the reconstructed logical address to the physical address.
S702, judging whether the flash memory block corresponding to the flash memory block information is valid, if so, executing the step S703, otherwise, executing the step S704.
S703, determining whether the block exceeds the total number of blocks, if yes, performing S704, otherwise performing S705.
S704, resetting the mapping table from physical address to logical address and the data structure from physical address to logical address to be in the no data state. And step S706 is executed to complete the rebuilding of the physical address to logical address mapping table.
S705, judging whether the flash block information and the block information have the same data structure from the physical address to the logical address with the operation type being updated, if so, executing step S707, otherwise, executing steps S708 and 709 in sequence, and then executing step S707.
S707, judging whether the index of the mapping table from the physical address to the logical address points to the end of the mapping table from the physical address to the logical address, if so, executing the step S706, otherwise, executing the step S710.
S708, resetting the physical address to logical address mapping table and the physical address to logical address data structure to be in a no data state.
S709, initializing the physical address to logical address data structure with the flash block information and the block information.
S710, reading a page corresponding to the index of the mapping table from the physical address to the logical address in the data flash area.
And S711, judging whether the content in the page is empty, if so, executing the step S706, otherwise, executing the step S712 and returning to the step S707.
S712, the physical address to logical address mapping table is updated with the logical address in the metadata of the page, and the index of the physical address to logical address mapping table is increased accordingly.
In some embodiments, the output flash block information and block information are reconstructed from the logical address to physical address mapping table to determine the physical address to logical address mapping table to be reconstructed. And for rebuilding the mapping table from physical address to logical address, using the second cache and the physical address to logical address data structure whose operation type is updated.
In some embodiments, if the flash block is invalid, it is determined that no physical address to logical address mapping table needs to be rebuilt, and the physical address to logical address mapping table and the physical address to logical address data structure are reset to a no-data state.
In some embodiments, if the flash block is valid, but the block exceeds the total number of blocks, it is determined that no physical address to logical address mapping table needs to be rebuilt, and the physical address to logical address mapping table and the physical address to logical address data structure are reset to a no data state.
In some embodiments, if the flash block is a valid value and the total number of blocks is not exceeded, a physical address to logical address mapping table reconstruction is required.
Before rebuilding the mapping table from physical address to logical address, it is necessary to determine whether the flash block information and the block information are both the same as the mapping table from physical address to logical address whose operation type is updated. If the difference is the same, directly rebuilding, and continuing the progress before power failure. If not, the operation type is reset to be the state of no data of the updated physical address to logical address mapping table and the physical address to logical address data structure, then the physical address to logical address data structure is initialized by the flash block information and the block information, and then the physical address to logical address mapping table is rebuilt.
The reconstruction of the physical address to logical address mapping table is performed by reading the metadata of the pages in the data flash from old to new until a page with blank contents is encountered or the end of the flash block is reached. After reading the metadata of the page, updating the mapping table from the physical address to the logical address by using the logical address in the metadata, and increasing the index value of the mapping table from the physical address to the logical address. When the flash memory block information and the block information are the same as the data structure of the physical address to the logical address with the operation type of updating, reading a page corresponding to the index of the physical address to the logical address mapping table in the data flash memory area, updating the physical address to the logical address mapping table by the logical address in the metadata of the page, and continuing the index forward until an empty page is read or the end of the mapping table is read; when the flash memory block information and the block information are different from the physical address to logical address data structure with the operation type of updating, resetting the physical address to logical address mapping table and the physical address to logical address data structure to be in a no-data state, initializing the physical address to logical address data structure by using the flash memory block information and the block information, reading a page corresponding to the index of the physical address to logical address mapping table in the data flash memory area, updating the physical address to logical address mapping table by using the logical address in the metadata of the page, and continuously advancing the index until reading an empty page or the end of the mapping table.
In summary, in the method for reconstructing a mapping table according to the present invention, before reconstructing the mapping table, the first cache and the second cache are configured in the controller to reconstruct the mapping table from the logical address to the physical address and the mapping table from the physical address to the logical address. When the mapping table is rebuilt, the mapping table from the logical address to the physical address is rebuilt first, and then the mapping table from the physical address to the logical address is rebuilt according to the flash memory block and the block output by the rebuilt mapping table from the logical address to the physical address.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (15)
1. A method for reconstructing a mapping table, comprising at least the steps of:
configuring a first cache and a second cache in a controller, wherein the first cache stores a mapping table from a logical address to a physical address during reconstruction, and the second cache stores the mapping table from the physical address to the logical address during reconstruction;
rebuilding the mapping table from the logical address to the physical address, and outputting a flash memory block and a next block of a last block participating in the rebuilding of the mapping table from the logical address to the physical address;
rebuilding the mapping table from the physical address to the logical address according to the rebuilt mapping table from the logical address to the physical address and the output flash memory block and block; and
and reserving part of the first cache and part of the second cache which store the reconstructed logical address-to-physical address mapping table and the reconstructed physical address-to-logical address mapping table, and releasing other first caches and other second caches.
2. The method for rebuilding a mapping table according to claim 1, comprising the following steps when rebuilding a logical address to physical address mapping table:
reading a logical address to physical address record table in a system flash memory area to obtain physical addresses of each logical address to physical address mapping table; and
a physical address to logical address mapping table and corresponding physical address to logical address data structures are read in a system flash memory.
3. The method for rebuilding mapping table of claim 1, wherein when rebuilding a logical address to physical address mapping table, the method comprises the following steps:
judging whether the flash block information in the logical address data structure from the physical address with the operation type of being flushed back in the cache is a valid value or not; and
determining whether the flash block information in the data structure of the physical address to logical address whose operation type is updated in the cache is valid.
4. The method for reconstructing a mapping table according to claim 3, wherein when reconstructing a logical address to physical address mapping table, the method comprises the following steps:
when the operation type is that the flash memory block information in the data structure from the physical address to the logical address which is flushed back is an invalid value, and the operation type is that the flash memory block information in the data structure from the physical address to the logical address which is updated is an invalid value, the mapping table from the logical address to the physical address does not need to be rebuilt.
5. The method for reconstructing a mapping table according to claim 3, wherein when reconstructing a logical address to physical address mapping table, the method comprises the following steps:
when the operation type is that the flash memory block information from the refreshed physical address to the logical address data structure is an invalid value, and the operation type is that the flash memory block information from the updated physical address to the logical address data structure is an effective value;
reading a mapping table from a physical address to a logical address of a corresponding block in a flash memory block in a data structure with an updated physical address to logical address, covering the mapping table from the physical address to the logical address with the read mapping table from the physical address to the logical address, and initializing the mapping table from the flash memory block information and the block information corresponding to the mapping table from the physical address to the logical address into the data structure from the physical address to the logical address with the operation type of the flash memory block and the block information; and
and clearing the back flushing flag bits of all the entries in the mapping table from the physical address to the logical address in the cache.
6. The method for rebuilding a mapping table according to claim 5, comprising the following steps when rebuilding a logical address to physical address mapping table:
when the operation type is the flash memory block information in the data structure of the physical address to the logical address which is flushed back is the effective value, reading all physical address to logical address mapping tables in the rest blocks of the flash memory block in the data flash memory area, and sequentially placing the mapping tables in a cache after the operation type is the physical address to the logical address which is flushed back, and identifying the physical address to the logical address mapping table which is flushed back and the physical address to the logical address mapping table which follows the mapping table as the state to be flushed back.
7. The method for rebuilding mapping table of claim 6, further comprising the following steps when rebuilding a logical address to physical address mapping table:
judging whether the corresponding content of all mapping tables of the physical address to the logical address to be refreshed in the cache is empty, if so, indicating that the rebuilding of the mapping tables of the logical address to the physical address is completed, outputting a final flash memory block and a block, and if not, clearing the refreshing flag bits of all the entries in the mapping tables of the physical address to the logical address and all the subsequent mapping tables of the physical address to the logical address, wherein the operation types of the refreshing flag bits are refreshing;
in the mapping table from the physical address to the logical address to be refreshed, the flash memory block information and the block information are the same as those from the physical address to the logical address table with the operation type being updated, and the flag bit is marked to be refreshed; and
and synchronously brushing all physical address to logical address mapping tables in the cache.
8. The method of rebuilding mapping table of claim 7, wherein clearing the flush back flag bits of all entries in the physical address to logical address mapping table comprises the steps of:
setting a bit mask in the cache value setting unit to clear all the back-flushing flag bits;
setting the preset value in the cache value setting unit to be zero;
setting the address length in the cache value setting unit as all the range of the back-flushing flag bits needing to be cleared; and
and starting a cache value setting unit, and clearing the back-flushing flag bits of all the entries in the required range.
9. The method for reconstructing a mapping table according to claim 1, wherein the step of flushing the flag bit back to the mapping table flag of the physical address to logical address to be flushed comprises the following steps:
setting a bit mask in a cache searching unit, and comparing the bit mask and brushing back a flag bit;
setting a search value in a cache search unit, wherein the search value is a refresh flag bit;
starting a cache searching unit, and finding out all items marked with the refresh flag bit in a mapping table from the physical address to the logical address with the operation type of updating;
acquiring an address block table according to the search result; and
and marking a back flushing flag bit in the corresponding entry of the mapping table from the target physical address to the logical address according to the address block table.
10. The method for reconstructing a mapping table according to claim 1, wherein synchronizing the flushing back of all the physical address to logical address mapping tables in the cache comprises the following steps:
judging whether the physical address to logical address entry corresponding to the physical address to logical address mapping table index is marked as a back-flushing flag bit;
reading a logical address-to-physical address mapping table from the physical address to the logical address entry and storing the mapping table in a first cache;
searching other items belonging to the mapping table from the logical address to the physical address by using a cache searching unit in all the mapping tables from the physical address to the logical address to be flushed back;
and flushing all physical address to logical address entries belonging to the logical address to physical address mapping table back to the logical address to physical address mapping table, and flushing the marks of the flushed physical address to logical address entries back to the flag bits.
11. The mapping table rebuilding method of claim 10, wherein using the cache search unit to search all physical address to logical address mapping tables to be flushed back for the remaining entries belonging to the logical address to physical address mapping table comprises the following steps:
setting data pre-searched in a cache search unit as physical address to logical address entries;
setting a bit mask in a cache searching unit, and only displaying the position information of a mapping table from a logical address to a physical address; and
and starting a cache search unit and storing the search result.
12. The method for rebuilding a mapping table according to claim 1, comprising the following steps when rebuilding a physical address to logical address mapping table:
acquiring flash block information and block information output by a mapping table from a reconstructed logical address to a physical address; and
and judging whether the flash memory block corresponding to the flash memory block information is valid or not and judging whether the block exceeds the total block number or not.
13. The method for rebuilding mapping table of claim 12, wherein when rebuilding a physical address to logical address mapping table, the method comprises the following steps:
when the flash memory block corresponding to the flash memory block information is invalid, or the flash memory block corresponding to the flash memory block information is valid and the block exceeds the total block number;
then, the physical address to logical address mapping table and the physical address to logical address data structure are reset to be in a no-data state, and the reconstruction of the physical address to logical address mapping table is completed.
14. The method for reconstructing a mapping table according to claim 12, wherein when the flash block corresponding to the flash block information is valid and the block does not exceed the total number of blocks when reconstructing the physical address to logical address mapping table, the method further comprises the following steps:
judging whether the flash memory block information and the block information have the same data structure from the physical address to the logical address with the operation type of updating, if so, reading a page corresponding to the index from the physical address to the logical address mapping table in the data flash memory area, updating the physical address to the logical address mapping table by the logical address in the metadata of the page, and continuing the index forward until an empty page is read or the tail end of the mapping table is read; if not, resetting the mapping table from the physical address to the logical address and the data structure from the physical address to the logical address to be in a no-data state, initializing the data structure from the physical address to the logical address by using the flash block information and the block information, reading a page corresponding to the index from the mapping table from the physical address to the logical address in the data flash memory area, updating the mapping table from the physical address to the logical address by using the logical address in the metadata of the page, and continuing the index until an empty page is read or the tail end of the mapping table is read.
15. A data storage device, characterized in that a computer program is stored on the data storage device, which computer program, when being executed by a processor, carries out the method for reconstructing a mapping table according to claim 1.
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