CN115562801A - Multi-CPU architecture virtual machine PCI bus address management method and device - Google Patents

Multi-CPU architecture virtual machine PCI bus address management method and device Download PDF

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Publication number
CN115562801A
CN115562801A CN202211117272.0A CN202211117272A CN115562801A CN 115562801 A CN115562801 A CN 115562801A CN 202211117272 A CN202211117272 A CN 202211117272A CN 115562801 A CN115562801 A CN 115562801A
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China
Prior art keywords
pci
virtual
pci bus
address
bus
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CN202211117272.0A
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Chinese (zh)
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张友加
罗海俊
李磊
卢亮军
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CLP Cloud Digital Intelligence Technology Co Ltd
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CLP Cloud Digital Intelligence Technology Co Ltd
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Priority to CN202211117272.0A priority Critical patent/CN115562801A/en
Publication of CN115562801A publication Critical patent/CN115562801A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45595—Network integration; Enabling network access in virtual machine instances
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)

Abstract

The application discloses a method and a device for managing PCI bus addresses of a virtual machine with multiple CPU architectures, wherein the method comprises the following steps: configuring primary PCI bus addresses of continuous first address bits into PCI bridge devices, wherein any one PCI bridge device corresponds to one secondary PCI bus so as to access the corresponding virtual PCI device through the secondary PCI bus under the PCI bridge device, and no secondary PCI bridge device is mounted under any secondary PCI bus; configuring a primary PCI bus address of consecutive second address bits as a virtual mount onboard PCI device, wherein the second address bits are non-overlapping with the first address bits. According to the embodiment of the application, the virtual devices are allocated to the appointed PCI address range according to different types of the virtual devices, the PCI address range is fully utilized, the shortage of PCI device numbers is avoided, and the manageability of the virtual devices and the expandability of the bus are improved.

Description

Multi-CPU architecture virtual machine PCI bus address management method and device
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for managing PCI bus addresses of a virtual machine with multiple CPU architectures.
Background
In some scenarios implemented using QEMU and KVM as virtual machines, the virtual machine management tool implements various configurations of the virtual machines by calling the management interface provided by the libvirtual irt.
For the i440fx virtual machine type, it only supports the PCI bus. For an i1440fx type virtual machine, the typical LIBVIRT will have a PCI interface type virtual hardware device on PCI bus 0 of that type of virtual machine. Since only a maximum of 32 devices can be hung on PCI bus 0, this results in no available device numbers if more PCI device insertions are required. Although this situation can be solved by hot-plugging a PCI bridge device, the bus number of the PCI bridge device that is dynamically hot-plugged will be different after the virtual machine is restarted than before the virtual machine is restarted, which may cause problems for applications that rely on the PCI bus number.
The Q35 virtual machine type for the X86_64 architecture, which supports only PCIE buses. For this type of virtual machine, the root bus of PCIE does not support hot plug. In the creation phase of the virtual machine, a plurality of PCIE Root ports are created in advance, and the PCIE Root ports are mounted on a PCIE Root bus. Then the LIBVIRT mounts the devices of the virtual machine to the pre-established PCIE Root ports, and starts the virtual machine through QEMU. Because the number of PCIE Root ports created in the virtual machine creation phase is limited and part of the PCIE Root ports is already occupied by the virtual machine device in the startup phase, the virtual machine device available for dynamic hot plug is limited, and thus, no PCI device number is available when the virtual device is newly inserted. Similar to i1440fx, this problem can also be solved by inserting a PCIE-to-PCI bridge device on a PCIE RootPort, but similarly, the bus number of the dynamically hot-inserted PCI bridge device is different before and after the virtual machine is restarted.
In the current method, the virtual machine management component does not realize the allocation of the PCI bus address of the virtual machine, which can cause the problems of waste of the PCI bus address space, insufficient PCI address of the virtual device, abnormal change of the PCI address of the virtual device and the like.
Disclosure of Invention
The embodiment of the application provides a method and equipment for managing PCI bus addresses of a virtual machine with a multi-CPU architecture, which are used for allocating the virtual devices to a specified PCI address range according to different types of the virtual devices, fully utilizing the PCI address range, avoiding the insufficient number of the PCI devices and improving the manageability of the virtual devices and the expandability of the buses.
The embodiment of the application provides a PCI bus address management method for a virtual machine with multiple CPU architectures, which comprises the following steps:
configuring primary PCI bus addresses of continuous first address bits into PCI bridge devices, wherein any one PCI bridge device corresponds to one secondary PCI bus so as to access the corresponding virtual PCI device through the secondary PCI bus under the PCI bridge device, and no secondary PCI bridge device is mounted under any secondary PCI bus;
configuring a PCI bus address of consecutive second address bits as a virtual mount onboard PCI device, wherein the second address bits are non-overlapping with the first address bits.
Optionally, setting the PCI functions of the primary PCI bus to 0; and
also included are setting the PCI functions of the secondary PCI bus to all 0 s.
Optionally, configuring a primary PCI bus address of consecutive 12 address bits as a PCI bridge device;
the next consecutive 19 address bits of the primary PCI bus address are configured as a virtual mount on-board PCI device.
Optionally, accessing the corresponding virtual PCI device through the secondary PCI bus under the PCI bridge device includes:
and designating a third address bit which is continuous under any secondary PCI bus to access the same type of virtual PCI equipment.
Optionally, the method further comprises directly using or designating other device extensions for the unplanned secondary PCI bus address.
Optionally, the virtual PCI device accessed through the secondary PCI bus includes a virtual network card virtual-net device, a virtual network card virtual-blk device, a virtual network card virtual-sci device, a virtual network card e1000 device, a virtual network card vfio device, and a virtual network card vfio-user device.
An embodiment of the present application further provides a computer device, which includes a processor and a memory, where the memory stores a computer program, and when the computer program is executed by the processor, the computer program implements the steps of the foregoing method.
According to the embodiment of the application, the virtual devices are allocated to the appointed PCI address range according to different types of the virtual devices, the PCI address range is fully utilized, the shortage of PCI device numbers is avoided, and the manageability of the virtual devices and the expandability of the bus are improved.
The above description is only an overview of the technical solutions of the present application, and the present application may be implemented in accordance with the content of the description so as to make the technical means of the present application more clearly understood, and the detailed description of the present application will be given below in order to make the above and other objects, features, and advantages of the present application more clearly understood.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is an example of an I440fx PCI bus architecture based on X86_64 according to an embodiment of the present application;
fig. 2 is an example of an AARCH64 or X86_64 based Q35 PCI bus architecture according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
A Virtual Machine (Virtual Machine) refers to a complete computer system with complete hardware system functionality, operating in a completely isolated environment, emulated by software. An independent virtual operating system is run as a user space process in the host operating system using the physical hardware and computing resources of the host. Like physical machines, virtual machines also require specialized equipment to provide functions for the system, such as processing power, memory, storage, networking, or graphics.
The LIBVIRT is a set of virtualization management components, provides a management channel for configuring and managing the virtual machine for the upper layer virtualization management components, and converts the configuration information into the configuration of the bottom layer QEMU, so as to realize the configuration management of the virtual machine.
The KVM is software of a virtual machine monitor, and resources of a physical server can be separated from hardware and appropriately configured by the KVM so as to be used by a virtual machine. The KVM support realizes a virtual machine based on hardware enhancement in the architectures of X86_64, AARCH64 and the like. QEMU emulates a complete virtual hardware platform on which a guest operating system can run and manages how resources are allocated in the host and provided to the guest, QEMU provides the various IO devices such as storage, network or graphics for the virtual machine, and the PCI bus connecting these IO devices to the virtual machine.
PCI is a local bus technology that connects computer peripherals to a computer system. The PCI technology mainly includes two types, i.e., PCI and PCIE. They are all used to implement the connection of devices to a computer except that they use different technologies for the communication of devices on a bus.
The embodiment of the application provides a PCI bus address management method for a virtual machine with multiple CPU architectures, which comprises the following steps:
configuring primary PCI bus addresses of continuous first address bits into PCI bridge devices, wherein any one PCI bridge device corresponds to one secondary PCI bus so as to access the corresponding virtual PCI device through the secondary PCI bus under the PCI bridge device, and no secondary PCI bridge device is mounted under any secondary PCI bus;
configuring a PCI bus address of consecutive second address bits as a virtual mount onboard PCI device, wherein the second address bits are non-overlapping with the first address bits.
In some embodiments, further comprising setting the PCI functions of the primary PCI bus to 0 each; and further comprising setting the PCI functions of the secondary PCI bus to all 0 s.
In some embodiments, consecutive 12 address bits of a primary PCI bus address are configured as PCI bridge devices;
the next 19 consecutive address bits of the primary PCI bus address are configured to virtually mount the PCI on board device.
A specific application example is that a total of 32 devices can be hung under a PCI bus root bridge (primary PCI bus), and the PCI functions (numbers) are all set to 0. One exemplary configuration is that bus address 00:01.0 to 00:0c.0 is set as a PCI bridge device, for 12 PCI bridges, and bus address 00:0d.0 to 00:1f.0, for 19 PCI addresses, is used to virtually mount an onboard PCI device.
According to the embodiment of the application, the virtual devices are allocated to the appointed PCI address range according to different types of the virtual devices, the PCI address range is fully utilized, the shortage of PCI device numbers is avoided, and the manageability of the virtual devices and the expandability of the bus are improved.
In some embodiments, accessing the corresponding virtual PCI device through a secondary PCI bus under the PCI bridge device comprises:
and designating a third address bit which is continuous under any secondary PCI bus to access the same type of virtual PCI equipment.
In some embodiments, the virtual PCI devices accessed through the secondary PCI bus include virtual PC devices of the same type, such as a virtual network card virtual-net device, a virtual network card virtual-blk device, a virtual network card virtual-sci device, a virtual network card e1000 device, a virtual network card vfio device, and a virtual network card vfio-user device, and the same type of virtual PCI device supports at most 31 virtual PCI devices
In some embodiments, the method further comprises directly engaging in use or designating other device extensions for unplanned secondary PCI bus addresses.
As shown in fig. 1, an alternative application example is that, a PCI bus root bridge (primary PCI bus) bus address of 00.
The PCI bridge device is used to mount a device supporting dynamic hot plug, each PCI bridge device corresponds to a new PCI bus (secondary PCI bus), the virtual PCI device is directly mounted instead of other PCI bridge devices under the PCI bridge device, and the PCI function is designated as 0, 32 PCI devices can be mounted under each PCI (secondary PCI bus) bridge, and the following definitions can be implemented:
the PCI addresses defining bus addresses of 01.
The PCI address defining the bus address as 02.
The PCI addresses defining the bus addresses as 03.0 to 03 f.0 are used for the virtual network card virtio-scsi device.
PCI addresses defining bus addresses as 04:00.0 to 04:1f.0 are used for the virtual network card e1000 device.
The PCI addresses defining bus addresses of 05.
PCI addresses defining bus addresses of 06.
PCI addresses that have not yet been planned for use can be used directly, or for future expansion.
For virt (AARCH 64) and Q35 (X86 _ 64) virtual machine types that only support PCIE buses, a bus planning example proposed in this application is shown in fig. 2, a total of 31 PCIE Root Port devices may be below a PCIE bus Root bridge, and each PCI function is set to 0. Wherein, a PCIE Root Port device with a bus address 00. That is, corresponding to the case of PCIE Root Port, as shown in fig. 2, in this example, one PCIE to PCI bridge device is accessed to one PCIE Root Port address to form a primary PCI bus, so that a secondary PCI bus can be mounted under the primary PCI bus.
The PCI bridge devices are used for mounting devices supporting dynamic hot plug, each PCI bridge device corresponds to a new PCI bus (secondary PCI bus), other PCI bridge devices are not mounted under the PCI bridge devices, but virtual PCI devices are directly mounted, and the designated PCI function is 0. 31 PCI devices can be hung under each PCI bridge, and the following definitions can be implemented:
defining the bus address as 02.
The PCI address defining the bus address as 04.
The PCI addresses defining the bus addresses from 06.0 to 06.
The PCI address defining the bus address as 08.
PCI addresses, which define bus addresses 0 a.
The PCI address, which defines bus address 0c.
PCI addresses that have not yet been planned for use can be used directly, or for future expansion.
After the PCI bus configuration and the address allocation, the virtual PCI equipment on the PCI bridge supports hot plug. Different types of virtual PCI devices are located in different PCI address fields, so that the management of the virtual machine management component is facilitated. The virtual PCI devices of the same type are positioned on the same PCI bus, so that the devices of the same type are represented as continuous PCI addresses inside the virtual machine, the management of the devices inside the virtual machine is optimized, and the management component of the virtual machine is convenient to acquire the device information of the virtual machine and display report information.
An embodiment of the present application further provides a computer device, which includes a processor and a memory, where the memory stores a computer program, and the computer program, when executed by the processor, implements the steps of the foregoing method.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (7)

1. A multi-CPU architecture virtual machine PCI bus address management method is characterized by comprising the following steps:
configuring primary PCI bus addresses of continuous first address bits into PCI bridge devices, wherein any one PCI bridge device corresponds to one secondary PCI bus so as to access the corresponding virtual PCI device through the secondary PCI bus under the PCI bridge device, and no secondary PCI bridge device is mounted under any secondary PCI bus;
configuring a primary PCI bus address of consecutive second address bits as a virtual mount onboard PCI device, wherein the second address bits are non-overlapping with the first address bits.
2. The method of claim 1, further comprising setting the PCI functions of the primary PCI bus to 0; and
also included is setting the PCI functions of the secondary PCI bus to all 0's.
3. The multi-CPU architecture virtual machine PCI bus address management method of claim 1, wherein a primary PCI bus address of consecutive 12 address bits is configured as a PCI bridge device;
the next 19 consecutive address bits of the primary PCI bus address are configured to virtually mount the PCI on board device.
4. The method for managing the PCI bus address of a virtual machine of a multi-CPU architecture as claimed in claim 1, wherein accessing the corresponding virtual PCI device through a secondary PCI bus under the PCI bridge device comprises:
and designating a third address bit which is continuous under any secondary PCI bus to access the same type of virtual PCI equipment.
5. The method of claim 4, further comprising directly engaging in use or designating other device extensions for unplanned secondary PCI bus addresses.
6. The method for managing the PCI bus addresses of the virtual machine with multiple CPU architectures according to claim 4, wherein the virtual PCI devices accessed through the secondary PCI bus include a virtual network card virtual-net device, a virtual network card virtual-blk device, a virtual network card virtual-sci device, a virtual network card e1000 device, a virtual network card vfio device, and a virtual network card vfio-user device.
7. A computer arrangement, characterized by a processor and a memory, on which a computer program is stored which, when being executed by the processor, carries out the steps of the method according to any one of claims 1 to 6.
CN202211117272.0A 2022-09-14 2022-09-14 Multi-CPU architecture virtual machine PCI bus address management method and device Pending CN115562801A (en)

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CN202211117272.0A CN115562801A (en) 2022-09-14 2022-09-14 Multi-CPU architecture virtual machine PCI bus address management method and device

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CN202211117272.0A CN115562801A (en) 2022-09-14 2022-09-14 Multi-CPU architecture virtual machine PCI bus address management method and device

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