CN115562798B - PCIe device resource dynamic allocation method and system - Google Patents
PCIe device resource dynamic allocation method and system Download PDFInfo
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- 238000010586 diagram Methods 0.000 description 7
- 238000013468 resource allocation Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45579—I/O management, e.g. providing access to device drivers or storage
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The application provides a PCIe equipment resource dynamic allocation method and a system, wherein the method comprises the following steps: respectively configuring dynamic balance base address registers for physical or virtual functional units of PCIe equipment; configuring a basic block space and a shared block space based on resource information of physical or virtual functional units of the PCIe device; when a resource application request of a physical or virtual functional unit of the PCIe device is received, a mapping from a host physical address to a device physical address is selectively established for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from a basic block space or the basic block space and the shared block space based on the size of a resource space applied by the physical or virtual functional unit of the PCIe device. The application enables each physical or virtual functional unit to dynamically adjust the size of the resource space in the whole PCIe equipment resource space according to the actual service demand.
Description
Technical Field
The application relates to the technical field of communication equipment, in particular to a PCIe equipment resource dynamic allocation method and a PCIe equipment resource dynamic allocation system.
Background
One PCIe (Peripheral Component Interconnect express, high-speed serial computer expansion bus) device may support multiple physical functional units, or multiple virtual functional units may be virtualized by Single Root I/O Virtualization (SR-IOV) technology. Each physical functional unit or virtual functional unit (hereinafter also referred to simply as a "physical or virtual functional unit") may allocate device resource space through Memory-mapped I/O (MMIO) base address registers (BAR, base address register) defined by the PCIe specification. However, these allocated device resource spaces are static fixed, i.e., the size of the resource space occupied by each physical functional unit or virtual functional unit is fixed and only a portion of the PCIe device's resource space is occupied.
To solve the above problem, PCIe specifications organize a physical functional unit or a virtual functional unit to provide a base address register (adjustable BAR) with an adjustable size, and use the base address register with an adjustable size to enable the physical functional unit or the virtual functional unit to dynamically adjust the size of available resource space within a part of the resource space occupied by the physical functional unit or the virtual functional unit according to service requirements, as shown in fig. 1 and fig. 2. Taking fig. 1 as an example for illustration, physical function units 0 to 2 are respectively allocated three resource spaces of fixed size, namely resource space 0 to resource space 2. The size-adjustable base address register 0 can only dynamically adjust the size of the resource space provided to the physical functional unit 0 within the range of the resource space 0 according to the service requirement, the size-adjustable base address register 1 can only dynamically adjust the size of the resource space provided to the physical functional unit 1 within the range of the resource space 1 according to the service requirement, and the size-adjustable base address register 2 can only dynamically adjust the size of the resource space provided to the physical functional unit 2 within the range of the resource space 2 according to the service requirement.
It can be seen that this solution still does not change the problem that each physical or virtual functional unit can only occupy a portion of the PCIe device's resource space, and that it can only be dynamically adjusted within this portion of the fixed resource space that is occupied.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present application is to provide a method and a system for dynamically allocating resources of a PCIe device, which are used for solving the technical problem that each physical functional unit or virtual functional unit in the existing PCIe device can only use a part of the resource space of the whole device.
To achieve the above and other related objects, the present application provides a method for dynamically allocating PCIe device resources, including the following steps: respectively configuring dynamic balance base address registers for physical or virtual functional units of PCIe equipment; configuring a basic block space and a shared block space of a PCIe device resource space based on resource information of a physical or virtual functional unit of the PCIe device; when a resource application request of a physical or virtual functional unit of the PCIe device is received, a mapping from a host physical address to a device physical address is selectively established for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space or the basic block space and the shared block space based on the size of a resource space applied by the physical or virtual functional unit of the PCIe device.
In one embodiment of the present application, the configuring the dynamic balance base address register for each physical or virtual functional unit of the PCIe device includes: configuring a minimum base address register space and a maximum base address register space of the dynamic balance base address register; the minimum base address register space is used for indicating the minimum resource space which can be applied by the dynamic balance base address register, and the maximum base address register space is used for indicating the maximum resource space which can be applied by the dynamic balance base address register.
In one embodiment of the present application, configuring the basic block space and the shared block space of the PCIe device resource space includes: configuring the basic block space based on the minimum base address register space of each physical or virtual functional unit in the PCIe device; and taking the residual resource space after the basic block space is removed in the PCIe equipment resource space as the shared block space.
In one embodiment of the present application, the selectively establishing a mapping from a host physical address to a device physical address for a dynamic balancing base address register of a physical or virtual functional unit of the PCIe device from the basic block space or the basic block space and the shared block space based on a size of a resource space applied by the physical or virtual functional unit of the PCIe device comprises: when the resource space applied by the physical or virtual functional unit of the PCIe device is smaller than or equal to the minimum base address register space, establishing a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space; and when the resource space applied by the physical or virtual functional unit of the PCIe device is larger than the minimum base address register space, establishing a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space and the shared block space.
In one embodiment of the present application, the size of the resource space is adjusted in units of block units.
In an embodiment of the application, the block unit is sized by a predetermined functional unit.
To achieve the above and other related objects, the present application further provides a PCIe device resource dynamic allocation system, including: the PCIe device is provided with dynamic balance base address registers respectively for each physical or virtual functional unit of the PCIe device; and the resource controller is used for configuring a basic block space and a shared block space of the PCIe device resource space based on the resource information of the physical or virtual functional unit of the PCIe device, and selectively establishing a mapping from a host physical address to a device physical address from a dynamic balance base address register of the physical or virtual functional unit of the PCIe device based on the size of the resource space applied by the physical or virtual functional unit of the PCIe device when receiving a resource application request of the physical or virtual functional unit of the PCIe device.
As described above, the PCIe device resource dynamic allocation method and system of the application have the following beneficial effects:
the application respectively configures dynamic balance base address registers for physical or virtual functional units of the PCIe device, configures basic block space and shared block space of the PCIe device resource space based on the resource information of the physical or virtual functional units of the PCIe device, selectively establishes mapping from host physical addresses to device physical addresses for the dynamic balance base address registers of the physical or virtual functional units of the PCIe device based on the size of the resource space applied by the physical or virtual functional units of the PCIe device when receiving the resource application request of the physical or virtual functional units of the PCIe device, so that each physical or virtual functional unit can dynamically adjust the size of the resource space within the whole device resource space according to actual service requirements, and solves the problem that each physical or virtual functional unit can only occupy part of the resource space of the PCIe device and can only dynamically adjust the resource space with fixed size within the part.
Drawings
FIG. 1 is a schematic diagram of the resource allocation of a base address register of an adjustable size for each physical function unit of a PCIe device in the prior art;
FIG. 2 is a schematic diagram of the resource allocation of a base address register of an adjustable size for each virtual function unit of a PCIe device according to the prior art;
FIG. 3 is a flow chart illustrating a method for dynamically allocating PCIe device resources according to an embodiment of the present application;
FIG. 4 is a schematic diagram showing a device resource space configuration in a PCIe device resource dynamic allocation method according to an embodiment of the application;
FIG. 5 is a schematic diagram illustrating the resource allocation of each physical function unit of a PCIe device resource dynamic allocation system using dynamic balance base address registers according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating the resource allocation of each virtual function unit of a PCIe device resource dynamic allocation system using dynamic balancing base address registers according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating a configuration of a resource controller in a PCIe device resource dynamic allocation system according to an embodiment of the present application;
FIG. 8 is a schematic diagram illustrating a configuration of a resource controller in a PCIe device resource dynamic allocation system according to an embodiment of the application.
Description of element numbers:
100 PCIe device resource dynamic allocation system
110 PCIe device
120. Resource controller
121. Basic block space configuration unit
122. Shared block space configuration unit
123. Resource address mapping unit
S100-S300.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, so that only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
The embodiment provides a dynamic PCIe device resource allocation method and system, which are used for solving the technical problem that each physical functional unit or virtual functional unit (herein simply referred to as a "physical or virtual functional unit") in the existing PCIe device can only use a part of the resource space of the whole device. In this embodiment, dynamic balance base address registers are respectively configured for each physical or virtual functional unit of the PCIe device, so that each physical or virtual functional unit may dynamically apply for releasing a resource space within a range of a whole device resource space according to actual service requirements.
The PCIe device resource dynamic allocation system and the corresponding PCIe device resource dynamic allocation method according to the present application will be described in detail below.
As shown in fig. 3, an embodiment of the present application provides a method for dynamically allocating PCIe device resources, including:
step S100, respectively configuring dynamic balance base address registers for each physical or virtual functional unit of the PCIe device.
In the embodiment of the application, a dynamic balance base address register can be configured for each physical functional unit or virtual functional unit in advance, and each physical functional unit or virtual functional unit can apply for the resource space of the PCIe device through the dynamic balance base address register. To guarantee the basic requirements of each physical or virtual functional unit, PCIe devices ensure that each dynamically balanced base address register is able to apply for a minimum resource space, i.e., minimum base address register space. Obviously, the sum of the minimum base address register space of all physical functional units and virtual functional units cannot exceed the entire PCIe device resource space. In the embodiment of the present application, each dynamic balance base address register further includes a maximum base address register space, i.e. a resource space to which the dynamic balance base address register is applied for dynamically at the maximum possible. Assuming that the entire PCIe device resource space is C, the minimum base address register space of each physical functional unit or virtual functional unit is a, in some embodiments, the size of the minimum base address register space of each physical functional unit or virtual functional unit may be different, the resource space remaining after the entire PCIe device resource space is removed from the minimum base address register space reserved for each physical functional unit or virtual functional unit is B, c=k×a+b, where k is the total number of all physical functional units and virtual functional units corresponding to the PCIe device, and then the resource space that each dynamic balance base address register is maximally applied to is a+b, that is, the sum of the minimum base address register space of the dynamic balance base address register and the resource space of the PCIe device is removed from the resource space remaining after the minimum base address register space reserved for each physical functional unit or virtual functional unit, and in some cases, the PCIe device does not ensure that each dynamic balance base address register can apply to the maximum base address register space. It follows that the resource space that each dynamically balanced base address register can apply for ranges between the minimum base address register space and the maximum base address register space.
Step S200, configuring a basic block space and a shared block space of a PCIe device resource space based on the resource information of the physical or virtual function unit of the PCIe device.
In some embodiments, the resource space of the PCIe device may be divided into individual resource blocks by block unit, and the size of the block unit may be set within a predetermined functional unit. In some embodiments, the predetermined functional unit may be physical functional unit 0 (physical function 0). As described above, these PCIe device resource spaces consisting of individual resource blocks may be roughly divided into two parts, one part being the resource block space where the minimum base address register space is reserved for each physical functional unit or virtual functional unit, to ensure the basic requirements of each physical functional unit or virtual functional unit, also referred to herein as the basic block space, i.e., k×a above. The size of the basic block space may be configured according to the sum of the minimum base address register space of each physical or virtual functional unit. The other part is the allocatable resource block space shared by the base address registers of all physical or virtual functional units, which is the resource space remaining after the entire resource space of the PCIe device has been freed up of the base block space, also referred to herein as the shared block space, i.e., B above. Wherein the relation between block units, basic block space and shared block space can be seen in fig. 4.
Step S300, when receiving a resource application request of a physical or virtual function unit of a PCIe device, a resource controller selectively establishes a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual function unit of the PCIe device from the basic block space or the basic block space and the shared block space based on the size of a resource space applied by the physical or virtual function unit of the PCIe device.
In the running process of the system, the physical or virtual functional unit can apply for the corresponding resource space to the resource controller through the dynamic balance base address register according to the actual service requirement. The resource controller may select, according to the size of the applied resource space, to allocate the resource space from the basic block space or the shared block space, which is specifically as follows:
as shown in fig. 5 and 6, for simplicity, the arrows in fig. 5 and 6 only schematically illustrate the resource allocation to the shared block space, and do not include the basic block space. When the resource space applied by the physical or virtual functional unit of the PCIe device is smaller than or equal to the minimum base address register space, the resource controller allocates resources for the dynamic balance base address register of the physical or virtual functional unit from the basic block space, namely, the mapping from the host physical address to the device physical address is established for the dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space. Taking the physical functional unit 1 in fig. 5 as an example, when the resource space applied by the dynamic balance base address register 1 is smaller than or equal to the minimum base address register space of the dynamic balance base address register 1, as described above, since the minimum base address register space has been reserved in advance in the basic block space for each dynamic balance base address register, the resource controller can allocate the resource space of the corresponding size directly from the basic block space for it.
When the resource space applied by the physical or virtual functional unit of the PCIe device is larger than the minimum base address register space, the resource controller allocates the minimum base address register space for the physical or virtual functional unit from the basic block space, and the part exceeding the minimum base address register space is allocated from the shared space, namely, the mapping from the host physical address to the device physical address is established for the dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space and the shared block space respectively. Still taking the physical functional unit 1 in fig. 5 as an example, when the resource space applied by the dynamic balancing base address register 1 is larger than the minimum base address register space of the dynamic balancing base address register 1, the part exceeding the minimum base address register space can be allocated to it from the shared block space, i.e. the resource controller still allocates the minimum base address register space of the dynamic balancing base address register 1 to it from the basic block space, and the part exceeding the minimum base address register space is allocated to it from the shared block space. For example, the resource block denoted as P1 in fig. 5 is the resource allocated by the resource controller to the physical function unit 1 in the shared block space, and the resource blocks denoted as P0 and P2 are the resources allocated by the resource controller to the physical function unit 1 and the physical function unit 2 in the shared block space respectively; the resource blocks identified as P0, V1, V2 in fig. 6 are resources of the shared block space allocated by the resource controllers for physical function unit 0, virtual function unit 1, and virtual function unit 2, respectively. Since the shared block space is shared by all physical or virtual functional units, in some embodiments, a first come first get principle may be used, i.e. who applies first, the resource controller assigns it to who, and if there are remaining resources in the shared block space, it will be assigned to the following applicant. Because of the limited resources in the shared block space, the resource controller cannot guarantee that all physical or virtual functional units can apply for the requested size of resources. When the residual resource space in the shared block space cannot meet the requirement, the resource controller can process according to the preset setting, and report errors.
Furthermore, as can be seen from the distribution of the resource blocks identified as P0, P1, P2, V1, V2 in fig. 5 and 6, the present embodiment establishes a mapping from the host physical address to the PCIe device resource internal address for the dynamic balancing base address register, the mapping being continuous from the perspective of the host physical address, but may be discrete from the perspective of the PCIe device resource internal address.
In the embodiment of the application, after the physical or virtual functional unit of the PCIe device applies for a successful application to the corresponding resource space and completes the related service, the resource controller may be notified or a request for releasing the resource space may be provided to the resource controller. Upon receipt of a notification or request, the resource controller may free up the resource space previously allocated to the physical or virtual functional unit, and the freed up resource space may participate in the reallocation.
The embodiment provides a way for optimizing the configuration resources of the PCIe device, which solves the problem that each physical or virtual functional unit only occupies a part of the resource space of the PCIe device and can only be dynamically adjusted in the part of the resource space with fixed size, so that each physical functional unit or virtual functional unit can dynamically adjust the size of the resource space in the whole device resource space according to actual service requirements.
The present embodiment further provides a PCIe device resource dynamic allocation system 100, where the PCIe device resource dynamic allocation system 100 includes: PCIe device 110 and resource controller 120.
In some embodiments, each physical or virtual functional unit of the PCIe device 110 is configured with a dynamic balancing base address register, respectively.
Each dynamic balance base address register can dynamically adjust the space size of the base address register according to the requirement, and can be increased or decreased. In some embodiments, the base address register may be adjusted in units of block units (block units) when adjusting the size of the resource space.
Specifically, in this embodiment, the dynamically balanced base address register includes a minimum base address register space and a maximum base address register space.
Each dynamic balance base address register has a minimum base address register space, i.e. the minimum resource space that the dynamic balance base address register can apply for, to guarantee the basic requirements of each physical or virtual functional unit. The PCIe device 110 ensures that each dynamically balanced base address register can dynamically apply to the minimum base address register space. The sum of the minimum base address register space for all physical and virtual functional units cannot exceed the sum of the entire PCIe device 110 resource space.
Each dynamic balance base address register has a maximum base address register space for indicating the resource space that the base address register is most likely to dynamically apply for, i.e., the sum of the resource spaces of PCIe device 110. The PCIe device 110 does not guarantee that each dynamically balanced base address register can be applied to the maximum base address register space.
In this embodiment, the resource controller 120 configures a basic block space and a shared block space of the PCIe device 110 resource space based on the resource information of the physical or virtual function unit of the PCIe device 110, and selectively establishes a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual function unit of the PCIe device 110 based on the size of the resource space applied by the physical or virtual function unit of the PCIe device 110 when receiving the resource application request of the physical or virtual function unit of the PCIe device 110.
Specifically, in this embodiment, as shown in fig. 7, the resource controller 120 includes: a basic block space configuration unit 121 and a shared block space configuration unit 122.
In this embodiment, the basic block space configuration unit 121 is configured to configure the basic block space based on a minimum base address register space of each physical or virtual functional unit in the PCIe device 110; the shared block space configuration unit 122 is configured to take, as the shared block space, a remaining resource space after the basic block space is removed from the PCIe device 110 resource space.
The resource controller 120 adjusts the size of the spatial resource in units of block units, and the size of the block units may be adjusted by a predetermined functional unit. In some embodiments, the predetermined functional unit may be physical functional unit 0.
In this embodiment, as shown in fig. 8, the resource controller 120 further includes: a resource address mapping unit 123, configured to establish, when a resource space applied by a physical or virtual function unit of the PCIe device 110 is less than or equal to the minimum base address register space, a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual function unit of the PCIe device 110 from the basic block space; when the resource space applied by the physical or virtual functional unit of the PCIe device 110 is greater than the minimum base address register space, a mapping from a host physical address to a device physical address is established for a dynamic balancing base address register of the physical or virtual functional unit of the PCIe device 110 from the base block space and the shared block space.
The principle and implementation of the PCIe device resource dynamic allocation system 100 of the present embodiment are the same as or similar to those of the PCIe device 110 resource dynamic allocation method described above, and the same parts between embodiments are not repeated.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A PCIe device resource dynamic allocation method is characterized by comprising the following steps:
respectively configuring a dynamic balance base address register for each physical or virtual functional unit of the PCIe equipment; each physical or virtual functional unit applies for PCIe device resource space through the dynamic balance base address register;
configuring a basic block space and a shared block space of a PCIe device resource space based on resource information of a physical or virtual functional unit of the PCIe device, wherein the basic block space is a minimum base address register space reserved for each dynamic balance base address register and corresponding to the dynamic balance base address register, and the shared block space is a resource space remained after the PCIe device resource space removes the basic block space;
when a resource application request of a physical or virtual functional unit of the PCIe device is received, selectively establishing a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space or the basic block space and the shared block space based on the size of a resource space applied by the physical or virtual functional unit of the PCIe device;
and when the size of the applied resource space exceeds the size of the minimum base address register space corresponding to the physical or virtual functional unit, allocating a resource space part exceeding the size of the minimum base address register space from the shared block space.
2. The PCIe device resource dynamic allocation method according to claim 1, wherein said selectively establishing a mapping from host physical addresses to device physical addresses for dynamic balancing base address registers of physical or virtual functional units of the PCIe device from the basic block space or the basic block space and the shared block space based on a size of a resource space applied by the physical or virtual functional units of the PCIe device comprises:
when the resource space applied by the physical or virtual functional unit of the PCIe device is smaller than or equal to the minimum base address register space, establishing a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space;
and when the resource space applied by the physical or virtual functional unit of the PCIe device is larger than the minimum base address register space, establishing a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space and the shared block space.
3. The PCIe device resource dynamic allocation method of claim 1, wherein the method further comprises:
the size of the resource space is adjusted in units of block units.
4. The PCIe device resource dynamic allocation method according to claim 3, wherein the block unit size is set by a predetermined functional unit.
5. A PCIe device resource dynamic allocation system, comprising:
the PCIe device is provided with dynamic balance base address registers respectively for each physical or virtual functional unit of the PCIe device; each physical or virtual functional unit applies for PCIe device resource space through the dynamic balance base address register;
a resource controller for configuring a basic block space and a shared block space of a PCIe device resource space based on resource information of a physical or virtual functional unit of the PCIe device, wherein the basic block space is a minimum base address register space reserved for each dynamic balance base address register and corresponding to the dynamic balance base address register, and the shared block space is a resource space remained after the PCIe device resource space removes the basic block space; when a resource application request of a physical or virtual functional unit of the PCIe device is received, selectively establishing a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space or the basic block space and the shared block space based on the size of a resource space applied by the physical or virtual functional unit of the PCIe device; and when the size of the applied resource space exceeds the size of the minimum base address register space corresponding to the physical or virtual functional unit, allocating a resource space part exceeding the size of the minimum base address register space from the shared block space.
6. The PCIe device resource dynamic allocation system of claim 5 wherein the resource controller further comprises:
a resource address mapping unit, configured to establish, when a resource space applied by a physical or virtual function unit of the PCIe device is smaller than or equal to the minimum base address register space, a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual function unit of the PCIe device from the basic block space;
and when the resource space applied by the physical or virtual functional unit of the PCIe device is larger than the minimum base address register space, establishing a mapping from a host physical address to a device physical address for a dynamic balance base address register of the physical or virtual functional unit of the PCIe device from the basic block space and the shared block space.
7. The PCIe device resource dynamic allocation system according to claim 5, wherein the resource controller is configured to adjust the size of the resource space in units of block units.
8. The PCIe device resource dynamic allocation system according to claim 7, wherein the block unit size is set by a predetermined functional unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210671777.5A CN115562798B (en) | 2022-06-14 | 2022-06-14 | PCIe device resource dynamic allocation method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210671777.5A CN115562798B (en) | 2022-06-14 | 2022-06-14 | PCIe device resource dynamic allocation method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115562798A CN115562798A (en) | 2023-01-03 |
| CN115562798B true CN115562798B (en) | 2023-11-03 |
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| US10977051B1 (en) * | 2019-11-08 | 2021-04-13 | Xilinx, Inc. | Dynamic base address register (BAR) reconfiguration using a peripheral component interconnect express (PCIe) extended configuration space |
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| US9003071B2 (en) * | 2013-03-13 | 2015-04-07 | Futurewei Technologies, Inc. | Namespace access control in NVM express PCIe NVM with SR-IOV |
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| US10579556B2 (en) * | 2017-08-21 | 2020-03-03 | International Business Machines Corporation | Allocating address space |
| US10852967B2 (en) * | 2018-04-26 | 2020-12-01 | Mellanox Technologies, Ltd. | Facilitating virtual functions using memory allocation in a virtualization environment |
| US10564872B2 (en) * | 2018-06-29 | 2020-02-18 | Western Digital Technologies, Inc. | System and method for dynamic allocation to a host of memory device controller memory resources |
| US10956361B2 (en) * | 2018-11-29 | 2021-03-23 | International Business Machines Corporation | Processor core design optimized for machine learning applications |
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| US9804988B1 (en) * | 2015-10-30 | 2017-10-31 | Amazon Technologies, Inc. | Device full memory access through standard PCI express bus |
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