CN115552596A

CN115552596A - LGA pad structure, manufacturing method, chip module, printed circuit board and device

Info

Publication number: CN115552596A
Application number: CN202180005063.4A
Authority: CN
Inventors: 李永胜; 史坡; 杨正得; 杨威; 曾川权
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2022-12-30
Also published as: WO2022227063A1

Abstract

The embodiment of the application discloses an LGA bonding pad structure, a manufacturing method, a chip module, a printed circuit board and a device, and relates to the microelectronic technology. The LGA pad structure includes one or more signal portions for passing signals between the chip module and the printed circuit board, a ground portion for covering the one or more signal portions, and a solder resist portion disposed between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions. The embodiment of the application can effectively shield the electromagnetic interference radiation of the chip, improve the electromagnetic shielding performance and improve the product competitiveness.

Description

LGA pad structure, manufacturing method, chip module, printed circuit board and device

Technical Field

The present disclosure relates to the field of microelectronic technologies, and in particular, to a Land Grid Array (LGA) pad structure, a method for manufacturing the same, a chip module, a printed circuit board, and a device.

Background

System In Package (SIP) can integrate active electronic components with different functions and passive optical components In a single Package. For example, by integrating a chip and a component device together and connecting the chip and the component device to a Printed Circuit Board (PCB) through a solder layer, a problem of limited layout and routing of a Circuit Board of an electronic product can be solved.

Chip packaging schemes in the prior art are Ball Grid Array (BGA) and Land Grid Array (LGA). Where a BGA enables connection of chip pins by soldering to a PCB through solder balls on the bottom of the printed circuit board, and an LGA enables connection of chip pins by soldering to contacts mounted to the PCB through pads on the bottom of the printed circuit board. In the above implementation scheme, if the working current of the chip is larger, the welding layer may generate an Electromagnetic Interference (EMI) leakage condition, and the Electromagnetic shielding performance is poorer.

Disclosure of Invention

The embodiment of the application provides an LGA bonding pad structure, a manufacturing method, a chip module, a printed circuit board and a device.

In a first aspect, embodiments of the present application provide a land grid array package LGA pad structure for electrically connecting a chip module and a printed circuit board, the LGA pad structure including: one or more signal portions, a ground portion, and a solder resist portion; the one or more signal parts are used for transmitting signals between the chip module and the printed circuit board; the ground portion is used for coating the one or more signal portions; the solder resist portion is disposed between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.

Based on the design, through the coaxial architecture design of the LGA pad structure, since the grounding portion can tightly wrap the one or more signal portions, and the solder-resisting portion can isolate the grounding portion from the one or more signal portions, the grounding portion can effectively shield the electromagnetic interference radiation of the first or more signal portions, thereby improving the electromagnetic shielding performance and the product competitiveness.

In one possible design, the one or more signal portions include one or more first signal portions for passing a first signal between the chip and the printed circuit board. Based on the design, the LGA pad structure adopting the coaxial design can carry out EMI shielding on the first signals of one or more first signal parts, and the shielding performance is improved.

In one possible design, the one or more signal portions include one or more second signal portions for conveying a second signal between the chip and the printed circuit board, the second signal having a tamper resistance that is weaker than a tamper resistance of the first signal. Based on the design, the LGA pad structure adopting the coaxial design can carry out EMI shielding on the second signals of one or more second signal parts, and the shielding performance is improved.

In one possible design, the solder resist portion is further disposed between two of the one or more signal portions to surround the two signal portions. With such a design, since the solder resist portion is provided between two of the one or more signal portions, it is possible to avoid one of the two signal portions from being interfered by the other signal portion.

In one possible design, the two signal portions include a first signal portion and a second signal portion, and the solder resist portion surrounding the first signal portion and the solder resist portion surrounding the second signal portion are separated by the ground portion.

In one possible design, the pad structure is a single pad structure formed using an LGA process. In a second aspect, embodiments of the present application further provide a chip module, where the chip module includes one or more chips and one or more LGA pad structures as described above; the one or more chips are electrically connected to a printed circuit board through the one or more LGA pad structures.

Based on such design, through the coaxial architecture design of the LGA pad structure, the ground portion can effectively shield the electromagnetic interference radiation of the first or the plurality of signal portions, and the electromagnetic shielding performance is improved.

In one possible design, the one or more chips correspond one-to-one to the one or more LGA pad structures.

In a third aspect, embodiments of the present application further provide a printed circuit board including one or more LGA pad structures as described above, the printed circuit board electrically connecting a chip module through the one or more LGA pad structures.

Based on the design, through the coaxial architecture design of the LGA bonding pad structure, the grounding part can effectively shield the electromagnetic interference radiation of the first or the second signal part, and the electromagnetic shielding performance is improved.

In a fourth aspect, an embodiment of the present application further provides a signal device, where the signal device includes the chip module as described above and the printed circuit board as described above, and the printed circuit board is electrically connected to the chip module.

In a fifth aspect, an embodiment of the present application further provides a method for manufacturing an LGA pad structure, including the following steps: providing a substrate; generating a solder resist portion on the substrate; generating one or more signal portions and a ground portion based on the solder resist portion using an LGA process; wherein the one or more signal portions are for passing signals between a chip module and the printed circuit board, the ground portion is for wrapping the one or more signal portions, and the solder resist portion is located between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.

The LGA pad structure and the manufacturing method thereof, the chip module, the printed circuit board and the signal device provided by the embodiment of the application are designed by a coaxial framework of the LGA pad structure, because the grounding part can tightly wrap the one or more signal parts, and the solder resisting part can isolate the grounding part from the one or more signal parts, the grounding part can effectively shield the electromagnetic interference radiation of the first or more signal parts, the embodiment of the application can effectively inhibit the electromagnetic interference in system-in-package, the electromagnetic shielding performance is improved, and the product competitiveness is promoted.

Drawings

Fig. 1 is a schematic structural diagram of a system-in-package module according to an embodiment of the present disclosure.

Fig. 2 is another schematic structural diagram of a system-in-package module according to an embodiment of the present application.

Fig. 3 is a diagram of an application environment of a system-in-package module according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of a signaling device according to an embodiment of the present application.

Fig. 5 is a diagram of a specific application scenario of the system-in-package module according to the embodiment of the present application.

Fig. 6 is a schematic structural diagram of an LGA pad structure according to an embodiment of the present application.

FIG. 7 is a diagram of a specific application scenario of the LGA pad structure according to the embodiment of the present application.

FIG. 8 is another schematic diagram of an LGA pad structure according to an embodiment of the present application.

FIG. 9 is another schematic diagram of an LGA pad structure according to an embodiment of the present application.

FIG. 10 is a flowchart of a method for fabricating an LGA pad structure according to an embodiment of the present application.

FIG. 11 is another flowchart of a method for fabricating an LGA pad structure according to an embodiment of the present application.

Description of the main elements

System in package module 100

External device 200

Chip module 10

Chips 101, 11

Component device groups

102, 15

Plastic packaging layers

103, 13

Shielding layer 104

LGA pad structure 105

Conventional bonding pad 106

Ground portion 107

Solder resist portion 108

Power signal portion 109

Sensitive signal portion 110

Solder layer 12

Sputter coating 14

Printed

circuit boards

16, 20

Signal pad 17

Ground pad 18

Shielding case 21

The following detailed description will explain the present application in further detail in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application.

In the embodiments of the present application, the terms "first", "second", and the like are used only for distinguishing different objects, and are not intended to indicate or imply relative importance, nor order to indicate or imply relative importance. For example, a first application, a second application, etc. is used to distinguish between different applications and not to describe a particular order of applications, and a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of that feature.

In the description of the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or illustrations. Any embodiment or design described as "exemplary" or "e.g.," in the embodiments of this application should not be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

With the rapid development of the electronic industry, electronic products are required to be more miniaturized, lighter, and more diversified in functions according to the user's needs. As an assembly technique to meet such a demand, homogeneous or heterogeneous Integrated Circuit (IC) chips are integrated into a single unit module. One such packaging technology that meets this trend is System In Package (SIP). In the system-in-package module, respective devices having different functions are mounted in a single package to utilize a given space, enabling miniaturization. In some possible scenarios, the system-in-package module may generate Electromagnetic Interference (EMI) leakage, and the Electromagnetic shielding performance is poor.

In order to deal with the above EMI leakage, in a possible implementation manner, as shown in fig. 1, a system in package module 100 may be configured by covering a molding compound layer 13 on an upper surface of the chip 11, the chip 11 being interconnected with the printed circuit board 16 through the soldering layer 12, and disposing a shielding cover 21 on an outer side of the chip 11 to connect two ends of the shielding cover 21 to the printed circuit board 16, that is, the shielding cover completely covers the chip 11, so that the electromagnetic interference of the system in package module 100 may be shielded, and the electromagnetic interference shielding performance of the system in package module 100 may be improved. In this implementation, the solder layer 12 may be a Land Grid Array (LGA) layer.

In the above implementation, based on the reliability requirement of the system-in-package module 100, a certain gap needs to exist between the shielding can 21 and the chip 11 in both the vertical direction and the horizontal direction. In addition, the shielding cover 21 needs to have pads on the surface of the printed circuit board 16, and the shielding cover 21 needs to have an internal spacer rib as a support, which increases the height and area occupied by the shielding cover 21, thereby increasing the volume of the system-in-package module 100 and reducing the product competitiveness.

In another possible implementation manner of the present application, as shown in fig. 2, the system-in-package module 100 may be connected to the printed circuit board 16 through the solder layer 12. For example, the chip 11 may be mounted on the printed circuit board 16 by a solder ball array package method or a grid array package method. The upper surface of the chip 11 is integrated with a component device group 15, and the sputter coating 14 can shield the printed circuit board 16 from external radiation. The molding layer 13 may wrap the upper surface of the chip 11 and the device group 15. In this implementation, the solder layer 12 may be an LGA layer.

The side surfaces and the upper surfaces of the chip 11 and the plastic package layer 13 are sputtered with metal coating films to form a shielding structure, and based on the design, the purpose of shielding electromagnetic interference can be achieved. The implementation of fig. 2 has advantages in height and area over the implementation of fig. 1 in which the shield 21 is provided outside the chip 11. In the above implementation, the solder layer 12 is exposed outside the shielding structure, which will cause EMI radiation leakage of the solder layer 12 and become a bottleneck of the shielding performance of the sputter coating scheme.

In another possible implementation manner of the present application, in order to reduce the risk of EMI leakage of the solder layer of the sputtering coating scheme, a ring of ground pads 18 may be added to the outer periphery of the signal pads 17, so as to achieve the function of electromagnetic shielding. Specifically, as shown in fig. 3, is a portion of a top view of a system-in-package module. According to the above-described embodiment of the present application, a plurality of ground pads 18 form a faraday cage around the signal pad 17. Such a faraday cage can prevent electromagnetic waves generated by the signal pad 17 from being radiated to the outside. In addition, the faraday cage can prevent external electromagnetic waves from entering and interfering with the signal pads 17. It can be understood that "faraday cage" can refer to a cage formed by good conductors such as metal, and the cage body is grounded, so that the electromagnetic shielding function can be effectively realized, and electromagnetic radiation is prevented from entering or radiating outside.

In the above implementation, a circle of grounding pads 18 is added outside the bonding layer, which needs to occupy a large amount of grid array packaging resources, and the signal pads 17 occupy a smaller area. If the chip has more signals and the pad resources are tight, the chip area may need to be enlarged to obtain a sufficient number of pads to include ground. Taking the 9 pads shown in fig. 3 as an example, if a chip has multiple signals to be connected to the pcb 16 through the grid array package layer, and the chip area is the same as the 9 pads, the chip area can only be enlarged to increase the pads, which will certainly affect the area gain of the system-in-package module. In addition, the pads of the grid array package layer still have a certain gap therebetween, and thus, the shielding performance of the above-described implementation is limited.

It will be appreciated that in several implementations described above, the LGA layer of the system-in-package module is at risk of EMI radiation leakage, and the above packaging scheme will affect the area yield of the system-in-package module and the shielding performance is limited. Therefore, the embodiment of the application provides an LGA pad structure, a processing method, a chip, a printed circuit board and a signal device.

Please refer to fig. 4, which is a schematic diagram of a signaling apparatus 100 according to an embodiment of the present disclosure. The signaling device 100 in the embodiment of the present application can establish an electrical connection with an external device 200. For example, the signal device 100 may transmit a signal to the external device 200, or the signal device 100 may receive a signal of the external device 200.

It is understood that in one implementation, the signaling device 100 may include a chip module 10 and a printed circuit board 20. The chip module 10 may be electrically connected to the printed circuit board 20, and the printed circuit board 20 may be electrically connected to an external device 200. Based on such a design, the chip module 10 can establish a connection with the external device 200 through the printed circuit board 20. For example, the chip module 10 may transmit a signal to the external device 200 or receive a signal of the external device 200, thereby implementing signal transmission between the chip module 10 and the external device 200.

Fig. 5 is a schematic diagram illustrating a specific application scenario of the system-in-package module 300 according to the embodiment of the present application. Embodiments of the present application provide a system in package module 300, and the system in package module 300 may include a chip module 10 and a printed circuit board 20. In one possible scenario, the chip module 10 may be disposed over an upper surface of the printed circuit board 20. It will be appreciated that the chip module 10 is, for example, a high performance integrated circuit module comprising one or more chips 101 and possibly passive components. The system-in-package module 300 of the present application may be assembled into a functional system in a single package.

The PCB may comprise a rigid PCB material (such as a glass-fiber filled epoxy), a flexible printed circuit (e.g., a printed circuit formed from a flexible polymer sheet such as polyimide), or a rigid flexible circuit (e.g., a printed circuit including both rigid portions and flexible leads). PCBs on which components such as integrated circuit components and discrete components are mounted may sometimes be referred to as Main Logic Boards (MLBs). Soldering or other suitable mounting schemes may be used to mount the components on the PCB. For example, the component may be a Surface Mount Technology (SMT) component that is mounted directly onto a PCB. System-in-package can achieve higher volumetric efficiency, superior reliability, and higher performance.

The chip module 10 may include one or more chips 101 and a component group 102. It is understood that one chip 101 is exemplified in the embodiments of the present application. The upper surface of the chip 101 integrates the component device group 102. In one possible case, the upper surface of the chip 101 and the outer side of the device group 102 are both wrapped with a molding layer 103.

It is understood that the molding layer 103 may be a filler, and the molding layer 103 may be used for encapsulating the chip 101 and the device group 102. The molding layer 103 in this embodiment may cover the chip module 10. Alternatively, the molding layer 103 may be made of an insulating material. As an example, the molding layer 103 may be formed by a filling process, a liquid sealing molding process, or the like.

Alternatively, in this embodiment, the molding layer 103 may be formed by a filling process, and the molding layer 103 may smoothly and rapidly fill up the gap between the upper surface of the chip 101 and the device group 102, so as to ensure the stress reliability of the chip 101 and the device group 102. Optionally, in one or more embodiments of the present application, the molding layer 103 covering the chip module 10 may have a first width, where the first width may be greater than or equal to 50 micrometers.

It is understood that the set of component devices 102 can be used to implement system-in-package functionality. Optionally, in this embodiment, the component device group 102 may include devices such as a resistor, a capacitor, and an inductor. In other implementation manners, the component device group 102 may further include other electronic devices, and the application is not limited thereto.

In this embodiment, a package may be formed on the opposite outer side of the chip module 10 for packaging the chip module 10 on the printed circuit board 20. In various embodiments of the present application, the package body may include a shielding layer 104 to implement shielding packaging of the chip module 10 mounted on the printed circuit board 20, and the shielding layer 104 may be disposed on an outer surface of the molding layer 103 on the chip module 10 that needs shielding packaging. Further, in order to improve the shielding effect, in the embodiment of the present application, the shielding layer 104 is disposed on the outer surface of the molding layer 103 on the chip module 10 and on both sides of the chip 101.

In the technical scheme of the application, the shielding layer 104 sputtered by metal is attached to the outer surface of the plastic packaging layer 103, so that no gap exists between the shielding layer 104 and the plastic packaging layer 103. Optionally, in one or more possible embodiments of the present application, the thickness of the shielding layer 104 may be between 2 microns and 10 microns. In this way, the shielding layer 104 can better cover the outer surface of the molding layer 103 and the side surface of the chip 101, so that the electronic element in the packaging area can be well shielded, and the non-packaging area is not affected.

It will be appreciated that in one use scenario, the chip 101 is provided with one or more LGA pad structures 105 proximate to a lower surface of the printed circuit board 20. One or more pins of the chip 101 may be electrically connected to one or more LGA pad structures 105, respectively. The upper surface of the printed circuit board 20 adjacent to the chip 101 is provided with one or more LGA pad structures 105. The pad structure 105 of the pcb 20 and the pad structure 105 of the chip 101 may be coupled together to achieve signal communication. In practice, when the chip 101 is disposed on the printed circuit board 20, the pad structures 105 of the two can be integrated, i.e. become a complete pad structure 105. The chip 101 and the printed circuit board 20 may be coupled by soldering, but the embodiment is not limited thereto.

In one embodiment, the number of LGA pad structures 105 of the printed circuit board 20 is the same as and corresponds to one of the number of LGA pad structures 105 of the chip 101. The LGA pad structure 105 of the printed circuit board 20 may be electrically connected with the LGA pad structure 105 of the chip 101. It is understood that the LGA pad structure 105 and the LGA pad structure 105 shown in FIG. 5 are each illustrated by way of example as 5. In other possible embodiments, the number of the LGA pad structures 105 and the number of the LGA pad structures 105 may be adjusted according to actual needs, and the disclosure is not limited thereto.

It is to be appreciated that the LGA pad structure 105 may be a single pad structure formed using an LGA process.

Referring to fig. 6, an LGA pad structure 105 provided in the present application will be described with reference to the accompanying drawings and a practical application scenario. It is understood that in the embodiment of the present application, the configurations of the LGA pad structures 105 of the printed circuit board 20 and the LGA pad structures 105 of the chip 101 are identical. Fig. 6 is a schematic cross-sectional view (top view) of the LGA pad structure 105 according to an embodiment of the present application. The LGA pad structure 105 in this embodiment is an LGA coaxial structure, and refer to fig. 7 specifically. The LGA pad structure 105 may include one or more signal portions. The one or more signal portions may include a power signal portion 109. Still further, the LGA pad structure 105 may also include a ground portion 107 and a solder resist portion 108. It is understood that one power signal portion 109 is shown in fig. 6 for illustration.

Specifically, the solder resist portion 108 is wrapped around the power signal portion 109, and the solder resist portion 108 is disposed between the power signal portion 109 and the ground portion 107 to isolate the ground portion 107 from the power signal portion 109.

Wherein the power signal portion 109 provides an interconnection path for signal transmission between the chip 101 and the printed circuit board 20. Based on such a design, the chip 101 can transmit signals to the printed circuit board 20 through the power signal portion 109 in the LGA pad structure 105, or the chip 101 can receive signals from the printed circuit board 20 through the power signal portion 109 in the LGA pad structure 105, and signal transmission is more convenient and simpler.

It is understood that the solder resist portion 108 in the present embodiment is located between the power signal portion 109 and the ground portion 107, and based on such design, the solder resist portion 108 can prevent the power signal portion 109 from being short-circuited by the ground portion 107, thereby effectively protecting the power signal portion 109. In one use scenario, the ground portion 107 may be used to shield the power signal portion 109 from EMI emissions.

It will be appreciated that in the coaxial architecture design of the LGA pad structure 105, the power signal portion 109 and the solder resist portion 108 can be tightly encapsulated by the ground portion 107. Based on the design, there is no gap between the ground portion 107 and the power signal portion 109 in the LGA pad structure 105. Further, the ground portion 107 can effectively shield the power signal of the power signal portion 109 from EMI radiation. Therefore, by adopting the coaxial architecture design of the LGA pad structure 105, an efficient shielding function can be realized for the power signal or all the signals of the power signal part 109 of the chip 101, and EMI radiation leakage is avoided.

In another possible scenario, when the power signal of the chip 101 is less, i.e. the radiation source of the chip 101, as shown in fig. 7, the embodiment of the present application may use the LGA pad structure 105 of the coaxial architecture to transmit the power signal of the chip 101, and other signals may be transmitted through the conventional pad 106. It is understood that in the application scenario shown in fig. 7, the power signal may be a large current signal of the chip 101, and the other signal may be a small current signal. With the above design, the number of ground pads can be reduced, thereby increasing the area yield of the system-in-package module. In addition, the gap between the grounding pads can be eliminated, and the shielding performance of the product is improved.

Please refer to fig. 8, which is a schematic structural diagram of an LGA pad structure 105 according to another embodiment of the present application. The difference from the embodiment of the LGA pad structure 105 shown in fig. 6 is that the LGA pad structure 105 in this embodiment may include a plurality of power signal portions 109 as shown in fig. 8. The LGA pad structure 105 can shield multiple power signal portions 109 from EMI leakage with a single ground portion 107, with greater shielding efficiency.

It is understood that fig. 8 illustrates 4 power signal portions 109 as an example. For example, embodiments of the present application may employ one ground portion 107 to simultaneously shield EMI emissions of 4 power signal portions 109. In the application scenario shown in fig. 8, the solder resist portion 108 is wrapped around the plurality of power signal portions 109, the plurality of power signal portions 109 are arranged at intervals, and the solder resist portion 108 is arranged in each gap between two power signal portions 109, and the ground portion 107 is wrapped around the solder resist portion 108. Based on such a design, the ground portion 107 can effectively shield EMI radiation of the plurality of power signals, and the solder resist portion 108 can effectively ensure that the plurality of power signal portions 109 are not shorted by the ground portion 107. Thus, the LGA pad structure 105 in this embodiment can achieve an efficient shielding design by using this coaxial architecture for either the power signal or the entire signal.

In a possible application scenario, the chip 101 may further include a power signal and a sensitive signal, for example, a radio frequency chip may include both an uplink signal and a downlink signal, and the uplink signal and the downlink signal may be collectively referred to as the sensitive signal. It will be appreciated that in some possible implementations, the power of the power signal may be greater than the power of the sensitive signal. To this end, other embodiments of the present application provide LGA pad structures 105 that may also effectively protect sensitive signals from power signals.

Fig. 9 is a schematic structural diagram of an LGA pad structure 105 according to another embodiment of the present application. The difference from the embodiment of LGA pad structure 105 shown in figure 6 is that LGA pad structure 105 in this embodiment may include one or more sensitive signal portions 110 and one or more power signal portions 109, as shown in figure 9.

In the embodiment of the present application, the plurality of signals of the chip 101 may also be isolated by the ground portion 107. It is to be understood that fig. 9 illustrates an application scenario in which 1 sensitive signal portion 110 and 5 power signal portions 109 are shown as examples. The sensitive signal portion 110 in this embodiment may be spaced from the 5 power signal portions 109, and every two power signal portions 109 are also spaced from each other. I.e. there is a gap between the sensitive signal portion 110 and the 5 power signal portions 109 and a gap between each power signal portion 109.

In the scenario shown in fig. 9, the solder resist portion 108 is also disposed between the power signal portion 109 and the sensitive signal portion 110 to surround the power signal portion 109 and the sensitive signal portion 110. The solder mask portion 108 is wrapped around both the sensitive signal portion 110 and the 5 power signal portions 109. The ground portion 107 is wrapped around the solder resist portion 108. Still further, the solder resist portion 108 surrounding the power signal portion 109 and the solder resist portion 108 surrounding the sensitive signal portion 110 may be separated by the ground portion 107.

It is understood that the power signal portion 109 in this embodiment provides an interconnection path for power signal transmission between the chip 101 and the printed circuit board 20. The sensitive signal portion 110 provides an interconnection path for sensitive signal transmission between the chip 101 and the printed circuit board 20. The ground portion 107 may effectively shield EMI emissions of power signals. It is understood that the power signal is a high current signal and the sensitive signal is a low current signal. It will be appreciated that in some possible scenarios the immunity to interference of the sensitive signal is less than the immunity to interference of the power signal. In some scenarios, the sensitive signal is susceptible to interference from the power signal. Thus, the ground portion 107 may also protect sensitive signals from EMI interference from power signals. It will be appreciated that the solder mask portion 108 is effective to ensure that the power signal portion 109 and the sensitive signal portion 110 are not shorted. Based on such a design, the embodiment of the present application may isolate the power signal of the chip 101 from the sensitive signal, so that the sensitive signal may be protected from the EMI interference of the power signal.

Referring to fig. 10, a flowchart of a method for fabricating an LGA pad structure according to an embodiment of the present application is shown, where the method can fabricate the LGA pad structure on a chip module, and the flowchart of the method for fabricating the LGA pad structure can include the following steps: step S101: a substrate is provided. Step S102: a solder copper layer is formed on the substrate. For example, in this embodiment, the solder pattern can be formed by brushing a layer of copper on the bottom layer of the substrate, etching away the excess portion, and then adding a solder mask and curing. Step S103: a solder resist portion is formed and one or more signal portions and a ground portion are generated using an LGA process based on the solder resist portion.

It is to be appreciated that embodiments of the present application may form the solder resist portion 108 on a substrate and may generate the one or more signal portions 109 and the ground portion 107 using an LGA process based on the solder resist portion 108, wherein the solder resist portion 108 may be located between the ground portion 107 and the one or more signal portions 109.

Referring to fig. 11, a flowchart of a method for fabricating an LGA pad structure according to an embodiment of the present application is provided, where the method can fabricate the LGA pad structure on a PCB, and the flowchart of the method for fabricating the LGA pad structure can include the following steps: step S111: a PCB is provided. Step S112: a solder copper layer is formed on the PCB. For example, in this embodiment, the solder pattern may be formed by brushing a layer of copper on the surface of the PCB, etching away the excess portion, and then adding a solder resist layer and curing. Step S113: solder resist portions are formed and, based on the solder resist portions, an LGA process is used to generate one or more signal portions and a ground portion. It is understood that embodiments of the present application may form the solder mask portion 108 on a substrate and may generate the one or more signal portions 109 and the ground portion 107 using an LGA process based on the solder mask portion 108, wherein the solder mask portion 108 may be located between the ground portion 107 and the one or more signal portions 109. Further, step S114 is performed to brush a layer of solder paste on the solder pattern to form a pad.

With the coaxial structure design of the LGA pad structure 105 in the embodiment of the present application, since the ground portion 107 can tightly wrap the power signal portion 109 and the solder mask portion 108, the ground portion 107 can effectively shield the EMI radiation of the power signal portion 109, thereby improving the electromagnetic shielding performance and enhancing the product competitiveness. In the above method, since the solder resist portion is formed in step S113, referring specifically to the structure of fig. 7, when the LGA process is employed to generate the one or more signal portions 109 and the ground portion 107 in S114, the one or more signal portions 109 and the ground portion 107 may be formed directly using a metal, such as copper, which does not form a metal due to the presence of the solder resist portion 108, thereby isolating the one or more signal portions 109 and the ground portion 107.

In the above 2 method flows, the pad structure is a single pad structure formed by LGA process, i.e. it is not necessary to form the solder mask portion surrounding one or more signal portions 109 by combining a plurality of different pads, but the solder mask portion is implemented by one-time flow, and the formed product has small volume, low cost and simple implementation.

It should be understood by those skilled in the art that the above embodiments are only for illustrating the present application and are not used as limitations of the present application, and that suitable changes and modifications of the above embodiments are within the scope of the present application as claimed.

Claims

A land grid array package (LGA) pad structure for electrically connecting a chip module to a printed circuit board, the LGA pad structure comprising: one or more signal portions, a ground portion, and a solder resist portion;

the one or more signal parts are used for transmitting signals between the chip module and the printed circuit board;

the ground portion is used for coating the one or more signal portions;

the solder resist portion is disposed between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.
The LGA pad structure of claim 1,

the one or more signal portions include one or more first signal portions for passing a first signal between the chip and the printed circuit board.
The LGA pad structure of claim 2,

the one or more signal portions include one or more second signal portions for communicating a second signal between the chip and the printed circuit board, the second signal having a tamper resistance that is less than a tamper resistance of the first signal.
The LGA pad structure of any one of claims 1-3,

the solder resist portion is also disposed between two of the one or more signal portions to surround the two signal portions.
The LGA pad structure of claim 4, wherein,

the two signal portions include a first signal portion and a second signal portion, and the solder resist portion surrounding the first signal portion and the solder resist portion surrounding the second signal portion are separated by the ground portion.
The LGA pad structure of any one of claims 1-5,

the pad structure is a single pad structure formed using an LGA process.
A chip module comprising one or more chips and one or more LGA pad structures according to any of claims 1-6; the one or more chips are electrically connected to a printed circuit board through the one or more LGA pad structures.
The chip module of claim 7,

the one or more chips correspond one-to-one with the one or more LGA pad structures.
A printed circuit board comprising one or more LGA pad structures according to any of claims 1-6, wherein the printed circuit board electrically connects a chip module through the one or more LGA pad structures.
A signaling device, characterized in that the signaling device comprises a chip module according to claim 7 or 8 and a printed circuit board according to claim 9, which printed circuit board is electrically connected to the chip module.
A method for fabricating an LGA pad structure is characterized in that,

providing a substrate;

generating a solder resist portion on the substrate;

generating one or more signal sections and a ground section based on the solder resist section using an LGA process;

wherein the one or more signal portions are used for passing signals between a chip module and the printed circuit board, the ground portion is used for wrapping the one or more signal portions, and the solder resist portion is located between the ground portion and the one or more signal portions to isolate the ground portion from the one or more signal portions.