CN115549695A - 2-bit-flipping decoding method and system thereof - Google Patents

Abstract

The application discloses a 2-bit flipping decoding method and a system thereof. The method comprises the following steps: acquiring a soft information sequence, wherein each element in the soft information sequence comprises a sign bit and an auxiliary bit, and the sign bit of each element in the soft information sequence forms a hard decision sequence; calculating a check sequence according to the hard decision sequence and the check matrix; determining an error equation sequence according to the check sequence and the check matrix; and for the elements which are greater than or equal to a preset threshold in the error equation sequence, further judging whether the auxiliary bit of the corresponding element in the soft information sequence is in a first state, if so, turning the auxiliary bit to be in a second state, and if not, turning the sign bit of the corresponding element in the soft information sequence. The algorithm is lower in complexity, better in performance and faster in convergence.

Description

2-bit-flipping decoding method and system thereof

Technical Field

The present application relates to the field of storage technologies, and in particular, to a 2-bit flipping decoding method and system.

Background

QC-LDPC (Quasi-cyclic Low-sensitivity Parity-Check Code) is used as a linear error correcting Code and gets more and more attention due to strong error correcting capability, low decoding complexity and strong realizability. In some occasions with higher requirements on information transmission reliability, the traditional bit flipping algorithm has poor correction capability and slow algorithm convergence, so that the decoding efficiency is not high, and the improved weighted bit flipping algorithm has the information reliability meeting the requirements, but the algorithm complexity is greatly improved due to the calculation of the weighting factors. Therefore, a bit flipping decoding algorithm with lower algorithm complexity, better performance and faster convergence is urgently needed.

Disclosure of Invention

In order to solve the above problems, the present invention provides a 2-bit flipping decoding method and system, which has lower algorithm complexity, better performance and faster convergence.

One aspect of the present application discloses a 2-bit flipping decoding method, including:

acquiring a soft information sequence, wherein each element in the soft information sequence comprises a sign bit and an auxiliary bit, and the sign bit of each element in the soft information sequence forms a hard decision sequence;

calculating a check sequence according to the hard decision sequence and the check matrix;

determining an error equation sequence according to the check sequence and the check matrix; and

and for the elements which are greater than or equal to a preset threshold in the error equation sequence, further judging whether the auxiliary bit of the corresponding element in the soft information sequence is in a first state, if so, turning the auxiliary bit to be in a second state, and if not, turning the sign bit of the corresponding element in the soft information sequence.

In a preferred embodiment, the auxiliary bit represents a confidence level of the sign bit, and the first state has a higher confidence level than the second state.

In a preferred embodiment, the step of obtaining the soft information sequence further includes: a codeword sequence is obtained, and the lower bits of each element in the codeword sequence are supplemented with another auxiliary bit to generate the soft information sequence.

In a preferred embodiment, after determining the error equation sequence according to the check sequence and the check matrix, the method further includes: and comparing the hard decision sequence with corresponding elements in the hard decision sequence, and if the hard decision sequence is different from the corresponding elements in the hard decision sequence, adding 1 to the value of the corresponding element in the error equation sequence.

In a preferred embodiment, the method further comprises:

counting the number of inverted sign bits of each element in the soft information sequence in the iteration process;

judging whether the overturned count is zero or not;

if the threshold value is zero, judging whether the preset threshold value is equal to a minimum threshold value, and if the threshold value is not the minimum threshold value, subtracting 1 from the preset threshold value; and

if not, judging whether the preset threshold is equal to the maximum threshold value, and if not, adding 1 to the preset threshold.

In a preferred embodiment, the maximum threshold is a maximum column weight of the check matrix, and the minimum threshold is not less than one half of the column weight of the check matrix.

In a preferred embodiment, if the predetermined threshold is equal to the maximum threshold, it is determined whether the auxiliary bit of the corresponding element in the soft information sequence is in the first state, and if the auxiliary bit of the corresponding element in the soft information sequence is in the first state, the auxiliary bit and the sign bit of the corresponding element in the soft information sequence are simultaneously inverted.

In a preferred embodiment, the method further comprises the following steps: updating the check sequence and the error equation sequence after each column of the soft information sequence is flipped.

In a preferred embodiment, the first state is a logic 1, and the second state is a logic 0.

In a preferred embodiment, if each element value in the check sequence is 0, the hard decision sequence is output.

Another aspect of the present application further discloses a 2-bit flipping decoding system, including:

the soft decision processing device comprises an acquisition unit, a decision unit and a decision unit, wherein the acquisition unit is used for acquiring a soft information sequence, each element in the soft information sequence comprises a sign bit and an auxiliary bit, and the sign bit of each element in the soft information sequence forms a hard decision sequence;

the calculation unit is used for calculating a check sequence according to the hard decision sequence and the check matrix;

the check unit is used for determining an error equation sequence according to the check sequence and the check matrix; and

and the overturning unit is used for further judging whether the auxiliary bit of the corresponding element in the soft information sequence is in a first state or not for the element which is greater than or equal to the preset threshold in the error equation sequence, if so, overturning the auxiliary bit to be in a second state, and if not, overturning the sign bit of the corresponding element in the soft information sequence.

In another aspect, the present application further discloses a computer-readable storage medium having stored therein computer-executable instructions, which when executed by a processor, implement the steps in the method as described above.

Compared with the prior art, the method has the following beneficial effects:

the invention provides a 2-bit flipping decoding algorithm of QC-LDPC. The internal operation data of the algorithm is 2 bits, the high-order data of the algorithm is a sign bit, and the low-order data of the algorithm determines the information reliability of the algorithm. When the external input data is 1bit, the external input data must be mapped into 2-bit internal operation data; when external data passes through an AWGN (Additive White Gaussian Noise) channel, quantization must be performed into 1-bit or 2-bit quantized data, and the 1-bit quantized data must be mapped into 2-bit internal operation data. The inversion rule of the algorithm is 2-bit inversion, low-bit data with low reliability of information is preferentially inverted, the sign bit is inverted, and the 2-bit inversion algorithm can effectively improve the error correction capability.

The algorithm can dynamically update the threshold, realize the update of the threshold by using a method for counting the turnover times, and accelerate the convergence speed by adopting the dynamic threshold.

The algorithm compares the code word sequence with the hard decision sequence to obtain variable nodes which are easy to overturn, adds 1 to the element value in the error equation sequence, accelerates the overturn probability of the variable nodes and can accelerate the convergence rate.

In the algorithm, each row calculates the check sequence and carries out judgment in advance, a mark of successful decoding can be obtained after a certain row is calculated, and a hard judgment sequence can be output in advance. And each column calculates the check sequence and updates the error equation sequence, so that the error equation sequence is kept in an optimized state, the overturning success probability is improved, the error correction capability can be effectively improved, and the convergence speed is accelerated.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, feature a + B + C is disclosed, in another example, feature a + B + D + E is disclosed, and features C and D are equivalent technical means that serve the same purpose, technically only one feature is used, but not both, and feature E may be technically combined with feature C, then the solution of a + B + C + D should not be considered as already described because the technology is not feasible, and the solution of a + B + C + E should be considered as already described.

Drawings

Fig. 1 shows a flow chart of a decoding method of 2-bit flipping in one embodiment of the present application.

FIG. 2 is a flow chart illustrating dynamically updating a predetermined threshold in one embodiment of the present application.

Fig. 3 shows a flow chart of additive white gaussian noise in one embodiment of the present application.

Fig. 4 shows an overall flow chart of a 2-bit flipping algorithm in one embodiment of the present application.

Fig. 5 is a diagram illustrating a dynamic threshold update rule in an embodiment of the present application.

FIG. 6 shows an algorithmic flow diagram of the original scheme in one embodiment of the present application.

FIG. 7 is a flow chart illustrating check sequence pre-storing in one embodiment of the present application.

FIG. 8 shows a flow chart of error equation calculation in one embodiment of the present application.

Fig. 9 shows a flow chart of the algorithm of the improvement 1 in one embodiment of the present application.

Fig. 10 shows a schematic diagram of 2-bit flip rule 1 in one embodiment of the present application.

Fig. 11 shows a schematic diagram of 2-bit flip rule 2 in one embodiment of the present application.

Fig. 12 shows a flow chart of the algorithm of the improvement 2 in one embodiment of the present application.

FIG. 13 shows a flow chart of error equation calculation and roll-over node voting in one embodiment of the present application.

Fig. 14 shows a flowchart of the algorithm of modification 3 in an embodiment of the present application.

FIG. 15 is a flow chart illustrating an nth column check sequence update in an embodiment of the present application.

Fig. 16 shows a signal-to-noise ratio versus bit error rate curve in an embodiment of the present application.

FIG. 17 shows a signal-to-noise ratio versus iteration number plot in an embodiment of the present application.

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

A first embodiment of the present application discloses a 2-bit-flipped decoding method, and fig. 1 shows a flowchart of the 2-bit-flipped decoding method in an embodiment. The method comprises the following steps:

step 101, a soft information sequence is obtained, each element in the soft information sequence comprises a sign bit and an auxiliary bit, and the sign bit of each element in the soft information sequence forms a hard decision sequence. In one embodiment, the auxiliary bit represents the confidence level of the sign bit. The auxiliary bit may have two states: a first state and a second state, the first state may be more trustworthy than the second state.

For example, in one embodiment, the first state is a logic 1 and the second state is a logic 0, i.e.: the soft information sequence elements with an auxiliary bit of 1 are more reliable than the soft information sequence elements with an auxiliary bit of 0, independent of the sign bit. It should be appreciated that in other embodiments, the first state may be a logic 0 and the second state may be a logic 1.

The sequence of soft information may be obtained from a direct flash (NAND flash) device or other communication device (e.g., receiver, etc.). The internal operation data of the 2-bit inversion algorithm is 2 bits, the high-order data is the sign bit, and the low-order data determines the information reliability. When the external input data may also be 1bit, it must be mapped to 2bit internal operation data. At this time, data read from the flash memory device includes only a codeword sequence of 1-bit sign bits. Therefore, in this embodiment, the step of acquiring the soft information sequence further includes: the lower bits of each element in the codeword sequence are supplemented with another auxiliary bit to generate a soft information sequence. Each element in the codeword sequence constitutes a sign bit of the soft information sequence, and an auxiliary bit supplemented at a lower level of the sign bit represents the trustworthiness of the sign bit. In one embodiment, the low order bits of each element of the codeword sequence are supplemented with a one-bit logic 0, thereby constituting a soft information sequence.

And 102, calculating a check sequence according to the hard decision sequence and the check matrix.

In one embodiment, the hard decision sequence Y = [ Y = ₁ ,y ₂ ,y ₃ ,...,y _N ]The check matrix is H _mn Then the calculated check sequence is S = [ S ] ₁ ,s ₂ ,s ₃ ,...,s _M ]Wherein, in the process,

wherein M is the length of the check bit, N is the length of the code, and N-M is the length of the information bit.

103, if at least one or more elements in the check sequence S are not zero, then according to the check sequence S and the check matrix H _mn A sequence of error equations (also referred to as a sequence of the number of unsatisfied check equations) is determined. In one embodiment, the computed error square program is F = [ F = [) ₁ ,f ₂ ,f ₃ ,...,f _N ]Wherein, in the process,

in another embodiment, if each element S in the check sequence S is a sequence of elements S _m If the values are zero, the decoding is completed, and a hard decision sequence Y is output.

And 104, further judging whether the auxiliary bit of the corresponding element in the soft information sequence is in a first state or not for the element which is greater than or equal to the preset threshold in the error equation sequence F, if so, turning the auxiliary bit to be in a second state, and if not, turning the sign bit of the corresponding element in the soft information sequence.

In the application, the low-bit data with low reliability is preferentially inverted, the sign bit is inverted, the storage data with high reliability can invert the low bit to become the storage data with low reliability, the storage data with low reliability can invert the high bit to become the new storage data with low reliability, and the error correction capability can be effectively improved.

Fig. 2 shows a flow chart for dynamically updating the predetermined threshold during a decoding iteration. In one embodiment, the 2-bit flipping decoding method further includes the following steps:

step 201, counting the count (or called the number of inversion) of the sign bit of each element in the soft information sequence in the current iteration process.

In step 202, it is determined whether the flipped count is zero.

Step 203, if it is zero, determine whether the predetermined threshold is equal to the minimum threshold, if not, subtract 1 from the predetermined threshold. If the threshold value is the minimum threshold value, the current preset threshold value is kept.

And step 204, if the preset threshold is not zero, judging whether the preset threshold is equal to the maximum threshold, and if the preset threshold is not equal to the maximum threshold, adding 1 to the preset threshold. If the threshold value is the maximum threshold value, the current preset threshold value is kept.

In one embodiment, if the predetermined threshold is equal to the maximum threshold, it is determined whether the auxiliary bit of the corresponding element in the soft information sequence is in the first state, and if the auxiliary bit of the corresponding element in the soft information sequence is in the first state, the auxiliary bit and the sign bit of the corresponding element in the soft information sequence are flipped.

In one embodiment, the method further comprises: updating the check sequence and the error equation sequence after each column of the soft information sequence is flipped.

In one embodiment, the maximum threshold is the maximum column weight of the check matrix H, and the minimum threshold is not less than one half of the column weight of the check matrix H.

In this embodiment, the threshold may be dynamically updated by the roll-over algorithm, the threshold may be updated by using a method of counting the number of roll-over times, and the dynamic threshold may be used to accelerate the convergence rate of the bit roll-over algorithm.

In one embodiment, after determining the error equation sequence according to the check sequence and the check matrix, the method further includes: and comparing the code word sequence with corresponding elements in the hard decision sequence, and if the code word sequence is different from the hard decision sequence, adding 1 to the value of the corresponding element in the error equation sequence.

In order to better understand the technical solution of the present application, the following description is given with reference to a specific example, in which the listed details are mainly for the sake of understanding and are not intended to limit the scope of the present application.

The application provides a decoding method of 2-bit flipping, the 2-bit flipping algorithm of the application can be suitable for LDPC codes, PL isLength of check bit, CL is code length, CL-PL is information bit length, its check matrix H = [ H = _m,n ]，1≤m≤PL，1≤n≤CL。

FIG. 3 is an AWGN flow chart, the specific implementation is as follows:

1) Inputting a sequence: CX = [ CX ] ₁ ,cx ₂ ,...,cx _CL ]

Gaussian white noise sequence: w = [ W = ₁ ,w ₂ ,...,w _CL ]

BPSK modulation sequence: b = [ B ] ₁ ,b ₂ ,...,b _CL ]

The channel output sequence is as follows: r = [ R ] ₁ ,r ₂ ,...,r _CL ]

And (3) quantization sequence: q = [ Q ] ₁ ,q ₂ ,...,q _CL ]

Outputting a sequence: CY = [ CY = ₁ ,cy ₂ ,...,cy _CL ]

2) The input sequence CX is modulated by binary amplitude keying (BPSK) to obtain a BPSK modulation sequence B, wherein B _n ＝1-2cx _n ，1≤n≤CL。

3) The Gaussian white noise (WGN) sequence W and the BPSK modulation sequence B enter into additive Gaussian white noise (AWGN) with the mean value of 0 and the variance of sigma to obtain a channel output sequence R, wherein R _n ＝b _n +w _n ，1≤n≤CL。

4) And the channel output sequence enters a quantization module to obtain LLR values of corresponding bit widths to obtain an output sequence CY. For example, 1bit quantization will convert r _n Quantisation to a value between 0 and 1 and 2bit quantisation will quantise r _n Quantized to a value between 0, 1, 2 and 3.

5) The output sequence CY is the input data of the LDPC code decoder.

6) When AWGN superimposed noise is used in the invention, the output sequence CY uses a 1-bit quantization sequence, and the 1-bit quantization sequence is mapped into a 2-bit internal operation sequence during LDPC decoding.

FIG. 4 is an overall flow chart of the 2-bit flipping algorithm, which is implemented as follows:

1) Inputting data:

LDPC code correctionExperience matrix H = [ H = _m,n ]，1≤m≤PL，1≤n≤CL。

Code word sequence C: the codeword sequence has CL elements in total, and is marked as C = [ C = ₁ ,c ₂ ,...,c _CL ]The values of the elements are only 0 and 1. The codeword sequence comes from a device such as flash memory or is modeled using AWGN.

Outputting data:

hard decision sequence Z: the hard decision sequence has a total of CL elements, denoted as Z = [ Z ] ₁ ,z ₂ ,...,z _CL ]The element values are only 0 and 1. And outputting a hard decision sequence Z after the decoding of the LDPC code is successful.

Internal data:

soft information sequence: the soft information sequence has a total of CL elements, and is marked as X = [ X = [ X ] ₁ ,x ₂ ,...,x _CL ]The values of the elements are 0, 1, 2 and 3.

And (3) checking a sequence S: the check sequence has a total of PL elements, and is denoted as S = [ S ] ₁ ,s ₂ ,...,s _PL ]The values of the elements are only 0 and 1.

Error equation sequence F: the sequence of error equations has a total of CL elements, denoted F = [ F = [ ] ₁ ,f ₂ ,...,f _CL ]And the element value is more than or equal to 0.

flip _ count: the number of turns of the hard decision sequence elements in each iteration.

T: the dynamic threshold changes with the increase of the iteration number.

2) Parameter settings (for reference only):

CL: codeword length, reference value 18400

PL: check bit length, reference value 1849

And MaxIT: maximum number of iterations, reference value 50

Tmin: dynamic threshold minimum, reference 3

Tmax: dynamic threshold maximum, reference value 5

3) Starting decoding: assigning the code word sequence C to a hard decision sequence Z, and shifting the elements in the hard decision sequence Z by 1bit to the left to obtain a soft information sequence X, namely X = [ Z ] ₁ <<1,z ₂ <<1,...,z _CL <<1]，T＝T _max . Step 4) is entered.

4) Calculating a check sequence S according to the hard decision sequence Z and the check matrix H,

if the element values in the check sequence S are all 0, decoding is successful, and the current hard decision sequence Y is taken as decoding output; if the element values in the check sequence S are not all 0 and reach the maximum iteration times MaxIT, the decoding fails; otherwise step 5) is entered.

5) For each element in the hard decision sequence Z, a sequence of error equations F is calculated in which it participates,

proceed to step 6).

6) If f is _n If T is greater than T, the corresponding element x in the soft information sequence is turned according to a 2-bit turning rule (as described in detail below) _n Else, element x in the soft information sequence _n Remain unchanged.

Proceed to step 7).

7) FIG. 5 is a process diagram showing a dynamic threshold update rule, wherein X in the soft information sequence X is counted during each iteration _n The number of times of the upper bits being turned over, if the number of times of turning over is 0 and T = = T _min Then T = T _min (ii) a If the number of flipping times is 0 and T>T _min If T = T-1; if the number of inversions is not 0 and T = = T _max Then T = T _max (ii) a If the number of flipping times is not 0 and T<T _max Then T = T +1.

And starting the next iteration and entering the step 4).

The 2-bit flipping algorithm can also be applied to QC-LDPC codes, and a mother matrix of a check matrix of the QC-LDPC codes is assumed to be (M, N, L), wherein M is the row number of the mother matrix of the check matrix of the QC-LDPC codes; n is the number of columns of the mother matrix; l is the sub-matrix size. For QC-LDPC codes, the codeword length is N × L, the information bit length is (N-M) × L and the check bit length is M × L.

The bit flipping decoding algorithm in the specification is based on column distribution, each iteration is divided into N columns, and each sub-calculation process calculates all effective points corresponding to one column in a QC-LDPC mother matrix.

The specification has four design schemes, namely an original scheme, a modified scheme 1, a modified scheme 2 and a modified scheme 3, and the specific design contents are shown in the following table I.

TABLE A description of four design scenarios

(one) original scheme: 1bit flip, the flow chart of which is shown with reference to fig. 6.

1) Inputting data:

QC-LDPC code check matrix mother matrix H = [ H ] _m,n ]，1≤m≤M，1≤n≤N；

Code word sequence C: dividing the code word sequence C into one group according to each L elements, dividing the code word sequence into N groups in total, and recording the grouped code word sequence as C = [ C ] ₁ ,c ₂ ,...,c _N ]. The codeword sequence comes from a device such as flash memory or is modeled using AWGN.

Outputting data:

hard decision sequence Z: dividing the hard decision sequence Z into one group according to each L elements, dividing the hard decision sequence into N groups in total, and recording the grouped hard decision sequence as Z = [ Z ] ₁ ,z ₂ ,...,z _N ]. And outputting a hard decision sequence Z after the QC-LDPC code decoding is successful.

Internal data:

and (3) checking a sequence S: dividing the check sequence S into one group according to each L elements, totally dividing the check sequence S into M groups, and dividing the check sequence S into the groupsThe sequence is marked as S = [ S ] ₁ ,s ₂ ,...,s _M ]. The values of elements in the check sequence are only 0 and 1.

Checking the shift sequence SS: dividing the check shift sequence SS into one group according to each L element, dividing the check shift sequence SS into M groups in total, and recording the grouped check shift sequence as SS = [ SS ] ₁ ,ss ₂ ,...,ss _M ]. The elements in the check shift sequence take values of only 0 and 1.

Checking the buffer sequence SF: dividing the check cache sequence SF into a group according to each L element, dividing the check cache sequence SF into M groups in total, and recording the grouped check cache sequence as SF = [ SF ] ₁ ,sf ₂ ,...,sf _M ]. The values of the elements in the check cache sequence are only 0 and 1.

Soft information sequence X: dividing the soft information sequence X into one group according to each L element, and dividing the soft information sequence into N groups in total, and recording the soft information sequence after grouping as X = [ X ] ₁ ,x ₂ ,...,x _N ]. The elements of the soft information sequence take values of 0, 1, 2 and 3.

Error equation sequence F: dividing the error equation sequence F into one group according to each L elements, and dividing the error equation sequence F into N groups in total, and recording the error equation sequence after grouping as F = [ F [ ] ₁ ,f ₂ ,...,f _N ]. The values of the elements of the error equation sequence are more than or equal to 0.

Hard decision shift sequence ZS/ZSS: dividing the hard decision shift sequences ZS/ZSS into one group according to each L elements, dividing the hard decision shift sequences into M groups in total, and recording the hard decision shift sequences after grouping as ZS = [ ZS ] ₁ ,zs ₂ ,...,zs _M ]/ZSS＝[zss ₁ ,zss ₂ ,...,zss _M ]. The elements in the hard decision shifted sequence take values of only 0 and 1. Where ZS is the hard decision shift sequence before bit flipping and ZSs is the hard decision shift sequence after bit flipping.

Hard decision buffer sequence ZP: dividing the hard decision cache sequence ZP into a group according to each L element, totally dividing the hard decision cache sequence ZP into N groups, and recording the grouped hard decision sequence ZP = [ ZP ] ₁ ,zp ₂ ,...,zp _N ]. The values of elements in the hard decision buffer sequence are only 0 and 1.

flip _ count: and the turnover times of the sequence elements are judged in each iteration.

T: the dynamic threshold changes with the increase of the iteration number.

2) Parameter settings (for reference only):

m: number of columns of QC-LDPC mother matrix, reference value 5

N: row number of QC-LDPC mother matrix, reference value 50

Z: QC-LDPC mother matrix submatrix size, reference value 368

And MaxIT: maximum number of iterations, reference value 50

T _min : dynamic threshold minimum, reference 3

T _max : dynamic threshold maximum, reference value 5

3) Starting decoding:

the codeword sequence C is assigned to the hard decision sequence Z, T = T _max . Step 4) is entered.

4) Pre-storing a check sequence:

referring to fig. 7, the check sequence S is first set to 0 (the check sequence S can be considered as a 0 column);

column 1, hard decision sequence input group 1 element z ₁ . First update ZS if h _1,1 Is the effective value, zs ₁ The vector being equal to z ₁ Circulation left shift h _1,1 Bit, else zs ₁ =0; if h is _2,1 Is an effective value, zs ₂ Is equal to z ₁ Circulation left shift h _2,1 Bit, else zs ₂ =0; by analogy, if h _M,1 Is the effective value, zs _M Is equal to z ₁ Circulation left shift h _M,1 Bit, else zs _M And =0. And then updating S, and performing exclusive OR on the check sequence of the previous column and the hard decision shift sequence of the current column to obtain the check sequence of the current column, namely S = S ^ ZS.

Column 2, hard decision sequence input group 2 element z ₂ . First update ZS if h _1,2 Is the effective value, zs ₁ Is equal to z ₂ Circulation left shift h _1,2 Bit, else zs ₁ =0; if h is _2,2 Is the effective value, zs ₂ Is equal to z ₂ Circulation left shift h _2,2 Bit, else zs ₂ =0; by analogy, if h _M,2 Is the effective value, zs _M Is equal to z ₂ Circulation left shift h _M,2 Bit, else zs _M =0. And then updating S, and performing exclusive OR on the check sequence of the previous column and the hard decision shift sequence of the current column to obtain the check sequence of the current column, namely S = S ^ ZS.

And so on.

Nth column, hard decision sequence input Nth group element z _N . First update ZS if h _1,N Is the effective value, zs ₁ Is equal to z _N Circulation left shift h _1,N Bit, else zs ₁ =0; if h is _2,N Is the effective value, zs ₂ Is equal to z _N Circulation left shift h _2,N Bit, else zs ₂ =0; by analogy, if h _M,N Is the effective value, zs _M Is equal to z _N Circulation left shift h _M,N Bit, else zs _M =0. And then updating S, and performing exclusive OR on the check sequence of the previous column and the hard decision shift sequence of the current column to obtain the check sequence of the current column, namely S = S ^ ZS.

Step 5) is entered.

5) And (3) judging in advance: if the element values in the check sequence S are all 0, decoding is successful, and a hard decision sequence Z is output; if the element values in the check sequence S are not all 0 and reach the maximum iteration times MaxIT, the decoding fails; otherwise step 6) is entered.

6) Initializing cache data: the flip _ count is set to 0 and the check buffer sequence SF is set to 0 (which can be regarded as the check buffer sequence in column 0), and the process proceeds to step 7).

7) Iterative computation (sequentially compute column 1, column 2 through column N):

calculate the nth column (1. Ltoreq. N. Ltoreq.N):

first step update SS if h _1,n Is an effective value, ss ₁ Is equal to s ₁ Circulation right shift h _1,n Bit, else ss ₁ =0; if h is _2,n Is an effective value, ss ₂ Is equal to s ₂ Circulation right shift h _2,n Bit, otherwise ss ₂ =0; by analogy, if h _M,n Is an effective value, ss _M Is equal to s _M Circulation right shift h _M,n Bit, else ss _M ＝0。

Second step update f _n Referring to FIG. 8, the corresponding bits of each group of elements in the check shift sequence are added to obtain F in the error equation sequence F _n I.e. f _n ＝ss ₁ +ss ₂ +...+ss _M 。

The third step is to flip z in the hard decision sequence _n If f is an element of _n If the value of the element in (1) is greater than or equal to the dynamic threshold T, then z _n The corresponding element value in (1) is xored with 1 and the flip _ count is incremented by 1.

The fourth step is to update the hard decision shift sequence ZS if h _1,n Is the effective value, zs ₁ Is equal to z _n Circulation left shift h _1,n Bit, else zs ₁ =0; if h is _2,n Is an effective value, zs ₂ Is equal to z _n Circulation left shift h _2,n Bit, else zs ₂ =0; by analogy, if h _M,n Is an effective value, zs _M Is equal to z _n Circulation left shift h _M,n Bit, else zs _M ＝0。

And step five, updating the check cache sequence SF, and performing exclusive or on the check cache sequence of the previous column and the hard decision shift sequence of the current column to obtain the check cache sequence of the current column, namely SF = SF ^ ZS.

After the nth column calculation is completed, the process proceeds to step 8).

8) And (3) dynamic threshold updating: referring again to fig. 5, if flip _ count = =0 and T = = T _min Then T = T _min ；

If flip _ count = =0 and T>T _min Then T = T-1; if the flip _ count! =0 and T = = T _max Then T = T _max ；

If the flip _ count! =0 and T<T _max Then T = T +1. Proceed to step 9).

9) Updating the check sequence: the check buffer sequence is assigned to the check sequence, i.e. S = SF. Step 5) is entered.

(II) improvement scheme 1: a 2bit roll-over rule is added and the flow chart is shown with reference to fig. 9.

The modified version 1 is substantially the same as the original version in steps 1) to 2), 4) to 6) and 8) to 9), the important difference being in steps 3 and 7).

3) And (3) starting decoding:

the codeword sequence C is assigned to a hard decision sequence Z, the elements in which are mapped to the elements in the soft information sequence, i.e. 0 becomes 1,1 becomes 3, t = _max . Step 4) is entered.

7) Iterative calculation (sequentially calculating the 1 st, 2 nd, through nth columns):

calculate the nth column (1. Ltoreq. N. Ltoreq.N):

first step update SS if h _1,n Is an effective value, ss ₁ Is equal to s ₁ Circulation right shift h _1,n Bit, otherwise ss ₁ =0; if h is _2,n Is an effective value, ss ₂ Is equal to s ₂ Circulation right shift h _2,n Bit, else ss ₂ =0; by analogy, if h _M,n Is an effective value, ss _M Is equal to s _M Circulation right shift h _M,n Bit, else ss _M ＝0。

Second step update f _n Adding corresponding bits of each group of elements in the check shift sequence to obtain F in the error equation sequence F _n Vector, i.e. f _n ＝ss ₁ +ss ₂ +...+ss _M 。

The third step is to flip the x in the soft information sequence _n For x, for _n If the dynamic threshold value T is equal to the dynamic threshold maximum value T _max Flip x according to 2bit flip rule 1 _n And z _n Otherwise, flip x by 2bit according to 2bit flip rule _n And z _n Each element of (1). If the flip is made, the flip count is updated.

2bit roll-over rule 1: if f is _n If the value of the element in (1) is greater than or equal to the dynamic threshold T, then x _n The value of the corresponding element in (1) is exclusive-or (high-order low-order data is inverted at the same time) with (3), z _n The corresponding element value in (1) is xored with 1 and the flip _ count is incremented by 1.

2bit roll over rule 2: if f is _n If the value of the element in (1) is greater than or equal to the dynamic threshold T, then according to x _n In (1) corresponding toThe element values are flipped. If x _n Is 0, then x _n The value of the corresponding element in (1) is updated to 2,z _n The corresponding element value in the table is XOR-ed with 1, and the flip _ count is added with 1; if x _n Is 1, then x _n The value of the corresponding element in (1) is updated to 0 _n The corresponding element value in (1) is kept unchanged, and the flip _ count is kept unchanged; if x _n Is 2, then x _n The value of the corresponding element in (1) is updated to 0 _n The corresponding element value in the list is subjected to exclusive OR with 1, and the flip _ count is added with 1; if x _n Is 3, then x _n The value of the corresponding element in (1) is updated to 2,z _n The corresponding element value in (1) remains unchanged and the flip _ count remains unchanged.

The fourth step is to update the hard decision shift sequence ZS if h _1,n Is an effective value, zs ₁ Is equal to z _n Circulation left shift h _1,n Bit, else zs ₁ =0; if h is _2,n Is the effective value, zs ₂ Is equal to z _n Circulation left shift h _2,n Bit, else zs ₂ =0; by analogy, if h _M,n Is the effective value, zs _M Is equal to z _n Circulation left shift h _M,n Bit, else zs _M ＝0。

And step five, updating the check cache sequence SF, and performing exclusive or on the check cache sequence of the previous column and the hard decision shift sequence of the current column to obtain the check cache sequence of the current column, namely SF = SF ^ ZS.

After the nth column calculation is completed, the process proceeds to step 8).

2bit roll-over rule:

(1) when the QC-LDPC internal operation data is 2-bit data, the high-order data determines the storage data thereof, and the low-order data determines the data reliability thereof. The corresponding stored data and data reliability for different 2-bit data are shown in the following table two.

2bit data	Storing data	Data confidence
				0	0	0 (Low)
1	0	1 (high)
			2	1	0 (Low)
3	1	1 (high)

Table two 2bit data

(2) When the dynamic threshold T is equal to the maximum value T of the dynamic threshold _max I.e., T = = Tmax,

if the elements in the error equation sequence fn are more than or equal to T, the soft information sequence x is turned over according to a 2-bit turning rule 1 _n Otherwise, the corresponding element remains unchanged.

(3) When the dynamic threshold T is smaller than the maximum value T of the dynamic threshold _max I.e. T<Tmax is the time for the operation of the system,

if the sequence of error equations f _n The element in (2) is more than or equal to T, and the soft information sequence x is turned according to a 2bit turning rule 2 _n Otherwise, the corresponding element in (1) remains unchanged.

Fig. 10 is a 2bit roll over rule 1: if the preset threshold is equal to the maximum threshold value, judging whether the auxiliary bit of the corresponding element in the soft information sequence is in a first state, if so, turning over the auxiliary bit and the sign bit of the corresponding element in the soft information sequence. Specifically, when the lower bit is 1, if it is "11", the inversion is "00", and if it is "01", the inversion is "10".

Fig. 11 is a 2bit roll-over rule 2: when the internal operation data is 2-bit data, the high-order data determines the storage data, and the low-order data determines the reliability of the storage data. When the inversion condition is met, the storage data with high reliability can invert low bits to become storage data with low reliability, and the storage data with low reliability can invert high bits to become new storage data with low reliability. Specifically, the method comprises the following steps: determining the lower bits of 2-bit internal operation data, and turning to be 01 if the lower bits are 0 and turning to be 11 if the lower bits are 10; when the low order is 1, if "01", the inversion is "11", and if "11", the inversion is "01". It is to be understood that in another embodiment, where a logical 1 is used to indicate that the confidence level is high and a logical 0 is used to indicate that the confidence level is high, when the lower bit is 1, if "01", the inversion is "00", if "11", the inversion is "10", when the lower bit is 0, the inversion is "10", and if "10", the inversion is "00".

(III) improvement scheme 2: the roll-over node votes on the sequence of error equations, the flow chart of which is shown with reference to fig. 12.

The modified version 2 is substantially the same as the original version in steps 1) to 2), 4) to 6) and 8) to 9), the important difference being in steps 3 and 7).

3) Starting decoding:

assigning the code word sequence C to a hard decision sequence Z, supplementing logic 0 to the lower bits of elements in the code word sequence to obtain a soft information sequence, namely changing 0 into 1,1 into 3, and changing T = T _max . Step 4) is entered.

7) Iterative calculation (sequentially calculating the 1 st, 2 nd, through nth columns):

calculate the nth column (1. Ltoreq. N. Ltoreq.N):

first step update SS if h _1,n Is an effective value, ss ₁ Is equal to s ₁ Circulation right shift h _1,n Bit noThen ss ₁ =0; if h is _2,n Is an effective value, ss ₂ Is equal to s ₂ Circulation right shift h _2,n Bit, otherwise ss ₂ =0; by analogy, if h _M,n Is an effective value, ss _M Is equal to s _M Circulation right shift h _M,n Bit, otherwise ss _M ＝0。

Second step of updating f _n Adding corresponding bits of each group of elements in the check shift sequence to obtain F in the error equation sequence F _n I.e. f _n ＝ss ₁ +ss ₂ +...+ss _M 。

The third step is to flip the node and vote for the error equation sequence, as shown in FIG. 13, to compare c in the codeword sequence _n And a hard decision sequence z _n If the two are not the same, F in the error equation sequence F _n Plus 1 for the corresponding element value.

The fourth step is to flip the x in the soft information sequence _n For x, for _n If the dynamic threshold value T is equal to the dynamic threshold maximum value T _max Flip x according to 2bit flip rule 1 _n And z _n Otherwise, x is flipped by 2 according to 2bit flipping rules _n And z _n Each element of (1). If it is flipped, the flip count is updated.

The fifth step is to update the hard decision shift sequence ZS if h _1,n Is the effective value, zs ₁ Is equal to z _n Circulation left shift h _1,n Bit, else zs ₁ =0; if h is _2,n Is the effective value, zs ₂ Is equal to z _n Circulation left shift h _2,n Bit, else zs ₂ =0; by analogy, if h _M,n Is the effective value, zs _M Is equal to z _n Circulation left shift h _M,n Bit, else zs _M ＝0。

And the sixth step is to update the check cache sequence SF, and the check cache sequence of the previous column is XOR-ed with the hard decision shift sequence of the current column to obtain the check cache sequence of the current column, namely SF = SF ^ ZS.

After the nth column calculation is completed, the process proceeds to step 8).

(IV) improvement scheme 3: the modification 2 updates the check sequence and the error equation sequence after all columns of data are turned over, and the modification 3 updates the check sequence and the error equation sequence after each column of data is turned over, and the flowchart thereof is shown with reference to fig. 14.

The modified version 3 is substantially the same as the original version in steps 1) to 2) and 4) to 6), the important differences being in steps 3), 7) and 8).

3) Starting decoding:

assigning the code word sequence C to a hard decision sequence Z, supplementing logic 0 to the lower bits of elements in the code word sequence to obtain a soft information sequence, namely changing 0 into 1,1 into 3, and changing T = T _max . Step 4) is entered.

7) Iterative computation (sequentially compute column 1, column 2 through column N):

calculate the nth column (1. Ltoreq. N. Ltoreq.N), as shown with reference to FIG. 15:

the first step is to update SS: if h is _1,n Is an effective value, ss ₁ Is equal to s ₁ Circulation right shift h _1,n Bit, otherwise ss ₁ =0; if h is _2,n Is an effective value, ss ₂ Is equal to s ₂ Circulation right shift h _2,n Bit, otherwise ss ₂ =0; by analogy, if h _M,n Is an effective value, ss _M Is equal to s _M Circulation right shift h _M,n Bit, otherwise ss _M ＝0。

Second step update f _n : adding corresponding bits of each group of elements in the check shift sequence to obtain F in the error equation sequence F _n I.e. f _n ＝ss ₁ +ss ₂ +...+ss _M 。

The third step is to count the turning nodes and compare c in the code word sequence _n And a hard decision sequence z _n If the two are not the same, F in the error equation sequence F _n Plus 1 for the corresponding element value.

The fourth step is to store the nth group element Z in the hard decision sequence Z _n Is assigned to the nth group element in the hard decision cache sequence ZP, namely ZP _n ＝z _n 。

The fifth step is to flip x in the soft information sequence _n The elements (c): for x _n If the dynamic threshold value T is equal to the dynamic threshold maximum value T _max Flip x according to 2bit flip rule 1 _n And z _n Otherwise, x is flipped by 2 according to 2bit flipping rules _n And z _n Each element of (a). If the flip is made, the flip count is updated.

The sixth step is to update the hard decision shift sequence ZS after the bit flipping: if h is _1,n Is the effective value, zs ₁ Is equal to z _n Circulation left shift h _1,n Bit, else zs ₁ =0; if h is _2,n Is the effective value, zs ₂ Is equal to z _n Circulation left shift h _2,n Bit, else zs ₂ =0; by analogy, if h _M,n Is the effective value, zs _M Is equal to z _n Circulation left shift h _M,n Bit, else zs _M ＝0。

The seventh step is to update the hard decision shift sequence ZSS before the bit flipping: if h is _1,n Is an effective value, zss ₁ Is equal to zp _n Circulation left shift h _1,n Bit, else zss ₁ =0; if h is _2,n Is an effective value, zss ₂ Is equal to zp _n Circulation left shift h _2,n Bit, else zss ₂ =0; by analogy, if h _M,n Is an effective value, zss _M Is equal to zp _n Circulation left shift h _M,n Bit, else zss _M ＝0。

The eighth step is to update the check sequence S: and the check sequence of the previous column, the hard decision shift sequence before bit flipping of the current column and the hard decision shift sequence after bit flipping of the current column are subjected to exclusive OR to obtain the check sequence of the current column, namely S = S ^ ZSS ^ ZS.

The ninth step is decision ahead: if the check sequence S = =0, decoding is successful, and a hard decision sequence Z is output, otherwise, the next column calculation is carried out until the Nth column.

Column N calculation is complete and S! =0, proceed to step 8).

8) And (3) dynamic threshold updating: if flip _ count = =0 and T = = T _min Then T = T _min (ii) a If flip _ count = =0 and T>T _min Then T = T-1; if the flip _ count! =0 and T = = T _max Then T = T _max (ii) a If the flip _ count! =0 and T<T _max Then T = T +1. Proceed to step 6).

Fig. 16 shows a signal-to-noise ratio versus bit error rate curve in an embodiment of the present application. FIG. 17 shows a signal-to-noise ratio versus iteration number plot in one embodiment of the present application. As can be seen from fig. 16 and 17:

1. BF 1bit algorithm (original scheme) and BF 2bit algorithm (improved scheme 1)

The bit error rate of the BF 1bit algorithm is lower than that of the BF 2bit algorithm, but the iteration times of the BF 1bit algorithm are slightly higher than that of the BF 2bit algorithm, so that the BF 2bit algorithm is used for improving the error correction capability at the cost of slightly improving the iteration times compared with the BF 1bit algorithm.

2. BF 2bit algorithm (modified version 1) and BF 2bit modify1 (modified version 2)

When the bit error rate of the improved scheme 2 is lower than that of the improved scheme 1,5.3 & sSNR & lt 5.7, the iteration number of the improved scheme 2 is slightly lower than that of the improved scheme 1, and when the SNR & lt 5.7, the iteration number of the improved scheme 2 is slightly lower than that of the improved scheme 1, so that the improved scheme 2 algorithm can improve the error correction capability and slightly reduce the iteration number compared with the improved scheme 1 algorithm.

3. BF 2bit algorithm (modified scheme 1) and BF 2bit modify3 (modified scheme 3)

The bit error rate and the iteration times of the improved scheme 3 are far lower than those of the improved scheme 1, so that the error correction capability of the improved scheme 3 algorithm can be greatly improved and the iteration times can be reduced compared with the improved scheme 1 algorithm.

The second embodiment of the present application further discloses a 2-bit flipping decoding system, which includes: the device comprises an acquisition unit, a calculation unit, a verification unit and a turnover unit. Wherein:

the acquisition unit is used for acquiring a soft information sequence, each element in the soft information sequence comprises a sign bit and an auxiliary bit, and the sign bit of each element in the soft information sequence forms a hard decision sequence.

And the calculation unit is used for calculating a check sequence according to the hard decision sequence and the check matrix.

The check unit is used for determining an error equation sequence according to the check sequence and the check matrix.

The flipping unit is used for further judging whether an auxiliary bit of a corresponding element in the soft information sequence is in a first state or not for an element which is greater than or equal to a preset threshold in the error equation sequence, flipping the auxiliary bit to be in a second state if the auxiliary bit is in the first state, and flipping a sign bit of the corresponding element in the soft information sequence if the auxiliary bit is not in the first state.

The first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment may be applied to the present embodiment, and the technical details in the present embodiment may also be applied to the first embodiment.

It should be noted that, as will be understood by those skilled in the art, the implementation functions of the modules shown in the embodiment of the 2-bit flipping decoding system can be understood by referring to the related description of the 2-bit flipping decoding method. The functions of the modules shown in the above embodiment of the 2-bit flipping decoding system can be implemented by a program (executable instructions) running on a processor, and can also be implemented by a specific logic circuit. In the embodiment of the present application, the 2-bit flipping decoding system may also be stored in a computer readable storage medium if it is implemented in the form of a software functional module and sold or used as an independent product. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. Multiple, etc. expressions include 2, 2 2 kinds and more than 2, more than 2 times and more than 2 kinds.

Accordingly, the present application also provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, the computer-executable instructions implement the method embodiments of the present application. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable storage medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

All documents mentioned in this specification are to be considered as being integrally included in the disclosure of the present application so as to be able to be a basis for modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.

In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Claims (12)

1. A 2-bit flipped decoding method, comprising:

acquiring a soft information sequence, wherein each element in the soft information sequence comprises a sign bit and an auxiliary bit, and the sign bit of each element in the soft information sequence forms a hard decision sequence;

calculating a check sequence according to the hard decision sequence and the check matrix;

determining an error equation sequence according to the check sequence and the check matrix; and

and for the elements which are greater than or equal to a preset threshold in the error equation sequence, further judging whether the auxiliary bit of the corresponding element in the soft information sequence is in a first state, if so, turning the auxiliary bit to be in a second state, and if not, turning the sign bit of the corresponding element in the soft information sequence.

2. The decoding method of claim 1, wherein the auxiliary bit represents a confidence level of the sign bit, the first state having a higher confidence level than the second state.

3. The decoding method of claim 1, wherein the step of obtaining the soft information sequence further comprises: a codeword sequence is obtained, and the lower bits of each element in the codeword sequence are supplemented with another auxiliary bit to generate the soft information sequence.

4. The decoding method of claim 3, after determining a sequence of error equations from the check sequence and the check matrix, further comprising: and comparing the code word sequence with corresponding elements in the hard decision sequence, and if the code word sequence is different from the hard decision sequence, adding 1 to the value of the corresponding element in the error equation sequence.

5. The decoding method of claim 1, further comprising:

counting the number of inverted sign bits of each element in the soft information sequence in the iteration process;

judging whether the overturned count is zero or not;

if the threshold value is zero, judging whether the preset threshold value is equal to a minimum threshold value, and if the threshold value is not the minimum threshold value, subtracting 1 from the preset threshold value; and

if not, judging whether the preset threshold is equal to the maximum threshold value or not, and if not, adding 1 to the preset threshold.

6. The decoding method of claim 5, wherein the maximum threshold is a maximum column weight of the check matrix, and the minimum threshold is not less than one-half of the column weight of the check matrix.

7. The decoding method of claim 5, wherein if the predetermined threshold is equal to the maximum threshold, determining whether the auxiliary bit of the corresponding element in the soft information sequence is in the first state, and if so, flipping the auxiliary bit and the sign bit of the corresponding element in the soft information sequence.

8. The decoding method of claim 1, further comprising: updating the check sequence and the error equation sequence after each column of the soft information sequence is flipped.

9. The decoding method of claim 1, wherein the first state is a logic 1 and the second state is a logic 0.

10. The decoding method of claim 1, wherein the hard decision sequence is output if each element value in the check sequence is 0.

11. A 2-bit flipped decoding system, comprising:

the soft information processing device comprises an acquisition unit, a decision unit and a decision unit, wherein the acquisition unit is used for acquiring a soft information sequence, each element in the soft information sequence comprises a sign bit and an auxiliary bit, and the sign bit of each element in the soft information sequence forms a hard decision sequence;

the calculation unit is used for calculating a check sequence according to the hard decision sequence and the check matrix;

the check unit is used for determining an error equation sequence according to the check sequence and the check matrix; and

and the overturning unit is used for further judging whether the auxiliary bit of the corresponding element in the soft information sequence is in a first state or not for the element which is greater than or equal to the preset threshold in the error equation sequence, if so, overturning the auxiliary bit to be in a second state, and if not, overturning the sign bit of the corresponding element in the soft information sequence.

12. A computer-readable storage medium having computer-executable instructions stored therein, which when executed by a processor implement the steps in the method of any one of claims 1 to 10.

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