CN115549666A

CN115549666A - Radio frequency switch control circuit

Info

Publication number: CN115549666A
Application number: CN202210741917.1A
Authority: CN
Inventors: S·纳加拉詹; A·德瓦拉杰; F·G·巴尔蒂诺; 崔允荣
Original assignee: Skyworks Solutions Inc
Current assignee: Skyworks Solutions Inc
Priority date: 2021-06-28
Filing date: 2022-06-27
Publication date: 2022-12-30
Also published as: KR20230001545A; US11942972B2; TW202308334A; US20240195439A1; DE102022206458A1; US20220416816A1; JP2023007443A; GB202208730D0; GB2610028A

Abstract

Apparatus and methods for Radio Frequency (RF) switch control are provided. In some embodiments, a level shifter for a radio frequency switch includes: a first level-shifting n-type transistor; a first cascode n-type transistor in series with the first level-shifted n-type transistor between a negative charge pump voltage and a first output providing a first switch control signal; a first level-shifted p-type transistor; a first cascode p-type transistor in series with the first level-shifting p-type transistor between the positive charge pump voltage and the first output; and a second cascode p-type transistor between the regulation voltage and the gate of the first level-shifted n-type transistor and controlled by the first switch enable signal.

Description

Radio frequency switch control circuit

Technical Field

Embodiments of the present invention relate to electronic systems, and more particularly, to Radio Frequency (RF) communication systems.

Background

Radio Frequency (RF) communication systems may be used to transmit and/or receive signals at a wide range of frequencies. For example, the RF communication system may be used to wirelessly communicate RF signals in a frequency range of about 30kHz to 300GHz, such as in a range of about 400MHz to about 7.125GHz in a frequency range 1 (FR 1) for a fifth generation (5G) communication standard, or in a range of about 24.250GHz to about 71.000GHz in a frequency range 2 (FR 2) for a 5G communication standard.

Examples of RF communication systems include, but are not limited to, mobile phones, tablets, base stations, network access points, customer Premises Equipment (CPE), laptops, and wearable electronics.

Disclosure of Invention

In certain embodiments, the present application relates to a mobile device. The mobile device includes: a power management system includes a positive charge pump configured to generate a positive charge pump voltage, a negative charge pump configured to generate a negative charge pump voltage, and a voltage regulator configured to generate a regulated voltage. The mobile device further comprises: a front-end system comprising a radio frequency switch controlled by a first switch control signal; and a level shifter operable to level shift the first switch enable signal to produce a first switch control signal at the first output. The level shifter includes: a first level-shifting n-type transistor and a first cascode (cascode) n-type transistor in series between the negative charge pump voltage and the first output, a first level-shifting p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output, and a second cascode p-type transistor between the regulation voltage and a gate of the first level-shifting n-type transistor and controlled by the first switch enable signal.

In some embodiments, the level shifter is further operable to level shift a second switch enable signal to produce a second switch control signal at a second output, the second switch enable signal having a complementary polarity to the first switch enable signal. According to a number of embodiments, the level shifter further comprises: a second level-shifted n-type transistor in series with the second cascode p-type transistor between the regulation voltage and the negative charge-pump voltage; a third cascode p-type transistor; and a third level-shifted n-type transistor in series with the third cascode p-type transistor between the regulation voltage and the negative charge-pump voltage. According to various embodiments, the level shifter further comprises: a fourth level-shifted n-type transistor and a second cascode n-type transistor in series between the second output and the negative charge-pump voltage, and a second level-shifted p-type transistor and a fourth cascode p-type transistor in series between the positive charge-pump voltage and the second output.

In several embodiments, the head-end system further includes a power amplifier configured to provide a radio frequency signal to the radio frequency switch.

In some embodiments, the power management system further comprises: a charge pump clock generator comprising a multiphase oscillator configured to generate a plurality of oscillator clock signals; and a clock phase logic and combination circuit configured to process a plurality of oscillator clock signals to generate a first clock signal having a frequency higher than an oscillation frequency of the multiphase oscillator, the first clock signal operable to control at least one of the positive charge pump or the negative charge pump. According to some embodiments, the clock phase logic and combination circuit is further configured to generate a second clock signal phase offset from the first clock signal, the first clock signal operable to control the positive charge pump and the second clock signal operable to control the negative charge pump.

In certain embodiments, the present application relates to a radio frequency switching system. The radio frequency switch system includes: a radio frequency switch configured to receive a radio frequency signal and controlled by a first switch control signal; a positive charge pump configured to generate a positive charge pump voltage; a negative charge pump configured to generate a negative charge pump voltage; a voltage regulator configured to generate a regulated voltage; and a level shifter operable to level shift a first switch enable signal to produce the first switch control signal at a first output. The level shifter includes: a first level-shifting n-type transistor and a first cascode n-type transistor in series between the negative charge pump voltage and the first output, a first level-shifting p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output, and a second cascode p-type transistor between the regulation voltage and a gate of the first level-shifting n-type transistor and controlled by the first switch enable signal.

In some embodiments, the level shifter is further operable to level shift a second switch enable signal to produce a second switch control signal at a second output, the second switch enable signal having a complementary polarity to the first switch enable signal. According to a number of embodiments, the level shifter further comprises: a second level-shifted n-type transistor in series with the second cascode p-type transistor between the regulation voltage and the negative charge-pump voltage; a third cascode p-type transistor; and a third level-shifted n-type transistor in series with the third cascode p-type transistor between the regulation voltage and the negative charge-pump voltage. According to a number of embodiments, the level shifter further comprises: a fourth level-shifting n-type transistor and a second cascode n-type transistor in series between the negative charge-pump voltage and the second output, and a second level-shifting p-type transistor and a fourth cascode p-type transistor in series between the positive charge-pump voltage and the second output. According to various embodiments, the radio frequency switching system further comprises: a first enable level shift circuit configured to level shift the first switch enable signal to generate a first level shift switch enable signal that controls a gate of the second level shift p-type transistor; and a second enable level shift circuit configured to level shift a second switch enable signal to generate a second level shift switch enable signal that controls a gate of the first level shift p-type transistor. According to several embodiments, the gate of the first cascode p-type transistor and the gate of the fourth cascode p-type transistor are connected to a ground voltage. According to several embodiments, the gate of the second level-shifting n-type transistor and the gate of the fourth level-shifting n-type transistor are connected to the drain of the third level-shifting n-type transistor, and the gate of the first level-shifting n-type transistor and the gate of the third level-shifting n-type transistor are connected to the drain of the second level-shifting n-type transistor. According to various embodiments, the radio frequency switch comprises: a series transistor switch electrically connected between an input terminal and an output terminal and controlled by the first switch control signal; and a shunt (shunt) transistor switch electrically connected between the input terminal and a ground voltage and controlled by the second switch control signal.

In several embodiments, the radio frequency switching system further comprises: a charge pump clock generator comprising a multiphase oscillator configured to generate a plurality of oscillator clock signals; and a clock phase logic and combination circuit configured to process a plurality of oscillator clock signals to generate a first clock signal having a frequency higher than an oscillation frequency of the multiphase oscillator, the first clock signal operable to control at least one of the positive charge pump or the negative charge pump. According to some embodiments, the clock phase logic and combination circuit is further configured to generate a second clock signal phase offset from the first clock signal, the first clock signal operable to control the positive charge pump and the second clock signal operable to control the negative charge pump.

In various embodiments, the voltage regulator is a low dropout regulator.

In certain embodiments, the present application relates to a level shifter for a radio frequency switch. The level shifter includes: a first level-shifting n-type transistor; a first cascode n-type transistor in series with the first level-shifted n-type transistor between a negative charge-pump voltage and a first output providing a first switch control signal; a first level-shifted p-type transistor; a first cascode p-type transistor in series with a first level-shifted p-type transistor between a positive charge pump voltage and the first output; and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifted n-type transistor and controlled by a first switch enable signal.

In several embodiments, the level shifter further comprises: a second level-shifted n-type transistor in series with the second cascode p-type transistor between the regulation voltage and the negative charge-pump voltage; a third cascode p-type transistor; and a third level-shifted n-type transistor in series with the third cascode p-type transistor between the regulation voltage and the negative charge-pump voltage. According to a number of embodiments, the level shifter further comprises: a fourth level-shifting n-type transistor and a second cascode n-type transistor in series between a second output and the negative charge-pump voltage, and a second level-shifting p-type transistor and a fourth cascode p-type transistor in series between the positive charge-pump voltage and the second output. According to various embodiments, the level shifter further comprises: a first enable level shift circuit configured to level shift the first switch enable signal to generate a first level shift switch enable signal that controls a gate of the second level shift p-type transistor; and a second enable level shift circuit configured to level shift a second switch enable signal to generate a second level shift switch enable signal that controls a gate of the first level shift p-type transistor. According to a number of embodiments, the gate of the first cascode p-type transistor and the gate of the fourth cascode p-type transistor are connected to a ground voltage. According to several embodiments, the gate of the second level-shifting n-type transistor and the gate of the fourth level-shifting n-type transistor are connected to the drain of the third level-shifting n-type transistor, and the gate of the first level-shifting n-type transistor and the gate of the third level-shifting n-type transistor are connected to the drain of the second level-shifting n-type transistor.

Drawings

Fig. 1 is a schematic diagram of one example of a communication network.

Fig. 2A is a schematic diagram of one example of a communication link using carrier aggregation.

Fig. 2B illustrates various examples of uplink carrier aggregation for the communication link of fig. 2A.

Fig. 2C illustrates various examples of downlink carrier aggregation for the communication link of fig. 2A.

Fig. 3A is a diagram of one example of a downlink channel using multiple-input and multiple-output (MIMO) communication.

Fig. 3B is a diagram of one example of an uplink channel using MIMO communication.

Fig. 3C is a diagram of another example of an uplink channel using MIMO communication.

Fig. 4 is a schematic block diagram of one embodiment of a power amplifier system.

FIG. 5A is a schematic diagram of one embodiment of a level shifter.

Fig. 5B is a diagram of one example of a waveform of the level shifter of fig. 5A.

FIG. 6 is a schematic diagram of one embodiment of a charge pump.

Figure 7A is a schematic diagram of one embodiment of a charge pump clock generator.

FIG. 7B is a schematic diagram of one embodiment of frequency multiplication logic for a charge pump clock generator.

Fig. 7C is a graph of one example of waveforms for positive and negative charge pumps operating at different clock frequencies.

Fig. 8A is a schematic diagram of another embodiment of a charge pump clock generator.

Fig. 8B is a schematic diagram of another embodiment of frequency multiplication logic of a charge pump clock generator.

Fig. 8C is a diagram of one example of a waveform of the charge pump clock generator.

FIG. 9 is a schematic block diagram of a Radio Frequency (RF) switch system in accordance with one embodiment.

Fig. 10A is a schematic diagram of one embodiment of a packaged module.

Fig. 10B is a cross-sectional schematic view of the packaged module of fig. 10A taken along line 10B-10B.

Fig. 11 is a schematic diagram of an RF switching network according to another embodiment.

FIG. 12 is a schematic diagram of one embodiment of a mobile device.

Detailed Description

The following detailed description of certain embodiments presents various descriptions of specific embodiments. The innovations described herein may, however, be embodied in many different forms, for example, as defined and covered by the claims. In the description, reference is made to the drawings wherein like reference numbers may indicate identical or functionally similar elements. It should be understood that the elements illustrated in the figures are not necessarily drawn to scale. Further, it should be understood that some embodiments may include more elements and/or subsets of the elements illustrated in the figures. Furthermore, some embodiments may include any suitable combination of features in two or more figures.

The International Telecommunications Union (ITU) is a specialized institution of United Nations (UN) responsible for global problems with information and communication technologies, including the global shared use of radio spectrum.

The third generation partnership project (3 GPP) is a collaboration between groups of telecommunication Standards organizations around the world, such as the Association of Radio Industries and Businesses (ARIB), telecommunications Technology Committee (TTC), chinese Communication Standards Association (CCSA), telecommunications Industry Solutions Alliance (Alliance for Telecommunications Industries issues, ATIS), telecommunications Technology Association (TTA), european Telecommunications Standards Institute (European Telecommunications Standards Institute, ETSI), and indian Telecommunications Standards Development Institute (dsi).

Working within the scope of the ITU, the 3GPP develops and maintains specifications for various mobile communication technologies, including, for example, second generation (2G) technologies (e.g., global system for mobile communications (GSM) and enhanced data rates for GSM evolution (EDGE)), third generation (3G) technologies (e.g., universal Mobile Telecommunications System (UMTS) and High Speed Packet Access (HSPA)), and fourth generation (4G) technologies (e.g., long Term Evolution (LTE) and LTE-upgrades).

The technical specifications controlled by the 3GPP may be extended and revised by specification releases that may span many years and specify the breadth of new features and evolutions.

In one example, 3GPP introduced Carrier Aggregation (CA) for LTE in release 10. Although two downlink carriers were originally introduced, 3GPP extended carrier aggregation in release 14 to include up to five downlink carriers and up to three uplink carriers. Examples of other new functions and evolutions provided by the 3GPP release include, but are not limited to, licensed Assisted Access (LAA), enhanced licensed assisted access (eLAA), narrowband Internet of things (navband Internet of things, NB-IOT), vehicle-to-event (V2X), and High Power User Equipment (HPUE).

3GPP introduced stage 1 of the fifth generation (5G) technology in release 15 and stage 2 of the 5G technology in release 16. Subsequent 3GPP releases will further evolve and extend the 5G technology. The 5G technology is also referred to herein as 5G New Radio (NR).

The 5G NR supports and/or plans to support various features such as communication over the millimeter wave spectrum, beamforming capability, high spectral efficiency waveforms, low latency communication, multiple radio parameter set (numerology), and/or non-orthogonal multiple access (NOMA). While such RF functionality provides flexibility to the network and increases user data rates, supporting these functions presents some technical challenges.

The teachings herein are applicable to a wide variety of communication systems, including but not limited to communication systems using Advanced cellular technology, such as LTE-Advanced, LTE-Advanced Pro, and/or 5G NR.

Fig. 1 is a schematic diagram of one example of a communication network 10. The communication network 10 includes various examples of macro cellular base stations 1, small cellular base stations 3, and User Equipment (UE) including a first mobile device 2a, a wirelessly connected automobile 2b, a laptop computer 2c, a fixed wireless device 2d, a wirelessly connected train 2e, a second mobile device 2f, and a third mobile device 2g.

Although specific examples of base stations and user equipment are illustrated in fig. 1, the communication network may include a wide variety of types and/or numbers of base stations and user equipment.

For example, in the example shown, the communication network 10 comprises a macrocell base station 1 and a microcellular base station 3. The small cell base station 3 may operate at relatively lower power, shorter distance and/or fewer concurrent users relative to the macro cell base station 1. The small cell base station 3 may also be referred to as a femtocell (femtocell), a picocell (picocell), or a microcell (microcell). Although communication network 10 is illustrated as including two base stations, communication network 10 may be implemented to include more or fewer base stations and/or other types of base stations.

Although various examples of user equipment are shown, the teachings herein are applicable to a wide variety of user equipment, including but not limited to mobile phones, tablets, laptops, ioT devices, wearable electronics, customer Premises Equipment (CPE), wirelessly connected vehicles, wireless relays, and/or a wide variety of other communication devices. Further, the user equipment includes not only the presently available communication devices operating in the cellular network, but also communication devices subsequently developed that will be readily implemented with the inventive systems, processes, methods and devices described and claimed herein.

The illustrated communication network 10 of fig. 1 supports communication using a variety of cellular technologies, including, for example, 4G LTE and 5G NR. In some embodiments, the communication network 10 is further adapted to provide a Wireless Local Area Network (WLAN), such as WiFi. Although examples of various communication technologies have been provided, the communication network 10 may be adapted to support a variety of communication technologies.

Various communication links of the communication network 10 have been depicted in fig. 1. The communication links may be duplexed in a variety of ways including, for example, using frequency-division duplexing (FDD) and/or time-division duplexing (TDD). FDD is a type of radio frequency communication that uses different frequencies for transmitting and receiving signals. FDD may provide many advantages such as high data rates and low latency. In contrast, TDD is a type of radio frequency communication that uses approximately the same frequency to transmit and receive signals, and where the transmit and receive communications are switched in time. TDD can provide many advantages, such as efficient use of spectrum and variable allocation of throughput between transmit and receive directions.

In some embodiments, the user equipment may communicate with the base station using one or more of 4G LTE, 5G NR, and WiFi technologies. In some embodiments, enhanced licensed assisted access (eLAA) is used to aggregate one or more licensed frequency carriers (e.g., licensed 4G LTE and/or 5G NR frequencies) with one or more unlicensed carriers (e.g., unlicensed WiFi frequencies).

As shown in fig. 1, the communication link includes not only a communication link between the UE and the base station, but also UE-to-UE communication and base station-to-base station communication. For example, the communication network 10 may be implemented to support self-forwarding and/or self-backhauling (self-backhaul).

The communication link may operate on a variety of frequencies. In certain embodiments, communications are supported using 5G NR techniques on one or more frequency bands less than 6 gigahertz (GHz) and/or on one or more frequency bands greater than 6 GHz. For example, the communication link may serve frequency range 1 (FR 1), frequency range 2 (FR 2), or a combination thereof.

For example, a 5G NR may operate with different specifications on the 5G band, including with a flexible parameter set compared to the fixed parameter set of 4G. The FR1 (400 MHz to 7125 MHz) band was run with parameter set subcarrier spacing of 15kHz, 30kHz and 60 kHz. In addition, FR2 includes FR2-1 (24 GHz to 52 GHz) and FR2-2 (52 GHz to 71 GHz) and operates with parameter set subcarrier spacing of 60kHz, 120kHz and 240kHz to enable handling of higher phase noise and Doppler effects (e.g., for train applications up to 500 km/h).

In some embodiments, the base station and/or the user equipment communicate using beamforming. For example, beamforming may be used to focus signal strength to overcome path loss, such as high loss associated with communication at high signal frequencies. In some embodiments, user equipment, such as one or more mobile phones, communicate using beamforming at millimeter wave frequency bands in the range of 30GHz to 300GHz and/or centimeter wave frequencies in the range of 6GHz to 30GHz, or more specifically 24GHz to 30 GHz. In an embodiment, one or more of the mobile devices support HPUE power class specifications.

Different users of communication network 10 may share available network resources, such as available spectrum, in a variety of ways.

In one example, frequency Division Multiple Access (FDMA) is used to divide a frequency band into multiple frequency carriers. Further, one or more carriers are allocated to a particular user. Examples of FDMA include, but are not limited to, single carrier FDMA (SC-FDMA) and orthogonal FDMA (orthogonal FDMA). OFDMA is a multi-carrier technique that subdivides the available bandwidth into multiple mutually orthogonal narrowband subcarriers that can be allocated to different users, respectively.

Other examples of shared access include, but are not limited to: time Division Multiple Access (TDMA), in which users are allocated to use a specific time slot of a frequency resource; code Division Multiple Access (CDMA), in which frequency resources are shared among different users by assigning a unique code to each user; space-division multiple access (SDMA), in which beamforming is used to provide shared access through spatial division; and non-orthogonal multiple access (NOMA), in which the power domain is used for multiple access. For example, NOMA may be used to serve multiple users at the same frequency, time, and/or code, but at different power levels.

Enhanced mobile broadband (eMBB) refers to a technology for increasing system capacity of an LTE network. For example, the eMBB may refer to communications with a peak data rate of at least 10Gbps and a minimum of 100Mbps per user. Ultra-reliable low latency communication (urlllc) refers to a communication technology with very low latency, e.g., less than 2 milliseconds. The urrllc may be used for mission critical communications such as autopilot and/or telesurgical applications. Massive machine-type communication (mtc) refers to low-cost and low-data-rate communication associated with wireless connection of everyday objects, such as communication associated with Internet of Things (IoT) applications.

The communication network 10 of fig. 1 may be used to support a wide variety of advanced communication features including, but not limited to, eMBB, urrllc, and/or mtc.

Fig. 2A is a schematic diagram of one example of a communication link using carrier aggregation. Carrier aggregation may be used to broaden the bandwidth of a communication link by supporting communication on multiple frequency carriers, thereby increasing user data rates and enhancing network capacity by utilizing segmented spectrum allocations.

In the illustrated example, the communication link is provided between the base station 21 and the mobile device 22. As shown in FIG. 2A, the communication link includes a downlink channel for RF communication from the base station 21 to the mobile device 22 and an uplink channel for RF communication from the mobile device 22 to the base station 21.

Although fig. 2A illustrates carrier aggregation in the case of FDD communication, carrier aggregation may also be used for TDD communication.

In some embodiments, the communication link may provide asymmetric data rates for the downlink and uplink lanes. For example, the communication link may be used to support a relatively high downlink data rate to enable high-speed streaming of multimedia content to the mobile device, while providing a relatively slow data rate for uploading data from the mobile device to the cloud.

In the illustrated example, the base station 21 and the mobile device 22 communicate via carrier aggregation, which may be used to selectively increase the bandwidth of the communication link. Carrier aggregation includes contiguous aggregation in which contiguous carriers within the same operating frequency band are aggregated. Carrier aggregation may also be non-contiguous and may include carriers that are frequency separated within a common frequency band or within different frequency bands.

In the example shown in fig. 2A, the uplink channel comprises three aggregated component carriers f _UL1 、f _UL2 And f _UL3 . Furthermore, the downlink channel comprises five aggregated component carriers f _DL1 、f _DL2 、f _DL3 、f _DL4 And f _DL5 . Although one example of component carrier aggregation is shown, more or fewer carriers may be aggregated for uplink and/or downlink. Further, the number of aggregated carriers may vary over time to achieve desired uplink and downlink data rates.

For example, the number of aggregated carriers used for uplink and/or downlink communications related to a particular mobile device may vary over time. For example, the number of aggregated carriers may vary as devices move through the communication network and/or as network usage changes over time.

Fig. 2B illustrates various examples of uplink carrier aggregation for the communication link of fig. 2A. Fig. 2B includes a first carrier aggregation scenario 31, a second carrier aggregation scenario 32, and a third carrier aggregation scenario 33, which schematically depict three carrier aggregation types.

Carrier aggregation scenarios 31-33 illustrate for a first component carrier f _UL1 A second component carrier f _UL2 And a third component carrier f _UL3 Different spectrum allocations. Although fig. 2B is illustrated in the case of aggregating three component carriers, carrier aggregation may be used to aggregate more or fewer carriers. Furthermore, although illustrated in the context of uplink, the aggregation scenario also applies to downlink.

The first carrier aggregation scenario 31 illustrates in-band contiguous carrier aggregation, where adjacent in frequency and at a common frequencyThe component carriers of the band are aggregated. For example, the first carrier aggregation scenario 31 describes a component carrier f that is contiguous and located within the first frequency BAND1 _UL1 、f _UL2 And f _UL3 The polymerization of (2).

With continued reference to fig. 2B, a second carrier aggregation scenario 32 illustrates intra-band non-contiguous carrier aggregation, where two or more component carriers that are not adjacent in frequency and within a common frequency band are aggregated. For example, the second carrier aggregation scenario 32 depicts a component carrier f that is not adjacent but within the first frequency BAND1 _UL1 、f _UL2 、f _UL3 The polymerization of (2).

A third carrier aggregation scenario 33 illustrates inter-band non-adjacent carrier aggregation, where component carriers that are not adjacent in frequency and in multiple frequency bands are aggregated. For example, the third carrier aggregation scenario 33 describes the component carrier f of the first BAND1 _UL1 And f _UL2 With component carrier f of the second BAND BAND2 _UL3 The polymerization of (2).

Fig. 2C illustrates various examples of downlink carrier aggregation for the communication link of fig. 2A. These examples depict for the first component carrier f _DL1 A second component carrier f _DL2 A third component carrier f _DL3 Fourth component carrier f _DL 4 and a fifth component carrier f _DL5 Various carrier aggregation scenarios 34-38 of different spectrum allocations. Although fig. 2C illustrates a case where five component carriers are aggregated, carrier aggregation may be used to aggregate more or fewer carriers. Furthermore, although illustrated in the context of the downlink, the aggregation scenario also applies to the uplink.

The first carrier aggregation scenario 34 describes the aggregation of component carriers that are contiguous and located within the same frequency band. Further, the second carrier aggregation scenario 35 and the third carrier aggregation scenario 36 illustrate two examples of aggregations that are not adjacent but within the same frequency band. Further, the fourth carrier aggregation scenario 37 and the fifth carrier aggregation scenario 38 illustrate two aggregated examples in which component carriers that are not adjacent in frequency and in multiple frequency bands are aggregated. As the number of aggregated component carriers increases, the complexity of possible carrier aggregation scenarios also increases.

Referring to fig. 2A-2C, the individual component carriers used in carrier aggregation may be of multiple frequencies, including, for example, frequency carriers of the same frequency band or multiple frequency bands. Furthermore, carrier aggregation is applicable to embodiments in which the respective component carriers have approximately the same bandwidth, and also to embodiments in which the respective component carriers have different bandwidths.

Some communication networks allocate a Primary Component Carrier (PCC) for the uplink or anchor carrier and a PCC for the downlink for a particular user equipment. Further, when the mobile device uses a single frequency carrier for uplink or downlink communications, the user equipment communicates using the PCC. To improve the bandwidth of uplink communications, the uplink PCC may be aggregated with one or more uplink Secondary Component Carriers (SCCs). Further, to increase bandwidth of downlink communications, the downlink PCC may be aggregated with one or more downlink SCCs.

In some embodiments, the communication network provides a network element for each component carrier. Further, the primary cell may operate using a PCC, and the secondary cell may operate using an SCC. For example, the primary cell and the secondary cell may have different coverage areas due to differences in frequency of carriers and/or network environment.

Licensed spectrum assisted access (LAA) refers to downlink carrier aggregation where licensed frequency carriers associated with a mobile operator are aggregated with frequency carriers in unlicensed spectrum, such as WiFi. LAA employs a downlink PCC in a licensed spectrum that carries control and signaling information associated with the communication link, while unlicensed spectrum is aggregated for wider downlink bandwidth when available. The LAA may avoid and/or co-exist with WiFi users by dynamically adjusting the secondary carrier. Enhanced licensed spectrum assisted access (eLAA) refers to the evolution of LAA, which is a downlink and uplink aggregated licensed and unlicensed spectrum. Furthermore, the NR-U may operate over LAA/eLAA on the 5GHz band (5150 to 5925 MHz) and/or the 6GHz band (5925 MHz to 7125 MHz).

Fig. 3A is a diagram of one example of a downlink channel using multiple-input and multiple-output (MIMO) communication. Fig. 3B is a diagram of one example of an uplink channel using MIMO communication.

MIMO communication uses multiple antennas to simultaneously communicate multiple data streams over a common frequency spectrum. In some embodiments, the data streams operate with different reference signals to enhance data reception at the receiver. MIMO communications benefit from higher signal-to-noise ratios, improved coding, and/or reduced signal interference due to spatial multiplexing differences in the radio environment.

The MIMO order refers to the number of separate data streams transmitted or received. For example, the MIMO order for downlink communications may be described by the number of transmit antennas at the base station and the number of receive antennas at the UE (such as a mobile device). For example, two-by-two (2 x 2) DL MIMO refers to MIMO downlink communication using two base station antennas and two UE antennas. Further, four-by-four (4 x 4) DL MIMO refers to MIMO downlink communication using four base station antennas and four UE antennas.

In the example shown in fig. 3A, downlink MIMO communication is provided by transmitting using

M antennas

43A, 43b, 43c,. 43M of the base station 41 and receiving using

N antennas

44a, 44b, 44c,. 44N of the mobile device 42. Thus, fig. 3A illustrates an example of an m x n DL MIMO.

Likewise, the MIMO order for uplink communications may be described by the number of transmit antennas of a UE (such as a mobile device) and the number of receive antennas of a base station. For example, 2x 2UL MIMO refers to MIMO uplink communications using two UE antennas and two base station antennas. Furthermore, 4x 4ul MIMO refers to MIMO uplink communication using four UE antennas and four base station antennas.

In the example shown in fig. 3B, uplink MIMO communication is provided by transmitting using

N antennas

44a, 44B, 44c,. 44N of the mobile device 42 and receiving using

M antennas

43a, 43B, 43c,. 43M of the base station 41. Accordingly, fig. 3B illustrates an example of n x m UL MIMO.

By increasing the MIMO stage or order, the data bandwidth of the uplink channel and/or downlink channel may be increased.

MIMO communication is applicable to various types of communication links, such as FDD and TDD communication links.

Fig. 3C is a diagram of another example of an uplink channel using MIMO communication. In the example shown in fig. 3C, uplink MIMO communications are provided by transmitting using

N antennas

44a, 44b, 44C. A first portion of the additional uplink transmission is received using the M antennas 43a1, 43b1, 43c1,. 43M1 of the first base station 41a, while a second portion of the uplink transmission is received using the M antennas 43a2, 43b2, 43c2,. 43M2 of the second base station 41 b. Further, the first base station 41a and the second base station 41b communicate with each other through wired, optical and/or wireless links.

The MIMO scenario of fig. 3C illustrates an example in which multiple base stations cooperate to facilitate MIMO communications.

Fig. 4 is a schematic block diagram of one embodiment of a power amplifier system 140. The illustrated power amplifier system 140 includes an RF switching circuit 127 that includes a series switching transistor 125 and a parallel switching transistor 126. The illustrated power amplifier system 140 further includes a charge pump 122, a level shifter 123, a directional coupler 124, a power amplifier bias circuit 130, a power amplifier 132, and a transmitter 133. The illustrated transmitter 133 includes a baseband processor 134, an I/Q modulator 137, a mixer 138, and an analog-to-digital converter (ADC) 139. Although not shown in fig. 4 for clarity, transmitter 133 may include circuitry associated with receiving signals through one or more receive paths such that transceiving functionality is achieved.

The baseband signal processor 134 may be used to generate an in-phase (I) signal and a quadrature-phase (Q) signal, which may be used to represent a sine wave or signal of desired amplitude, frequency, and phase. For example, the I signal may be used to represent the in-phase component of a sine wave, and the Q signal may be used to represent the quadrature component of a sine wave, which may be an equivalent representation of a sine wave. In some embodiments, the I and Q signals may be provided to I/Q modulator 137 in a digital format. The baseband processor 134 may be any suitable processor configured to process baseband signals. For example, baseband processor 134 may include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Further, in some embodiments, two or more baseband processors 134 may be included in the power amplifier system 140.

The I/Q modulator 137 may be configured to receive the I and Q signals from the baseband processor 134 and process the I and Q signals to generate an RF signal. For example, the I/Q modulator 137 may include: a DAC configured to convert the I and Q signals to an analog format, a mixer for upconverting the I and Q signals to a radio frequency, and a signal synthesizer for combining the upconverted I and Q signals into an RF signal suitable for amplification by the power amplifier 132. In some embodiments, I/Q modulator 137 may include one or more filters configured to filter the frequency content of the signal processed therein.

The power amplifier bias circuit 130 may receive one or more control signals from the baseband processor 134, which may be used to generate one or more bias signals for the power amplifier 132. The control signal may include, for example, a bias setting or level and/or an enable function. Power amplifier 132 may receive a radio frequency signal from I/Q modulator 137 of transmitter 133.

The level shifter 123 may turn on and off the series switching transistor 125 and the parallel switching transistor 126 in a complementary manner. For example, the level shifter 123 may be used to turn on the series switching transistor 125 and turn off the shunt switching transistor 126 such that the power amplifier 132 provides an amplified RF signal to the antenna 114 through the series switching transistor 125. In addition, the level shifter 123 may be used to turn off the series switching transistor 125 and turn on the shunt switching transistor 126 to provide a high impedance path between the output of the power amplifier 132 and the antenna 114 while providing termination to the output of the power amplifier. To control the state of RF switching circuitry 127, level shifter 123 may receive a switch enable signal (not shown in fig. 4) from any suitable circuitry, such as transmitter 133.

Directional coupler 124 may be located between the output of power amplifier 132 and the source of series-switched transistor 125, allowing the output power measurement of power amplifier 132 to exclude the insertion loss of series-switched transistor 125. The sense output signal from the directional coupler 124 may be provided to a mixer 138, which may multiply the sense output signal by a reference signal of a controlled frequency to downconvert the frequency content of the sense output signal to produce a downconverted signal. The downconverted signal may be provided to an ADC 139, which may convert the downconverted signal to a digital format suitable for processing by the baseband processor 134.

By including a feedback path between the output of the power amplifier 132 and the baseband processor 134, the baseband processor 134 may be configured to dynamically adjust the I and Q signals to optimize operation of the power amplifier system 140. Configuring the power amplifier system 140 in this manner may help to control the Power Added Efficiency (PAE) and/or linearity of the power amplifier 132, for example.

In the illustrated configuration, the charge pump 122 provides a positive charge pump voltage and a negative charge pump voltage to the level shifter 123. In some configurations (e.g., when the switches are implemented using n-type transistors), a positive charge pump voltage is used to bias the gate voltage of the series switch transistor 125 and/or the shunt switch transistor 126 when on, and a negative charge pump voltage is used to bias the gate voltage of the series switch transistor 125 and/or the shunt switch transistor 126 when off.

Although the series switching transistor 125 and the parallel switching transistor 126 are each described as a single transistor, each of the series switching transistor 125 and the parallel switching transistor 126 is typically implemented using a transistor stack. For example, stacked transistors help meet desired power handling capabilities. In addition, certain biasing details of the series switching transistor 125 and the parallel switching transistor 126, such as gate resistance and other biasing, are not depicted in fig. 4 for clarity of the drawing.

Fig. 5A is a circuit diagram of one embodiment of a level shifter 210. The level shifter 210 includes a first n-type metal oxide semiconductor (NMOS) level-shifting transistor 171, a second NMOS level-shifting transistor 172, a third NMOS level-shifting transistor 173, a fourth NMOS level-shifting transistor 174, a first NMOS cascode transistor 181, a second NMOS cascode transistor 182, a first p-type metal oxide semiconductor (PMOS) level-shifting transistor 191, a second PMOS level-shifting transistor 192, a first PMOS cascode transistor 193, a second PMOS cascode transistor 194, a third PMOS cascode transistor 195, a fourth PMOS cascode transistor 196, a first enable level-shifter 207, and a second enable level-shifter 208.

In the illustrated embodiment, level shifter 210 receives a switch enable signal SW _EN And an inverted switch enable signal SW _ENB Regulated voltage V (from a voltage regulator, such as a low dropout regulator) _REG Negative charge pump voltage V (from the negative charge pump) _NEG And a positive charge pump voltage V (from the positive charge pump) _POS . Level shifter 210 includes a non-inverting switch control output SW _CTL And an inverting switch control output SW _CTLB For generating switch control signals of complementary polarity to control the RF switching circuitry (e.g. one for controlling the series switch and the other for controlling the parallel switch as in the configuration of fig. 4). Although in some applications both outputs are used, in other embodiments only the output of the level shifter is used.

The first enable level shifter 207 level-shifts the switch enable signal SW _EN To generate level shifted switch enable signals in the voltage domain of the positive charge pump (first enable level shifter 207 and second enable level shifter 208 are driven by V _POS And ground supply). In addition, the second enable level shifter 208 level-shifts the inverse switch enable signal SW _ENB To generate a level shifted inverted switch enable signal in the voltage domain of the positive charge pump. Although shown as receiving a pair of switch enable signals of complementary polarity, in another embodiment, the level shifter 210 receives a single switch enable signal, which may be inverted (e.g., using an inverter) to generate a pair of switch enable signals.

As shown in FIG. 5A, the first NMOS level-shifting transistor 171 and the first NMOS cascode transistor 181 are at a negative charge-pump voltage V _NEG And an inverting switch control output SW _CTLB In series (source to drain) with the first PMOS level-shift transistor 191 and the first PMOS cascode transistor 193 at the positive charge pump voltage V _POS And an inverting switch control output SW _CTLB In series (from source to drain). In addition, the fourth NMOS level shiftsThe bit transistor 174 and the second NMOS cascode transistor 182 are at a negative charge-pump voltage V _NEG And a non-inverting switch control output SW _CTL In series (source to drain) with the second PMOS level-shift transistor 192 and the fourth PMOS cascode transistor 196 at the positive charge pump voltage V _POS And a non-inverting switch control output SW _CTL In series (source to drain).

In the illustrated embodiment, the gate of the first NMOS level shift transistor 171 and the gate of the third NMOS level shift transistor 173 are connected to the drain of the second NMOS level shift transistor 172. Further, the gate of the second NMOS level-shift transistor 172 and the gate of the fourth NMOS level-shift transistor 174 are connected to the drain of the third NMOS level-shift transistor 173. The gates and drains of the second NMOS level-shift transistor 172 and the third NMOS level-shift transistor 173 are cross-coupled.

The gates of the first and second

NMOS cascode transistors

181 and 182 are connected to a regulation voltage V _REG . In addition, the gate of the second PMOS cascode transistor 194 is enabled by the switch enable signal SW _EN Control while the gate of the third PMOS cascode transistor 195 is enabled by the inverse switch enable signal SW _ENB And (5) controlling.

The gates of the first and fourth

PMOS cascode transistors

193 and 196 are grounded. In addition, the gate of the first PMOS level-shift transistor 191 receives the level-shift inverted switch enable signal, and the gate of the second PMOS level-shift transistor 192 receives the level-shift switch enable signal.

Level shifter 210 provides a number of advantages, including a charge pump voltage V _POS And V _NEG Low current draw (current draw), low voltage margin (headroom), and robust latching (of cross-coupled transistors 172 and 173) during low voltage operation. In addition, the voltage V is regulated _REG Is low impedance to maintain robust operation and also activates quickly after start-up. Thus, the level shifter 210 is associated with fast start-up times even at the charge pump voltage V _POS And/or V _NEG Not at steady state values, such as aboveThe level shifting can also be performed shortly after the electrical sequence and/or start-up.

Fig. 5B is a graph of one example of a waveform of the level shifter 210 of fig. 5A. The graph includes a positive charge pump voltage V _POS Negative charge pump voltage V _NEG Switch control output SW _CTL And a reverse switch control output SW _CTLB For example, where positive and negative charge pumps drive many level shifters and suffer from large current draw at the end of a transmit or receive timeslot associated with changing switch states (approximately 12 microseconds (mus) and 27 mus in this simulation), for example in Time Division Duplex (TDD) applications.

As shown in fig. 5B, the level shifter 210 continues to operate normally even in the presence of a large current draw on the charge pump power supply.

Fig. 6 is a schematic diagram of one embodiment of a charge pump 220. The charge pump 220 includes a first set of clock inverters 211a/212a/213a, a second set of clock inverters 211b/212b/213b, a first flying capacitor Cfly1, a second flying capacitor Cfly2, a first NMOS transistor 215, a second NMOS transistor 216, a first PMOS transistor 217, and a second PMOS transistor 218.

With continued reference to FIG. 6, the charge pump 220 includes a first clock input CLK for receiving a non-inverted clock signal for driving the first set of clock inverters 211a/212a/213a and a second clock input CLK _ B for receiving an inverted clock signal for driving the second set of clock inverters 211B/212B/213B. The first set of clock inverters 211a/212a/213a is sized to buffer the non-inverted clock signal to provide sufficient drive strength to drive the first terminal of the first flying capacitor Cfly 1. Similarly, the second set of clock inverters 211b/212b/213b is sized to buffer the inverted clock signal to provide sufficient drive strength to drive the first terminal of the second flying capacitor Cfly 2.

The set of clock inverters may include any suitable number of inverters and may be scaled in any suitable manner (1 x, 4x, and 12x in this example). Thus, although an example of three inverters with 4x amplification is shown, more or fewer inverters and/or different scaling may be used. In some embodiments, the buffered clock signals used to drive the flying capacitor correspond to a pair of non-overlapping clock signals.

As shown in fig. 6, the charge pump 220 includes a first terminal VP and a second terminal VN. Based on the connectivity of the first terminal VP and the second terminal VN, the charge pump 220 can act as a positive charge pump (generating V at the first terminal VP) _POS Having a boost with respect to, for example, the second terminal VN connected to the normal supply voltage supplied to the chip pin) or negative charge pump (generating V at the second terminal VN) _NEG Which has a reduced or stepped-down voltage with respect to, for example, the first terminal VP connected to ground).

Fig. 7A is a schematic diagram of one embodiment of a charge pump clock generator 230. The charge pump clock generator 230 includes a multiphase oscillator (corresponding to the seven-phase ring oscillator 221 in this example). The charge pump clock generator 230 further includes a clock phase logic circuit 222 (implemented in this example as AND

gates

222a, 222b, 222c, 222d, 222e, 222f, AND 222 g) AND a clock phase combining circuit 223.

In the illustrated embodiment, the ring oscillator 221 generates clock signals clk <1>, clk <2>, clk <3>, clk <4>, clk <5>, clk <6> and clk <7> that are the same frequency but different in phase (e.g., evenly spaced). Further, the and

gates

222a, 222b, 222c, 222d, 222e, 222f, and 222g perform logical operations on adjacent clock signal phases, generating clock phase signals ph1, ph2, ph3, ph4, ph5, ph6, and ph7, which are processed by the phase combining circuit 223 to generate a multiplied frequency clock signal CLK with respect to the oscillation frequency of the ring oscillator 221.

In this example, and gates operate with respective enable signals EN1, EN2, EN3, EN4, EN5, EN6, and EN7 to selectively enable one or more clock phase signals ph1, ph2, ph3, ph4, ph5, ph6, and ph7.

The charge pump clock generator 230 advantageously synthesizes a higher frequency clock signal than the oscillator 221. This in turn reduces the charge pump output voltage (e.g., V) _POS Or V _NEG ) Medium frequency spikes (spurs) and/or undesirableClock noise, the charge pump output voltage, is generated by the charge pump using a clock signal to control pumping.

Figure 7B is a schematic diagram of one embodiment of frequency multiplication logic 240 for a charge pump clock generator. The frequency multiplication logic 240 includes a clock phase logic circuit 232 (implemented in this example as and

gates

232a, 232b, 232c, 232d, 232e, 232f, 232g, 232h, and 232 i) and a clock phase combining circuit 233 (implemented in this example as OR

gates

233a, 233b, 234, and 235).

In the illustrated embodiment, the clock phase logic processes nine clock signals (CLK <1>, CLK <2>, CLK <3>, CLK <4>, CLK <5>, CLK <6>, CLK <7>, CLK <8>, and CLK <9 >) from a multiphase oscillator (e.g., a ring oscillator) to generate the clock signal phases CLK _ a <1>, CLK _ a <2>, CLK _ a <3>, CLK _ a <4>, CLK _ a <5>, CLK _ a <6>, CLK _ a <7>, CLK _ a <8>, and CLK _ a <9>. The phase combining circuit 233 performs a logical OR of the phases of the clock signals to generate a boosted clock signal FCLK _ BOOST having a frequency higher than the received clock signal from the multiphase oscillator.

Fig. 7C is a graph of one example of waveforms for positive and negative charge pumps operating at different clock frequencies. As the waveforms illustrate, faster clock speeds are advantageous for providing a charge pump with higher output drive capability and/or initial ramp-up time.

While fast clock speeds are desirable, frequency spikes and/or undesirable clock noise can be introduced when using fast oscillators. The benefits of fast pumping, small frequency spurs, and/or low clock noise may be achieved in accordance with the teachings herein by synthesizing a faster clock signal for the charge pump using a slower running oscillator.

Fig. 8A is a schematic diagram of another embodiment of a charge pump clock generator 250. The charge pump clock generator 250 includes a multiphase oscillator (corresponding to a seven-phase ring oscillator 241 in this example). The charge pump clock generator 230 further includes a clock phase logic and combination circuit 242 (implemented in this example as exclusive OR

gates

242a, 242b, and 242 c).

Clock phase logic and combination circuit 242 processes the oscillator clock signals from the multiphase oscillator to generate a first multiplied clock signal (CLK _ DBL <1> or pvg) for driving the positive charge pump (e.g., CLK _ DBL <1> may be inverted to generate a pair of input clock signals CLK and CLKB to charge pump 220 of fig. 6) and a second multiplied clock signal (CLK _ DBL <3> or nvg) for driving the negative charge pump.

Advantageously, the first multiplied clock signal and the second multiplied clock signal have a common frequency but are offset in phase to spread out the time instances of current draw by the positive charge pump and the negative charge pump. Thus, enhanced performance is obtained relative to a configuration in which the clock signals to the positive charge pump and the negative charge pump have the same phase (phase alignment).

Fig. 8B is a schematic diagram of another embodiment of frequency multiplication logic 260 of the charge pump clock generator. In this example,

XOR gates

251 and 252 are used to process the clock signal phases (CLK <1>, CLK <3>, CLK <5>, and CLK <8 >) to synthesize double (doubled) frequency clock signals CLK _ DBL1 and CLK _ DBL2, respectively. In addition, the OR gate 253 is used to process the clock signals CLK _ DBL1 and CLK _ DBL2 to generate a clock signal CLK _4x at a quadruple frequency (twice the frequency) with respect to the original clock signal phases (CLK <1>, CLK <3>, CLK <5>, and CLK <8 >).

Fig. 8C is a diagram of one example of a waveform of the charge pump clock generator. These waveforms correspond to a charge pump clock generator that includes the frequency multiplication logic 260 of fig. 8B. As shown in fig. 8C, a doubling of the frequency is achieved.

Fig. 9 is a schematic block diagram of an RF switch system 290 according to an embodiment. The RF switch system 290 includes

RF switches

291a, 291 b.. 291n, a switch controller 292, generating a positive charge pump voltage V _POS Positive charge pump 293 generating negative charge pump voltage V _NEG A negative charge pump 294, and a charge pump clock generator 295.

As shown in FIG. 9, the switch controller 292 includes generating the regulated voltage V _REG Corresponding to the low dropout regulator 297 in this example), and a level shifter298a、298b、...298n。

Level shifters

298a, 298b,. 298n operate to shift the switch enable signal SW _ENa 、SW _ENb 、...SW _ENn To generate switch control signals SW for

RF switches

291a, 291b _CTLa 、SW _CTLb 、...SW _CTLn . As shown in FIG. 9,

level shifters

298a, 298b,. 298n receive regulated voltage V, respectively _REG Positive charge pump voltage V _POS And a negative charge pump voltage V _NEG . In addition, charge pump clock generator 295 generates clock signals for positive charge pump 293 and negative charge pump 294.

The

level shifters

298a, 298b,. 298n and/or the charge pump clock generator 295 may be implemented according to any embodiment herein.

Although the illustrated RF switching system 290 includes three level shifters and three switches, any number of level shifters and switches may be included.

Fig. 10A is a schematic diagram of one embodiment of a package module 300. Fig. 10B is a cross-sectional schematic view of the package module 300 of fig. 10A taken along line 10B-10B.

The package module 300 includes an IC or chip 301, a surface mount component 303, wire bonds 308, a package substrate 320, and a packaging structure 940. Package substrate 320 includes pads 306 formed from conductors disposed therein. In addition, semiconductor chip 301 includes pads 304, and wire bonds 308 have been used to electrically connect pads 304 of chip 301 to pads 306 of package substrate 301.

As shown in fig. 10A and 10B, chip 301 includes charge pump 122, level shifter 123, and switch 127, which may be as previously described.

Package substrate 320 may be configured to receive a plurality of components, such as chip 301 and surface mount component 303, where surface mount component 303 may include, for example, a surface mount capacitor and/or an inductor.

As shown in fig. 10B, the packaged module 300 is shown to include a plurality of contact pads 332, the plurality of contact pads 332 being disposed on a side of the packaged module 300 opposite a side for mounting the chip 301. Configuring the packaged module 300 in this manner can facilitate connecting the packaged module 300 to a circuit board, such as a phone board of a wireless device. Example contact pads 332 may be configured to provide an RF signal, a bias signal, a power low voltage, and/or a power high voltage to chip 301 and/or surface mount components. As shown in fig. 10B, electrical connections between contact pads 332 and chip 301 may be made through connections 333 through package substrate 320. Connections 333 may represent electrical pathways formed through package substrate 320, such as connections associated with vias and conductors of a multi-layer laminate package substrate.

In some embodiments, the packaged module 300 may also include one or more packaging structures to, for example, provide protection and/or facilitate access to the packaged module 300. Such a package structure may include a cladding or encapsulation structure 340 formed over the package substrate 320 and the components and chips disposed thereon.

It will be appreciated that although the package module 300 is described in the context of wire-bond based electrical connections, one or more features of the present application may also be implemented in other package configurations, including, for example, flip-chip configurations.

Fig. 11 is a schematic diagram of an RF (radio frequency) switching network 420 according to another embodiment. The rf switching network 420 includes a first series transistor switch 361, a second series transistor switch 365, a first input shunt transistor switch 381, a second input shunt transistor switch 385, a first output shunt transistor switch 401, and a second output shunt transistor switch 405.

RF switch network 420 of fig. 11 illustrates another embodiment of an RF switch network suitable for use in an RF switch system, such as RF switch system 120 of fig. 4. However, other embodiments are possible, including but not limited to RF switch networks that include more or fewer series transistor switches and/or more or fewer parallel transistor switches.

IN the illustrated embodiment, the first series transistor switch 361 is electrically connected between the first RF input terminal RF _ IN1 and the RF output terminal RF _ OUT, while the second series transistor switch 365 is electrically connected between the second RF input terminal RF _ IN2 and the RF output terminal RF _ OUT. Further, a first input shunt transistor switch 381 is electrically connected between the first RF input terminal RF _ IN1 and ground, and a second input shunt transistor 385 is electrically connected between the second RF input terminal RF _ IN2 and ground. Further, a first output shunt transistor switch 401 is electrically connected between the RF output terminal RF _ OUT and ground, and a second output shunt transistor switch 405 is electrically connected between the RF output terminal RF _ OUT and ground.

As shown in fig. 11, the first switch control voltage V _CTL1 Controls the first series transistor switch 361, and the first inverting switch controls the voltage V _CTL1B Controlling the first input parallel transistor switch 381 and the first output parallel transistor switch 401. In addition, a second switch control voltage V _CTL2 The second series transistor switch 365 is controlled and the second inverting switch controls the voltage V _CTL2B Controlling the second input shunt transistor switch 385 and the second output shunt transistor switch 405. In some embodiments, the first level shifter generates a first switch control voltage V _CTL1 And a first inverse switch control voltage V _CTL1B And the second level shifter generates a second switch control voltage V _CTL2 And a second inverse switch control voltage V _CTL2B 。

The described transistor switches each comprise several transistors in series, where the biased transistors use corresponding gate and channel resistors, to achieve the desired power handling capability.

For example, the first series transistor switch 361 includes

NFETs

371a, 371b,. 371n,

gate resistors

372a, 372b,. 372n, and

channel resistors

373a, 373b,. 373n. In addition, the second series transistor switch 365 includes NFETs 375a, 375b,. 375n,

gate resistors

376a, 376b,. 376n, and channel resistors 377a, 377b,. 377n. In addition, the first input shunt transistor switch 381 includes

NFETs

391a, 391b,

gate resistors

392a, 392b, and

channel resistors

393a, 393b. In addition, second input parallel transistor switch 385 includes

NFETs

395a, 395b,

gate resistors

396a, 396b, and

channel resistors

397a, 397b. In addition, first output parallel transistor switch 401 includes NFETs 411a, 411b,

gate resistors

412a, 412b, and

channel resistors

413a, 413b. In addition, second output shunt transistor switch 405 includes

NFETs

415a, 415b,

gate resistors

416a, 416b, and

channel resistors

417a, 417b.

Fig. 12 is a schematic diagram of one embodiment of a mobile device 800, according to another embodiment. Mobile device 800 includes a baseband system 801, a transceiver 802, a front-end system 803, an antenna 804, a power management system 805, memory 806, a user interface 807, and a battery 808.

The mobile device 800 may communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (LTE, LTE Advanced, and LTE-Advanced Pro 1), 5G NR, WLAN (e.g., wiFi), WPAN (e.g., bluetooth and ZigBee), WMAN (e.g., wiMax), and/or GPS technologies.

The transceiver 802 generates RF signals for transmission and processes incoming RF signals received from the antenna 804. It should be appreciated that various functions associated with the transmission and reception of RF signals may be obtained by one or more components, generally represented in fig. 12 as transceiver 802. In an example, different components (e.g., different circuits or chips) may be provided for processing a particular type of RF signal.

Front-end system 803 facilitates conditioning signals transmitted to antenna 804 and/or received from antenna 804. In the illustrated embodiment, front-end system 803 includes a level shifter 810, a Power Amplifier (PA) 811, a Low Noise Amplifier (LNA) 812, a filter 813, a switch 814, and a signal splitting/combining circuit 815. However, other implementations are possible.

For example, front-end system 803 may provide functions including, but not limited to, amplifying a signal for transmission, amplifying a received signal, filtering a signal, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, duplexing of signals, multiplexing of signals (e.g., diplexing or triplexing), or some combination thereof.

In some embodiments, the mobile device 800 supports carrier aggregation, providing flexibility to increase peak data rates. Carrier aggregation may be used for both Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD), and may be used to aggregate multiple carriers or channels. Carrier aggregation includes contiguous aggregation in which contiguous carriers having the same operating frequency band are aggregated. Carrier aggregation may also be non-contiguous and may include carriers separated in frequency in a common frequency band or different frequency bands.

The antenna 804 may include an antenna for various types of communication. For example, the antenna 804 may include an antenna for transmitting and/or receiving signals associated with a wide variety of frequencies and communication standards.

In certain embodiments, antennas 804 support MIMO communications and/or switched diversity communications. For example, MIMO communication uses multiple antennas to transmit multiple data streams via a single radio frequency channel. MIMO communications benefit from higher signal-to-noise ratios, improved coding, and/or reduced signal interference due to spatial multiplexing differences in the radio environment. Switched diversity refers to communication in which a particular antenna is selected to operate at a particular time. For example, a switch may be used to select a particular antenna from a group of antennas based on various factors, such as an observed bit error rate and/or a signal strength indicator.

The mobile device 800 may operate with beamforming in some embodiments. For example, the front-end system 803 may include amplifiers with controllable gain and phase shifters with controllable phase to provide beamforming and directivity for transmission and/or reception of signals using the antenna 804. For example, in the case of signal transmission, the amplitude and phase of the transmit signal provided to the antenna 804 are controlled such that the radiated signals from the antenna 804 combine using constructive and destructive interference to produce an aggregate transmit signal exhibiting similar beam quality with more signal strength propagating in a given direction. In the case of signal reception, the amplitude and phase are controlled so that more signal energy is received when the signal arrives at the antenna 804 from a particular direction. In some embodiments, the antenna 804 includes one or more arrays of antenna elements to enhance beamforming.

The baseband system 801 is coupled to a user interface 807 to facilitate processing of various user inputs and outputs (I/O), such as voice and data. The baseband system 801 provides a transceiver 802 with a digital representation of the transmitted signal, which the transceiver 802 processes to generate an RF signal for transmission. The baseband system 801 also processes the digital representation of the received signal provided by the transceiver 802. As shown in fig. 12, the baseband system 801 is coupled to memory 806 to facilitate operation of the mobile device 800.

Memory 806 may be used for a variety of purposes such as, for example, storing data and/or instructions to facilitate operation of mobile device 800 and/or providing storage of user information.

Power management system 805 provides a number of power management functions for mobile device 800. In some embodiments, power management system 805 includes PA power supply control circuitry that controls the supply voltage of power amplifier 811. For example, the power management system 805 may be configured to vary the supply voltage provided to one or more power amplifiers 811 to improve efficiency, such as Power Added Efficiency (PAE).

As shown in fig. 12, power management system 805 receives battery voltage from battery 808. Battery 808 can be any suitable battery for mobile device 800 including, for example, a lithium ion battery.

The mobile device 800 may include any combination of the features of the present application. For example, in some embodiments, power management system 805 includes a positive charge pump that generates a positive charge pump voltage, a negative charge pump that generates a negative charge pump voltage, and a voltage regulator that generates a regulated voltage. Furthermore, front-end system 803 includes an RF switch (in switch 814) controlled by a level shifter (in level shifter 810), wherein the level shifter receives a positive charge pump voltage, a negative charge pump voltage, and a regulated voltage.

Conclusion

Some of the embodiments described above have provided examples relating to mobile devices. However, the principles and advantages of the embodiments may be applied to any other system or apparatus where RF switching is desired.

Throughout the specification and claims, the words "comprise," "comprising," and similar words are to be construed in an inclusive sense as opposed to an exclusive or exclusive sense, unless the context clearly requires otherwise; that is, in the sense of "including, but not limited to". As generally used herein, the word "coupled" means that two or more elements may be connected directly or through one or more intermediate elements. Similarly, the word "connected," as generally used herein, means that two or more elements may be connected directly or through one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words of the above detailed description in the singular or plural number may also include the singular or plural number respectively. The word "or" when referring to a list of two or more items, this word covers all of the following interpretations of the word: any item in the list, all items in the list, any combination of items in the list.

Moreover, unless stated otherwise or used as understood within the context, conditional language such as, where "may", "might", "may" (right) "" may "," example "," for example "," such as "and similar languages, as used herein, are generally intended to convey that certain embodiments include but other embodiments do not include certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and/or states are included or are to be performed in any particular embodiment.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while flows or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some flows or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these flows or blocks may be implemented in a variety of different ways. Additionally, while flows or blocks are sometimes shown as being performed in series, these flows or blocks may instead be performed in parallel, or may be performed at different times.

The teachings of the invention provided herein may be applied to other systems, not necessarily the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the application. Indeed, the novel methods and systems described herein may be implemented in a variety of other applications; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the application. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A mobile device, comprising:

a power management system comprising a positive charge pump configured to generate a positive charge pump voltage, a negative charge pump configured to generate a negative charge pump voltage, and a voltage regulator configured to generate a regulated voltage; and

a front-end system comprising a radio frequency switch controlled by a first switch control signal; and a level shifter operable to level shift a first switch enable signal to produce a first switch control signal at a first output, the level shifter comprising a first level-shifted n-type transistor and a first cascode n-type transistor in series between the negative charge pump voltage and the first output, a first level-shifted p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output, and a second cascode p-type transistor between the regulation voltage and a gate of the first level-shifted n-type transistor and controlled by the first switch enable signal.

2. The mobile device 1 of claim 1, wherein the level shifter is further operable to level shift a second switch enable signal to produce a second switch control signal at a second output, the second switch enable signal having a complementary polarity to the first switch enable signal.

3. The mobile device of claim 2, wherein the level shifter further comprises: a second level-shifted n-type transistor in series with the second cascode p-type transistor between the regulation voltage and the negative charge-pump voltage; a third cascode p-type transistor; and a third level-shifted n-type transistor in series with the third cascode p-type transistor between the regulation voltage and the negative charge-pump voltage.

4. The mobile device of claim 3, wherein the level shifter further comprises: a fourth level-shifting n-type transistor and a second cascode n-type transistor in series between the second output and the negative charge-pump voltage, and a second level-shifting p-type transistor and a fourth cascode p-type transistor in series between the positive charge-pump voltage and the second output.

5. The mobile device of claim 1, wherein the front-end system further comprises a power amplifier configured to provide a radio frequency signal to the radio frequency switch.

6. The mobile device 1 of claim 1, wherein the power management system further comprises: a charge pump clock generator comprising a multiphase oscillator configured to generate a plurality of oscillator clock signals; and a clock phase logic and combination circuit configured to process the plurality of oscillator clock signals to generate a first clock signal having a frequency higher than an oscillation frequency of the multiphase oscillator, the first clock signal operable to control at least one of the positive charge pump or the negative charge pump.

7. The mobile device of claim 6, wherein the clock phase logic and combination circuit is further configured to generate a second clock signal phase offset from the first clock signal, the first clock signal operable to control the positive charge pump and the second clock signal operable to control the negative charge pump.

8. A radio frequency switching system, comprising:

a radio frequency switch configured to receive a radio frequency signal and controlled by a first switch control signal;

a positive charge pump configured to generate a positive charge pump voltage;

a negative charge pump configured to generate a negative charge pump voltage;

a voltage regulator configured to generate a regulated voltage; and

a level shifter operable to level shift a first switch enable signal to produce the first switch control signal at a first output, the level shifter comprising a first level-shifted n-type transistor and a first cascode n-type transistor in series between the negative charge pump voltage and the first output, a first level-shifted p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output, and a second cascode p-type transistor between the regulation voltage and a gate of the first level-shifted n-type transistor and controlled by the first switch enable signal.

9. The radio frequency switching system of claim 8, wherein the level shifter is further operable to level shift a second switch enable signal to produce a second switch control signal at a second output, the second switch enable signal having a complementary polarity to the first switch enable signal.

10. The radio frequency switching system of claim 9, wherein the level shifter further comprises: a second level-shifted n-type transistor in series with the second cascode p-type transistor between the regulation voltage and the negative charge-pump voltage; a third cascode p-type transistor; and a third level-shifted n-type transistor in series with the third cascode p-type transistor between the regulation voltage and the negative charge-pump voltage.

11. The radio frequency switching system of claim 10, wherein the level shifter further comprises: a fourth level-shifting n-type transistor and a second cascode n-type transistor in series between the negative charge-pump voltage and the second output, and a second level-shifting p-type transistor and a fourth cascode p-type transistor in series between the positive charge-pump voltage and the second output.

12. The radio frequency switching system of claim 11, further comprising: a first enable level shift circuit configured to level shift the first switch enable signal to generate a first level shift switch enable signal that controls a gate of the second level shift p-type transistor; and a second enable level shift circuit configured to level shift a second switch enable signal to generate a second level shift switch enable signal that controls a gate of the first level shift p-type transistor.

13. The radio frequency switching system of claim 11, wherein the gates of the first and fourth cascode p-type transistors are connected to a ground voltage.

14. The radio frequency switching system of claim 11, wherein the gate of the second level-shifting n-type transistor and the gate of the fourth level-shifting n-type transistor are connected to the drain of the third level-shifting n-type transistor, and the gate of the first level-shifting n-type transistor and the gate of the third level-shifting n-type transistor are connected to the drain of the second level-shifting n-type transistor.

15. The radio frequency switch system of claim 9, wherein the radio frequency switch comprises: a series transistor switch electrically connected between an input terminal and an output terminal and controlled by the first switch control signal; and a parallel transistor switch electrically connected between the input terminal and a ground voltage and controlled by the second switch control signal.

16. The radio frequency switching system of claim 8, further comprising: a charge pump clock generator comprising a multiphase oscillator configured to generate a plurality of oscillator clock signals; and a clock phase logic and combination circuit configured to process a plurality of oscillator clock signals to generate a first clock signal having a frequency higher than an oscillation frequency of the multiphase oscillator, the first clock signal operable to control at least one of the positive charge pump or the negative charge pump.

17. The radio frequency switching system of claim 16, wherein the clock phase logic and combining circuit is further configured to generate a second clock signal phase offset from the first clock signal, the first clock signal operable to control a positive charge pump and the second clock signal operable to control the negative charge pump.

18. The radio frequency switching system of claim 8, wherein the voltage regulator is a low dropout regulator.

19. A level shifter for a radio frequency switch, the level shifter comprising:

a first level-shifting n-type transistor;

a first cascode n-type transistor in series with the first level-shifted n-type transistor between a negative charge-pump voltage and a first output providing a first switch control signal;

a first level-shifted p-type transistor;

a first cascode p-type transistor in series with a first level-shifted p-type transistor between a positive charge pump voltage and the first output; and

a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifted n-type transistor and controlled by a first switch enable signal.

20. The level shifter of claim 19, further comprising: a second level-shifted n-type transistor in series with the second cascode p-type transistor between the regulation voltage and the negative charge-pump voltage; a third cascode p-type transistor; and a third level-shifted n-type transistor in series with the third cascode p-type transistor between the regulation voltage and the negative charge-pump voltage.