CN115548057A

CN115548057A - Display device and method for manufacturing the same

Info

Publication number: CN115548057A
Application number: CN202210319103.9A
Authority: CN
Inventors: 车明根; 崔相虔; 姜泰旭; 成范模; 吴允祯; 李镕守
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2021-06-14
Filing date: 2022-03-29
Publication date: 2022-12-30
Also published as: KR20220167831A; US20220399428A1; CN217334099U

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a substrate; a transistor disposed on the substrate; a first electrode connected to the transistor; an emission layer disposed on the first electrode; a second electrode disposed on the emission layer; a common voltage line connected to the second electrode; and third and fourth electrodes disposed between the common voltage line and the second electrode.

Description

Display device and method for manufacturing the same

This application claims priority and benefit of korean patent application No. 10-2021-0076799, filed on 14/6/2021, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Technical Field

Embodiments of the invention relate generally to a display device and a method of manufacturing the same, and more particularly, to a display device having a common voltage line connected to an auxiliary electrode and a method of manufacturing the same.

Background

The display device is a device for displaying an image, and includes a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, and the like. Display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, electronic books, portable game machines, and various terminals.

An organic light emitting display device includes two electrodes and an organic light emitting layer interposed between the two electrodes, wherein electrons injected from one electrode and holes injected from the other electrode are recombined in the organic light emitting layer to generate excitons. The generated excitons change from an excited state to a ground state, releasing energy to emit light.

Such an organic light emitting display device includes a plurality of pixels including an organic light emitting diode as a self-emission element, and in each pixel, a plurality of transistors and at least one capacitor for driving the organic light emitting diode may be formed.

In this case, in order to improve the transmittance of the display device, the thickness of the cathode electrode of the portion where the organic light emitting diode is formed may be thinly formed.

The above information disclosed in this background section is only for background understanding of the inventive concept and, therefore, may contain information that does not form the prior art.

Disclosure of Invention

The applicant found that as the thickness of the cathode electrode is reduced, its resistance increases and the cathode electrode separates in some areas, which leads to a voltage drop phenomenon. Therefore, the display device may have uneven brightness due to a voltage drop of a cathode electrode of the light emitting diode of the display device.

The display device and the method of manufacturing the same constructed according to the principles and illustrative embodiments of the invention can reduce or prevent a voltage drop of the cathode electrode of the light emitting diode thereof such that the display device has substantially uniform luminance.

Additional features of the inventive concept will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the inventive concept.

According to an aspect of the invention, a display device includes: a substrate; a transistor disposed on the substrate; a first electrode connected to the transistor; an emission layer disposed on the first electrode; a second electrode disposed on the emission layer; a common voltage line connected to the second electrode; and third and fourth electrodes disposed between the common voltage line and the second electrode.

The third electrode may include a first auxiliary electrode contacting a side surface of the common voltage line, and the fourth electrode may include a second auxiliary electrode disposed on the first auxiliary electrode.

The first auxiliary electrode may include a first inclined surface adjacent to a side surface of the common voltage line, and the second auxiliary electrode may include a second inclined surface adjacent to the first inclined surface of the first auxiliary electrode, and wherein: the first inclined surface of the first auxiliary electrode may be disposed at a first inclination angle, the side surface of the common voltage line may be disposed at a second inclination angle, the first inclination angle being smaller than the second inclination angle, and the second inclined surface of the second auxiliary electrode may be disposed at a third inclination angle smaller than the first inclination angle.

The second electrode may be in contact with the second auxiliary electrode.

The common voltage line may include: a lower layer; an intermediate layer disposed on the lower layer; and an upper layer disposed on the intermediate layer, and having a width wider than that of the intermediate layer.

The third electrode may be in contact with a side surface of the intermediate layer, and the fourth electrode may be disposed on the third electrode.

The lower layer may have a width wider than that of the intermediate layer.

The display device may further include: a first layer disposed on the first electrode, the first layer including a pixel opening overlapping the first electrode; and a second layer disposed on the first layer, wherein the second auxiliary electrode and the second layer may be disposed on the same layer.

The first layer may include a bank layer having an upper surface, the second layer may include a separator layer having an edge adjacent to a pixel opening of the bank layer, and the edge of the separator layer may have a lower surface adjacent to the pixel opening and may not contact the upper surface of the bank layer.

A lower surface of the edge of the separator layer adjacent to the pixel opening may be in contact with the second electrode.

A portion of the bank layer adjacent to the pixel opening may have a thickness thinner than that of the remaining portion of the bank layer.

The second auxiliary electrode may be connected to the second layer.

A portion of the emission layer overlapping the second layer and a portion of the emission layer not overlapping the second layer may be separated from each other.

A portion of the emission layer overlapping the common voltage line and a portion of the emission layer not overlapping the common voltage line may be separated from each other.

A portion of the second electrode overlapping the second layer and a portion of the second electrode not overlapping the second layer may be connected to each other.

A portion of the second electrode overlapping the common voltage line and a portion of the second electrode not overlapping the common voltage line may be separated from each other.

The emission layer may include: a plurality of light emitting units; and a charge generation layer disposed between the plurality of light emitting cells.

The transistor may include: a semiconductor disposed on a substrate; a gate electrode overlapping the semiconductor; and a source electrode and a drain electrode connected to the semiconductor, and wherein the common voltage line, the source electrode, and the drain electrode may be disposed at the same layer.

The third electrode and the first electrode may be formed of the same material.

According to another aspect of the invention, a method of manufacturing a display device includes the steps of: forming a transistor on a substrate; forming a common voltage line spaced apart from the transistor on the substrate; forming a first electrode connected to the transistor; forming a third electrode connected to the common voltage line; forming a fourth electrode on the third electrode; forming an emission layer on the first electrode; and forming a second electrode on the emission layer and the fourth electrode.

The third electrode may be in contact with a side surface of the common voltage line.

The third electrode may include a first auxiliary electrode having a first inclined surface adjacent to a side surface of the common voltage line; and the fourth electrode may include a second auxiliary electrode having a second inclined surface adjacent to the first inclined surface of the first auxiliary electrode, and wherein: the first inclined surface of the first auxiliary electrode may be disposed at a first inclination angle, the side surface of the common voltage line may be disposed at a second inclination angle, the first inclination angle being smaller than the second inclination angle, and the second inclined surface of the second auxiliary electrode may be disposed at a third inclination angle smaller than the first inclination angle.

The second electrode may be in contact with the second auxiliary electrode.

The common voltage line may include: a lower layer; an intermediate layer disposed on the lower layer; and an upper layer disposed on the intermediate layer, and the intermediate layer is made of a material different from that of the upper layer, and has a width that becomes narrower than that of the upper layer by etching the intermediate layer after the common voltage line is formed.

The third electrode may be in contact with a side surface of the intermediate layer.

The intermediate layer may be made of a material different from that of the lower layer, and the intermediate layer may have a width that becomes narrower than that of the lower layer by an etching process of the intermediate layer.

The method may further comprise the steps of: forming a first layer on the first electrode; forming a pixel opening overlapping the first electrode in the first layer; forming a second layer on the first layer; and performing an ashing process to remove a portion of the first layer disposed under the second layer, wherein the fourth electrode and the second layer may be made of the same material and formed through the same process.

The transistor may include: a semiconductor disposed on a substrate; a gate electrode overlapping the semiconductor; and source and drain electrodes connected to the semiconductor, and the common voltage line is made of the same material and formed through the same process as the source and drain electrodes.

The third electrode and the first electrode may be made of the same material and formed through the same process.

It is to be understood that both the foregoing general description and the following detailed description are explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate illustrative embodiments of the invention and together with the description serve to explain the inventive concept.

FIG. 1 illustrates a cross-sectional view of an embodiment of a display device constructed in accordance with the principles of the invention.

Fig. 2 schematically shows an enlarged view of a partial region AA of fig. 1.

Fig. 3 shows a plurality of layers of an emission layer of the display device of fig. 1.

Fig. 4 shows a cross-sectional view of a display device according to a reference example.

Fig. 5 shows a circuit diagram of a representative pixel of the display device of fig. 1.

Fig. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 and 18 show illustrative sequential process cross-sectional views of a method of manufacturing the display device of fig. 1.

Fig. 19 shows a cross-sectional view of another embodiment of an emissive layer of the display device of fig. 1.

Fig. 20 illustrates a cross-sectional view of another embodiment of a display device constructed according to the principles of the present invention.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, "examples" and "embodiments" are interchangeable words and are non-limiting examples of apparatus or methods that employ one or more of the inventive concepts disclosed herein. It may be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments. Moreover, the various embodiments may be different, but are not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the embodiments may be used or practiced in another embodiment without departing from the inventive concept.

Unless otherwise indicated, the illustrated embodiments are to be understood as providing illustrative features of varying detail of some ways in which the inventive concepts may be practiced. Thus, unless otherwise specified, features, components, modules, layers, films, panels, regions, and/or aspects and the like (individually or collectively, "elements" hereinafter) of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality among the illustrated elements, and/or any other characteristic, attribute, property, etc., of an element. Further, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While embodiments may be practiced differently, the specific process sequence may be performed differently than described. For example, two consecutively described processes may be performed substantially simultaneously or in an order reverse to the order described. In addition, like reference numerals denote like elements.

When an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. For purposes of this specification, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements. Further, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes (such as x axis, y axis, and z axis) of a rectangular coordinate system, but may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be construed as X only, Y only, Z only, or any combination of two or more of X, Y and Z, such as XYZ, XYY, YZ and ZZ, for example. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms first, second, etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

For purposes of description, spatially relative terms such as "under 8230; \8230;," '823030;, "\8230; under," "under' 8230; \8230; above," "over," "on," "at 8230; \8230; above," "higher," "side" (e.g., as in "side walls"), etc., may be used herein and thus describe the relationship of one element to another (other) element as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "in the '8230;' 8230 ';' below 'can encompass both orientations in the' 8230; '8230'; 'above and in the' 8230; '8230'; 'below'. Further, the devices may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" are used in this specification, the stated features, integers, steps, operations, elements, components, and/or groups thereof are present but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as terms of degree, and as such are used to interpret the inherent variation of a measured value, a calculated value, and/or a provided value that would be recognized by one of ordinary skill in the art.

Various embodiments are described herein with reference to cross-sectional and/or exploded views as schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature and the shapes of these regions may not reflect the actual shape of a region of a device, and as such are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, a display device according to an embodiment of the invention will be described with reference to fig. 1, 2, and 3.

Fig. 1 shows a cross-sectional view of an embodiment of a display device constructed in accordance with the principles of the invention, fig. 2 shows an enlarged view of a portion AA of fig. 1, and fig. 3 shows layers of an emissive layer of the display device of fig. 1. Fig. 2 illustrates a common voltage line and a contact portion of a second electrode of a display device according to an embodiment, and fig. 3 illustrates a plurality of layers configuring an emission layer of the display device according to the embodiment.

As shown in fig. 1, the display device may include a substrate 110 and a semiconductor 1130, a gate electrode 1151, a source electrode 1173, and a drain electrode 1175 disposed on the substrate 110.

The substrate 110 may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. The substrate 110 may comprise a flexible material that may be bent or folded. For example, the substrate 110 may be a single layer or multiple layers.

The buffer layer 111 may be disposed on the substrate 110. The buffer layer 111 may have a single-layer structure or a multi-layer structure. The buffer layer 111 may include, for example, silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) And silicon oxynitride (SiO) _x N _y ) An inorganic insulating material or an organic insulating material. In some embodiments, the buffer layer 111 may be omitted. For example, a barrier layer may also be disposed between the substrate 110 and the buffer layer 111. The barrier layer may have a single-layer structure or a multi-layer structure. The barrier layer may comprise, for example, silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) And silicon oxynitride (SiO) _x N _y ) The inorganic insulating material of (1).

The semiconductor 1130 may be disposed on the buffer layer 111. The semiconductor 1130 may include a first region 1131, a channel 1132, and a second region 1133. The first and

second regions

1131 and 1133 may be disposed at respective sides of the channel 1132 of the semiconductor 1130. The semiconductor 1130 may include a semiconductor material such as amorphous silicon, polysilicon, or an oxide semiconductor.

The first gate insulating film 141 may be disposed on the semiconductor 1130. The first gate insulating film 141 may have a single-layer structure or a multi-layer structure. The first gate insulating film 141 may include, for example, silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) And silicon oxynitride (SiO) _x N _y ) The inorganic insulating material of (1).

The gate electrode 1151 may be disposed on the first gate insulating film 141. The gate electrode 1151 may overlap the channel 1132 of the semiconductor 1130. The gate electrode 1151 may have a single-layer structure or a multi-layer structure. The gate electrode 1151 may include a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti). After the gate electrode 1151 is formed, a doping process or plasma treatment may be performed on the semiconductor 1130. The portion of semiconductor 1130 covered by gate electrode 1151 may not be doped or plasma-treated, and the portion of semiconductor 1130 not covered by gate electrode 1151 may be doped or plasma-treated so as to be able to have the same characteristics as those of a doped semiconductor.

The second gate insulating film 142 may be disposed on the gate electrode 1151. The second gate insulating film 142 may have a single-layer structure or a multi-layer structure. The second gate insulating film 142 may include, for example, silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) And silicon oxynitride (SiO) _x N _y ) The inorganic insulating material of (1).

The first storage electrode 1153 may be disposed on the second gate insulating film 142. The first storage electrode 1153 may have a single layer structure or a multi-layer structure. The first storage electrode 1153 may include a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti). The first storage electrode 1153 may overlap the gate electrode 1151 to form a storage capacitor.

An interlayer insulating film 160 may be disposed on the first storage electrode 1153. The interlayer insulating film 160 may have a single-layer structure or a multi-layer structure. The interlayer insulating film 160 may include an inorganic insulating material or an organic insulating material.

A source electrode 1173 and a drain electrode 1175 may be disposed on the interlayer insulating film 160. The source electrode 1173 and the drain electrode 1175 may have a single-layer structure or a multi-layer structure. The source electrode 1173 and the drain electrode 1175 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu).

The source electrode 1173 and the drain electrode 1175 may include

lower layers

1173a and 1175a,

intermediate layers

1173b and 1175b, and

upper layers

1173c and 1175c. The

lower layers

1173a and 1175a may be directly provided on the interlayer insulating film 160.

Intermediate layers

1173b and 1175b may be disposed on the

lower layers

1173a and 1175 a.

Upper layers

1173c and 1175c may be disposed on the

intermediate layers

1173b and 1175 b. The

intermediate layers

1173b and 1175b may be made of a material different from that of the

lower layers

1173a and 1175a and the

upper layers

1173c and 1175c. For example, the

intermediate layers

1173b and 1175b may be made of aluminum (Al), while the

lower layers

1173a and 1175a and the

upper layers

1173c and 1175c may be made of titanium (Ti). However, this is only an example, and the materials of the

lower layers

1173a and 1175a, the

intermediate layers

1173b and 1175b, and the

upper layers

1173c and 1175c may be variously changed. In addition, the source electrode 1173 and the drain electrode 1175 may be formed as a double layer, or may be formed to have a form in which four or more layers are deposited.

The interlayer insulating film 160 may include an opening overlapping the source electrode 1173 and the first region 1131 of the semiconductor 1130. The source electrode 1173 may be connected to the first region 1131 of the semiconductor 1130 through the opening. The interlayer insulating film 160 may include an opening overlapping the drain electrode 1175 and the second region 1133 of the semiconductor 1130. The drain electrode 1175 may be connected to the second region 1133 of the semiconductor 1130 through the opening.

The semiconductor 1130, the gate electrode 1151, the source electrode 1173, and the drain electrode 1175 constitute one transistor TFT. In some embodiments, the transistor TFT may include only source and drain regions of the semiconductor 1130 without including the source and

drain electrodes

1173 and 1175.

The common voltage line 500 may be disposed on the interlayer insulating film 160. The common voltage line 500 may have a single-layer structure or a multi-layer structure. The common voltage line 500 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). The common voltage line 500 may be disposed at the same layer as the source electrode 1173 and the drain electrode 1175. The common voltage line 500 may be made of the same material as that of the source and

drain electrodes

1173 and 1175, and may be formed in the same process as that of the source and

drain electrodes

1173 and 1175.

The common voltage line 500 may include a lower layer 500a, an intermediate layer 500b, and an upper layer 500c. The lower layer 500a may be directly disposed on the interlayer insulating film 160. The intermediate layer 500b may be disposed on the lower layer 500 a. The upper layer 500c may be disposed on the middle layer 500b. The middle layer 500b may be made of a material different from that of the lower layer 500a and the upper layer 500c. For example, the intermediate layer 500b may be made of aluminum (Al), and the lower layer 500a and the upper layer 500c may be made of titanium (Ti). However, this is merely an example, and the materials of the lower layer 500a, the intermediate layer 500b, and the upper layer 500c may be variously changed. In addition, the common voltage line 500 may be formed in a double layer, or may be formed in a form in which four or more layers are deposited.

As shown in fig. 2, the width of the upper layer 500c of the common voltage line 500 may be wider than the width of the middle layer 500b. Accordingly, the side surface OS3 of the upper layer 500c may have a shape that is not aligned with the side surface OS2 of the intermediate layer 500b and protrudes much more than the side surface OS2 of the intermediate layer 500b. The lower surface of the upper layer 500c may be in contact with the upper surface of the intermediate layer 500b. However, at least a portion of the lower surface of the upper layer 500c may not be in contact with the upper surface of the intermediate layer 500b. The edge portion of the lower surface of the upper layer 500c may not contact the upper surface of the middle layer 500b.

The width of the lower layer 500a of the common voltage line 500 may be substantially the same as the width of the upper layer 500c of the common voltage line 500. The width of the lower layer 500a of the common voltage line 500 may be wider than the width of the middle layer 500b of the common voltage line 500. Accordingly, the side surface OS1 of the lower layer 500a may have a shape that is not aligned with the side surface OS2 of the intermediate layer 500b and protrudes much more than the side surface OS2 of the intermediate layer 500b. The upper surface of the lower layer 500a may be in contact with the lower surface of the middle layer 500b. However, at least a portion of the upper surface of the lower layer 500a may not be in contact with the lower surface of the intermediate layer 500b. An edge portion of the upper surface of the lower layer 500a may not contact the lower surface of the intermediate layer 500b.

The passivation film 180 may be disposed on the source electrode 1173 and the drain electrode 1175. The passivation film 180 may include an organic insulating material such as general-purpose polymer such as Polymethylmethacrylate (PMMA) or Polystyrene (PS), polymer derivatives having a phenol group, acryl-based polymer, imide-based polymer, polyimide, and siloxane-based polymer.

The first electrode 191 may be disposed on the passivation film 180. The first electrode 191 is also referred to as an anode electrode, and may be formed as a single layer or a plurality of layers including a transparent conductive oxide film or a metal material. The transparent conductive oxide film may include Indium Tin Oxide (ITO), poly-ITO, indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO). The metal material may include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al). For example, the first electrode 191 may have a structure in which a layer made of ITO, a layer made of silver (Ag), and a layer made of ITO are sequentially stacked.

The passivation film 180 may include an opening 181 overlapping the drain electrode 1175 and the first electrode 191. The first electrode 191 may be connected to the drain electrode 1175 through the opening 181. The first electrode 191 may be in contact with an upper surface of the upper layer 1175c of the drain electrode 1175. Accordingly, the first electrode 191 may receive an output current to be transmitted from the drain electrode 1175 to the emission layer 370.

The passivation film 180 may include an opening 183 overlapping the common voltage line 500. The common voltage line 500 may not be covered by the passivation film 180. For example, the upper surface and the side surface SS of the common voltage line 500 may be completely exposed through the opening 183. In addition, the upper surface of the interlayer insulating film 160 disposed around the common voltage line 500 may also be exposed through the opening 183.

A third electrode, which may be in the form of the first auxiliary electrode 600, may be disposed within the opening 183 of the passivation film 180. The first auxiliary electrode 600 may also be disposed on the passivation film 180. The first auxiliary electrode 600 may be disposed at the same layer as the first electrode 191. The first auxiliary electrode 600 may be made of the same material as the first electrode 191, and may be formed in the same process.

The first auxiliary electrode 600 may be disposed on the common voltage line 500, and may contact a side surface SS of the common voltage line 500. The first auxiliary electrode 600 may be disposed on the lower layer 500a of the common voltage line 500, and may be in contact with the side surface OS2 of the intermediate layer 500b. In addition, the first auxiliary electrode 600 may be disposed on the upper layer 500c of the common voltage line 500. The portion of the first auxiliary electrode 600 contacting the lower layer 500a and the intermediate layer 500b of the common voltage line 500 may be separated or disconnected from the portion of the first auxiliary electrode 600 disposed on the upper layer 500c of the common voltage line 500.

A first layer, which may be in the form of a bank layer 350, may be disposed on the first electrode 191, the first auxiliary electrode 600, and the passivation film 180. The bank layer 350 may also be referred to as a Pixel Defining Layer (PDL) and may include a pixel opening 351 overlapping the first electrode 191. In this case, the pixel opening 351 may overlap a central portion of the first electrode 191, and may not overlap an edge portion of the first electrode 191. Accordingly, the size of the pixel opening 351 may be smaller than the size of the first electrode 191. The bank layer 350 may be an organic insulating film including one or more of polyimide, polyamide, acryl resin, benzocyclobutene, and phenol resin. In some embodiments, the bank layer 350 may be formed as a Black Pixel Definition Layer (BPDL) including a black pigment.

The bank layer 350 may include an opening 353 overlapping the common voltage line 500. The opening 353 of the bank layer 350 may also overlap the opening 183 of the passivation film 180. The opening 353 of the bank layer 350 may have a width wider than that of the opening 183 of the passivation film 180. The opening 353 of the bank layer 350 may have a size larger than that of the common voltage line 500.

A second layer, which may be in the form of a separator layer 750, may be disposed on the bank layer 350. The edge of the separator layer 750 may be adjacent to the pixel opening 351 of the bank layer 350. A thickness of a portion of the bank layer 350 adjacent to an edge of the separator layer 750 may be thinner than a thickness of other portions of the bank layer 350. For example, a thickness of a portion of the bank layer 350 adjacent to the pixel opening 351 may be thinner than a thickness of the remaining portion of the bank layer 350. The lower surface of the separator layer 750 may be in contact with the upper surface of the bank layer 350. However, an edge portion of the lower surface of the separator layer 750 may not contact the upper surface of the bank layer 350. The separator layer 750 may be formed of a transparent conductive oxide film such as Indium Tin Oxide (ITO), poly-ITO, indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO).

A fourth electrode, which may be in the form of a second auxiliary electrode 700, may be disposed on the first auxiliary electrode 600. The second auxiliary electrode 700 may be disposed at the same layer as the separator layer 750. The second auxiliary electrode 700 may be made of the same material as that of the separator layer 750, and may be formed in the same process as that of the separator layer 750. The second auxiliary electrode 700 may or may not be connected to the separator layer 750.

The second auxiliary electrode 700 may be in contact with an upper surface of the first auxiliary electrode 600, and may be in contact with a side surface SS of the common voltage line 500. The second auxiliary electrode 700 may be in contact with the side surface OS2 of the middle layer 500b of the common voltage line 500. The second auxiliary electrode 700 may also be disposed on the upper layer 500c of the common voltage line 500. A portion of the second auxiliary electrode 700 contacting the side surface OS2 of the middle layer 500b of the common voltage line 500 may be separated or disconnected from a portion of the second auxiliary electrode 700 disposed on the upper layer 500c of the common voltage line 500.

The emission layer 370 may be disposed on the first electrode 191. As shown in fig. 3, the emission layer 370 may include a plurality of light emitting cells 1370 and 2370 and a charge generation layer 375, the charge generation layer 375 being disposed between the plurality of light emitting cells 1370 and 2370.

The plurality of light emitting units 1370 and 2370 may include a first light emitting unit 1370 and a second light emitting unit 2370. Each of the first light emitting unit 1370 and the second light emitting unit 2370 may include a plurality of layers. The first and second light emitting cells 1370 and 2370 may include

electron injection layers

1370a and 2370a, electron transport layers 1370b and 2370b, organic emission layers 1370c and 2370c, hole transport layers 1370d and 2370d, and

hole injection layers

1370e and 2370e, respectively. The organic emission layers 1370c and 2370c may include a low molecular weight organic material or a high molecular weight organic material that emits light such as red, green, and blue light. In another embodiment, at least some of the

electron injection layers

1370a and 2370a, the electron transport layers 1370b and 2370b, the hole transport layers 1370d and 2370d, and the

hole injection layers

1370e and 2370e may be omitted. The electron injection layer 1370a of the first light emitting cell 1370 may be in contact with the first electrode 191. The hole injection layer 2370e of the second light emitting cell 2370 may be in contact with the second electrode 270.

The charge generation layer 375 may be disposed between the first light emitting cell 1370 and the second light emitting cell 2370. The charge generation layer 375 may be a layer that generates electrons to serve as a cathode of one of the two light emitting cells 1370 and 2370 adjacent to each other and generates holes to serve as an anode of the other of the two light emitting cells 1370 and 2370. For example, the charge generation layer 375 may function as a cathode of the first light emitting unit 1370 and may function as an anode of the second light emitting unit 2370.

The charge generation layer 375 may include an n-type charge generation layer 375a and a p-type charge generation layer 375b. The n-type charge generation layer 375a and the p-type charge generation layer 375b may contact each other to form an NP junction. Electrons and holes may be simultaneously generated between the n-type charge generation layer 375a and the p-type charge generation layer 375b through the NP junction. The generated electrons may be transferred to one of the two light emitting cells 1370 and 2370 adjacent to each other through the n-type charge generation layer 375 a. The generated holes may be transported to the other of the two light emitting cells 1370 and 2370 adjacent to each other through the p-type charge generation layer 375b.

Although the emission layer 370 described above includes two light emitting cells, embodiments of the invention are not limited thereto. In another embodiment, the emission layer 370 may include three or more light emitting cells. For example, the emission layer 370 may include three light emitting cells and two charge generation layers disposed between the three light emitting cells.

The emission layer 370 may be disposed not only on the first electrode 191 but also on other regions on the substrate 110. The organic emission layers 1370c and 2370c of the emission layer 370 may be patterned to be disposed only within the pixel opening 351. The remaining layers except for the organic emission layers 1370c and 2370c may be entirely disposed on the substrate 110. The

electron injection layers

1370a and 2370a, the electron transport layers 1370b and 2370b, the hole transport layers 1370d and 2370d, the

hole injection layers

1370e and 2370e, and the charge generation layer 375 may be entirely disposed on the substrate 110.

A portion of the emission layer 370 disposed on the first electrode 191 may be separated or disconnected from other portions of the emission layer 370 disposed on the remaining portions except the first electrode 191. The emission layer 370 may be separated at an edge portion of the pixel opening 351 by the separator layer 750. For example, the emission layers 370 disposed at respective sides of the edge portion of the separator layer 750 may be separated from each other. A portion of the emission layer 370 overlapping the separator layer 750 and a portion of the emission layer 370 not overlapping the separator layer 750 may be separated from each other. A portion of the emission layer 370 disposed on the separator layer 750 and a portion of the emission layer 370 disposed within the pixel opening 351 may be separated from each other. The emission layer 370 may be formed as a plurality of layers, some of the emission layer 370 may be separated at edge portions of the pixel openings 351, and some other layers may be connected to each other. For example, the first light emitting unit 1370 and the charge generation layer 375 may be separated at an edge portion of the pixel opening 351, and the second light emitting units 2370 may be connected to each other.

The emission layer 370 may also be disposed on the second auxiliary electrode 700. In addition, the emission layer 370 may be disposed on an upper layer 500c of the common voltage line 500, and may overlap the common voltage line 500. A portion of the emission layer 370 overlapping the common voltage line 500 may be separated from a portion of the emission layer 370 not overlapping the common voltage line 500. A portion of the emission layer 370 disposed on the upper surface of the upper layer 500c of the common voltage line 500 may be separated from a portion of the emission layer 370 adjacent to the side surface SS of the common voltage line 500. For example, the emission layer 370 may be divided at an edge portion of the common voltage line 500. The emission layer 370 may be formed as a plurality of layers, and all layers of the emission layer 370 may be divided at an edge portion of the common voltage line 500. The side surface SS of the common voltage line 500 may not be covered by the emission layer 370. In addition, at least a portion of the edge of the second auxiliary electrode 700 may not be covered by the emission layer 370. A portion of the second auxiliary electrode 700 adjacent to the side surface SS of the common voltage line 500 may not be covered by the emission layer 370.

The second electrode 270 may be disposed on the emission layer 370. The second electrode 270 is also referred to as a cathode electrode, and may be formed of a transparent conductive layer including Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO). In addition, the second electrode 270 may have a semi-transparent property, and may form a micro-cavity together with the first electrode 191. The first electrode 191, the emission layer 370, and the second electrode 270 may form a Light Emitting Diode (LED).

The second electrode 270 may contact the emission layer 370. The emission layer 370 may be divided around the edges of the pixel opening 351 by the separator layer 750. The second electrodes 270 disposed on the portions in which the emission layers 370 are separated are not separated from each other, but may be connected to each other. For example, the second electrodes 270 may be connected to each other around the edges of the pixel openings 351. The overlapping portion of the second electrode 270 overlapping the separator layer 750 and the non-overlapping portion of the second electrode 270 not overlapping the separator layer 750 may be connected to each other. However, the step may be formed by the separated emission layer 370, and thus the overlapping portion and the non-overlapping portion of the second electrode 270 may not be smoothly connected to each other. The second electrode 270 may be in contact with a partial region of the separator layer 750. A lower surface of an edge of the separator layer 750 adjacent to the pixel opening 351 may contact the second electrode 270 without contacting an upper surface of the bank layer 350. For example, the second electrode 270 may be disposed between an edge of the separator layer 750 adjacent to the pixel opening 351 and the bank layer 350.

The second electrode 270 may be entirely disposed on the substrate 110. The second electrode 270 may be connected to the common voltage line 500. The common voltage ELVSS may be applied to the second electrode 270 and the common voltage line 500. Accordingly, when the second electrode 270 is not smoothly connected in some regions, the common voltage line 500 may prevent or minimize a voltage drop of the common voltage ELVSS in the second electrode 270.

The second electrode 270 may contact the side surface SS of the common voltage line 500. The second electrode 270 may directly contact the side surface SS of the common voltage line 500. Alternatively, the second electrode 270 may not directly contact the side surface SS of the common voltage line 500. The first and second

auxiliary electrodes

600 and 700 may be disposed between the second electrode 270 and the common voltage line 500. The first auxiliary electrode 600 may be in contact with the side surface OS2 of the middle layer 500b of the common voltage line 500, and the second auxiliary electrode 700 may be disposed on the first auxiliary electrode 600. The second electrode 270 may be in contact with the second auxiliary electrode 700. In a portion where the first auxiliary electrode 600 and the side surface SS of the common voltage line 500 contact each other, the first side surface IS1 of the first auxiliary electrode 600 IS disposed at the first inclination angle θ 1. The side surfaces SS (OS 1, OS2, and OS 3) of the common voltage line 500 are disposed at the second inclination angle θ 2, and the second side surface IS2 of the second auxiliary electrode may be disposed at the third inclination angle θ 3. The first inclination angle θ 1 may be smaller than the second inclination angle θ 2 of the side surface OS2 of the common voltage line 500, and the third inclination angle θ 3 of the second side surface IS2 of the second auxiliary electrode 700 may be smaller than the first inclination angle θ 1 (see fig. 2) of the first side surface IS1 of the first auxiliary electrode 600.

A portion of the second electrode 270 overlapping the common voltage line 500 may be separated or disconnected from a portion of the second electrode 270 not overlapping the common voltage line 500. A portion of the second electrode 270 disposed on the upper surface of the upper layer 500c of the common voltage line 500 may be separated from a portion of the second electrode 270 adjacent to the side surface SS of the common voltage line 500.

Referring to fig. 4, a display device according to a reference example and a display device according to fig. 2 will be compared and described. Fig. 4 shows a cross-sectional view of a display device according to a reference example in which the second auxiliary electrode is omitted from the display device.

In the display device according to the reference example, the first auxiliary electrode 600 may be in contact with the side surface SS of the common voltage line 500, and the emission layer 370 may be disposed on the first auxiliary electrode 600. The second electrode 270 may be disposed on the emission layer 370, and the second electrode 270 may not be connected to the first auxiliary electrode 600. The second electrode 270 and the first auxiliary electrode 600 may not be connected to each other through the emission layer 370 disposed between the second electrode 270 and the first auxiliary electrode 600. Accordingly, the second electrode 270 and the common voltage line 500 may not be connected, and a voltage drop may occur in the second electrode 270.

In the display device according to the embodiment of fig. 2, since the second auxiliary electrode 700 may be disposed on the first auxiliary electrode 600, the inclination angle of the connection portion CP between the second electrode 270 and the common voltage line 500 may be further reduced. Accordingly, the second electrode 270 may be smoothly connected to the common voltage line 500, thereby minimizing or preventing a voltage drop of the second electrode 270 from occurring. Therefore, a display device having uniform luminance as a whole can be implemented.

The first auxiliary electrode 600 and the first electrode 191 may be disposed at the same layer, and the second auxiliary electrode 700 and the separator layer 750 may be disposed at the same layer. For example, the first auxiliary electrode 600 and the first electrode 191 may be formed of the same material in the same process, and the second auxiliary electrode 700 and the separator layer 750 may be formed of the same material in the same process. Accordingly, the first and second

auxiliary electrodes

600 and 700 can be formed without an additional process, thereby reducing process costs.

An encapsulation layer may also be disposed on the second electrode 270. The encapsulation layer may protect a Light Emitting Diode (LED) from moisture or oxygen that may permeate from the outside, and may include at least one inorganic film and at least one organic film. For example, the encapsulation layer may have a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer may be stacked. However, this is merely an example, and the number of inorganic films and organic films configuring the encapsulation layer may be variously changed.

Although the structure in which one transistor is connected to a Light Emitting Diode (LED) has been described above, each Light Emitting Diode (LED) may be connected to a plurality of transistors. Hereinafter, with reference to fig. 5, an example of one representative pixel of a display device will be described.

As shown in fig. 5, the display device may include a plurality of pixels PX for displaying an image and a plurality of

signal lines

127, 151, 152, 153, 154, 171, and 172. The pixel PX may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to the plurality of

signal lines

127, 151, 152, 153, 154, 171, and 172, a capacitor Cst, and at least one light emitting diode LED. In the following description, an example in which the pixel PX includes one light emitting diode LED will be mainly described.

The signal lines 127, 151, 152, 153, 154, 171, and 172 may include an initialization voltage line 127, a plurality of

scan lines

151, 152, and 153, an emission control line 154, a data line 171, and a driving voltage line 172.

The initialization voltage line 127 may transmit an initialization voltage Vint. The plurality of

scan lines

151, 152, and 153 may transmit scan signals GWn, GIn, and GI (n + 1), respectively. The scan signals GWn, GIn, and GI (n + 1) may transmit gate-on voltages that may turn on the transistors T2, T3, T4, and T7 included in the pixel PX and gate-off voltages that may turn off the transistors T2, T3, T4, and T7 included in the pixel PX.

The

scan lines

151, 152, and 153 connected to the pixels PX may include a first scan line 151 capable of transmitting a scan signal GWn, a second scan line 152 capable of transmitting a scan signal GIn having a gate-on voltage at a timing different from that of the first scan line 151, and a third scan line 153 capable of transmitting a scan signal GI (n + 1). In the illustrated embodiment, an example in which the second scan line 152 transfers the gate-on voltage at a timing earlier than that of the first scan line 151 will be mainly described. For example, when the scan signal GWn is an nth scan signal Sn (where n is a natural number of 1 or more) among scan signals applied during one frame, the scan signal GIn may be a previous scan signal such as an (n-1) th scan signal S (n-1), and the scan signal GI (n + 1) may be the nth scan signal Sn. However, the embodiment is not limited thereto, and the scan signal GI (n + 1) may be a scan signal different from the nth scan signal Sn.

The emission control line 154 may transmit a control signal, and in particular, may transmit an emission control signal EM capable of controlling light emission of the light emitting diode LED included in the pixel PX. The control signal transmitted by the emission control line 154 may transmit a gate-on voltage and a gate-off voltage, and may have a waveform different from that of the scan signal transmitted by the

scan lines

151, 152, and 153.

The data line 171 may transmit a data signal Dm, and the driving voltage line 172 may transmit a driving voltage ELVDD. The data signal Dm may have different voltage levels according to an image signal input to the display device, and the driving voltage ELVDD may have a substantially constant voltage level.

The display device may further include a driver transmitting signals to the plurality of

signal lines

127, 151, 152, 153, 154, 171, and 172.

The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 included in the pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

The first scan line 151 may transmit a scan signal GWn to the second transistor T2 and the third transistor T3, the second scan line 152 may transmit a scan signal GIn to the fourth transistor T4, the third scan line 153 may transmit a scan signal GI (n + 1) to the seventh transistor T7, and the emission control line 154 may transmit an emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

The gate electrode G1 of the first transistor T1 may be connected to one end of the capacitor Cst via the driving gate node GN, the first electrode Ea1 of the first transistor T1 may be connected to the driving voltage line 172 via the fifth transistor T5, and the second electrode Eb1 of the first transistor T1 may be connected to the anode of the light emitting diode LED via the sixth transistor T6. The first transistor T1 may receive the data signal Dm transmitted by the data line 171 according to the switching operation of the second transistor T2 to supply the driving current Id to the light emitting diode LED.

The gate electrode G2 of the second transistor T2 may be connected to the first scan line 151, the first electrode Ea2 of the second transistor T2 may be connected to the data line 171, and the second electrode Eb2 of the second transistor T2 may be connected to the first electrode Ea1 of the first transistor T1 and may be connected to the driving voltage line 172 via the fifth transistor T5. The second transistor T2 may be turned on according to a scan signal GWn transmitted through the first scan line 151 to transmit a data signal Dm transmitted from the data line 171 to the first electrode Ea1 of the first transistor T1.

A gate electrode G3 of the third transistor T3 may be connected to the first scan line 151, and a first electrode Ea3 of the third transistor T3 may be connected to the second electrode Eb1 of the first transistor T1 and may be connected to an anode electrode of the light emitting diode LED via the sixth transistor T6. The second electrode Eb3 of the third transistor T3 may be connected to the second electrode Eb4 of the fourth transistor T4, one end of the capacitor Cst, and the gate electrode G1 of the first transistor T1. The third transistor T3 may be turned on in response to a scan signal GWn transmitted through the first scan line 151 to connect the gate electrode G1 and the second electrode Eb1 of the first transistor T1 to each other, to diode-connect the first transistor T1.

The gate electrode G4 of the fourth transistor T4 may be connected to the second scan line 152, the first electrode Ea4 of the fourth transistor T4 may be connected to a terminal of the initialization voltage Vint, and the second electrode Eb4 of the fourth transistor T4 may be connected to one end of the capacitor Cst and the gate electrode G1 of the first transistor T1 through the second electrode Eb3 of the third transistor T3. The fourth transistor T4 may be turned on according to the scan signal GIn received through the second scan line 152 to transmit the initialization voltage Vint to the gate electrode G1 of the first transistor T1 to perform an initialization operation for initializing a voltage of the gate electrode G1 of the first transistor T1.

The gate electrode G5 of the fifth transistor T5 may be connected to the emission control line 154, the first electrode Ea5 of the fifth transistor T5 may be connected to the driving voltage line 172, and the second electrode Eb5 of the fifth transistor T5 may be connected to the first electrode Ea1 of the first transistor T1 and the second electrode Eb2 of the second transistor T2.

The gate electrode G6 of the sixth transistor T6 may be connected to the emission control line 154, the first electrode Ea6 of the sixth transistor T6 may be connected to the second electrode Eb1 of the first transistor T1 and the first electrode Ea3 of the third transistor T3, and the second electrode Eb6 of the sixth transistor T6 may be electrically connected to the anode electrode of the light emitting diode LED. The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on in response to the emission control signal EM received through the emission control line 154, and by this, the driving voltage ELVDD may be compensated through the diode-connected first transistor T1 to transmit the driving voltage ELVDD to the light emitting diode LED.

The gate electrode G7 of the seventh transistor T7 may be connected to the third scan line 153, the first electrode Ea7 of the seventh transistor T7 may be connected to the second electrode Eb6 of the sixth transistor T6 and the anode of the light emitting diode LED, and the second electrode Eb7 of the seventh transistor T7 may be connected to the terminal of the initialization voltage Vint and the first electrode Ea4 of the fourth transistor T4.

The transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type channel transistors such as PMOS, but the embodiment is not limited thereto, and at least one of the transistors T1, T2, T3, T4, T5, T6, and T7 may be an N-type channel transistor.

As described above, one end of the capacitor Cst may be connected to the gate electrode G1 of the first transistor T1, and the other end of the capacitor Cst may be connected to the driving voltage line 172. The cathode of the light emitting diode LED may be connected to a common voltage ELVSS terminal transmitting the common voltage ELVSS to receive the common voltage ELVSS.

Although the pixel PX is described above as including seven transistors T1, T2, T3, T4, T5, T6, and T7, one capacitor Cst, and one light emitting diode LED, this is merely an example, and the number of transistors, the number of capacitors, the number of light emitting diode LEDs, and their connection relationship may be variously changed.

Hereinafter, a method of manufacturing a display device according to an embodiment will be described with reference to fig. 6 to 18.

Fig. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 and 18 are sequential process sectional views illustrating a method of manufacturing the display device of fig. 1.

As shown in fig. 6, a buffer layer 111 may be formed on the substrate 110 by using an inorganic insulating material or an organic insulating material. The semiconductor 1130 may be formed on the buffer layer 111 by using a semiconductor material. The semiconductor material may be made of amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like. The first gate insulating film 141 may be formed on the semiconductor 1130 and the buffer layer 111 by using an inorganic insulating material.

The gate electrode 1151 may be formed by depositing a metal material on the first gate insulating film 141 and patterning the deposited metal material. The gate electrode 1151 may overlap the semiconductor 1130. After the gate electrode 1151 is formed, a portion of the semiconductor 1130 which does not overlap with the gate electrode 1151 may be processed by a doping process or plasma treatment to have a doped semiconductor property. Therefore, a portion of the semiconductor 1130 overlapping with the gate electrode 1151 becomes the channel 1132, and portions of the semiconductor 1130 not overlapping with the gate electrode 1151 become the first region 1131 and the second region 1133. The second gate insulating film 142 may be formed by using an inorganic insulating material over the gate electrode 1151 and the first gate insulating film 141.

The first storage electrode 1153 may be formed by depositing a metal material on the second gate insulating film 142 and patterning the deposited metal material. The first storage electrode 1153 may overlap the gate electrode 1151. The interlayer insulating film 160 may be formed by using an inorganic insulating material or an organic insulating material on the first storage electrode 1153 and the second gate insulating film 142. The interlayer insulating film 160 may be patterned to form an opening that exposes at least a portion of the first region 1131 and the second region 1133 of the semiconductor 1130.

A metal material may be continuously deposited on the interlayer insulating film 160 and patterned to form the source electrode 1173 and the drain electrode 1175. A source electrode 1173 may be connected to the first region 1131 of the semiconductor 1130 through the opening, and a drain electrode 1175 may be connected to the second region 1133 of the semiconductor 1130 through the opening. The metal material may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). For example, three layers may be formed by sequentially stacking titanium (Ti), aluminum (Al), and titanium (Ti). The source electrode 1173 and the drain electrode 1175 may include

lower layers

1173a and 1175a,

intermediate layers

1173b and 1175b, and

upper layers

1173c and 1175c.

The common voltage line 500 may be formed on the interlayer insulating film 160. The common voltage line 500, the source electrode 1173, and the drain electrode 1175 may be made of the same material and in the same process. For example, the source electrode 1173, the drain electrode 1175, and the common voltage line 500 may be formed together by sequentially depositing and patterning a metal material. Accordingly, the common voltage line 500, the source electrode 1173, and the drain electrode 1175 may be disposed on the same layer (e.g., the interlayer insulating film 160). The common voltage line 500 may include a lower layer 500a, an intermediate layer 500b, and an upper layer 500c. The lower layer 500a of the common voltage line 500, the lower layer 1173a of the source electrode 1173, and the lower layer 1175a of the drain electrode 1175 may be made of the same material, and may be disposed on the same layer (for example, the interlayer insulating film 160). The intermediate layer 500b of the common voltage line 500, the intermediate layer 1173b of the source electrode 1173, and the intermediate layer 1175b of the drain electrode 1175 may be made of the same material, and may be disposed on the same material layer (e.g., the

lower layers

1173a, 1175a, and 500 a). The upper layer 500c of the common voltage line 500, the upper layer 1173c of the source electrode 1173, and the upper layer 1175c of the drain electrode 1175 may be made of the same material, and may be disposed on the same material layer (the

intermediate layers

1173b, 1175b, and 500 b).

As shown in fig. 7, the passivation film 180 may be formed by using an organic insulating material on the source electrode 1173, the drain electrode 1175, and the common voltage line 500. For example, the

openings

181 and 183 may be formed by patterning the passivation film 180.

At least a portion of drain electrode 1175 may be exposed through opening 181. At least a portion of the upper surface of upper layer 1175c of drain electrode 1175 may be exposed through opening 181.

At least a portion of the common voltage line 500 may be exposed through the opening 183. The upper surface of the upper layer 500c, the side surface OS1 (see fig. 8) of the lower layer 500a, the side surface of the intermediate layer 500b, and the side surface OS3 (see fig. 8) of the upper layer 500c of the common voltage line 500 may be exposed through the opening 183. In addition, the upper surface of the interlayer insulating film 160 disposed around the common voltage line 500 may also be exposed through the opening 183.

As shown in fig. 8, the intermediate layer 500b of the common voltage line 500 may be etched. The middle layer 500b of the common voltage line 500 may be made of a material different from that of the upper layer 500c and the lower layer 500a of the common voltage line 500. For example, the intermediate layer 500b may be selectively etched by an etchant that can etch only the intermediate layer 500b in an etching process. Accordingly, the intermediate layer 500b may be etched to form the side surface OS2 exposed through the opening 183, and the width of the intermediate layer 500b may become narrower than the width of the upper layer 500c. Accordingly, the side surface OS3 of the upper layer 500c may have a shape that is not aligned with the side surface OS2 of the intermediate layer 500b and protrudes much more than the side surface OS2 of the intermediate layer 500b. The edge portion of the lower surface of the upper layer 500c may not contact the upper surface of the middle layer 500b. In addition, the width of the middle layer 500b may be narrower than that of the lower layer 500 a. Accordingly, the side surface OS1 of the lower layer 500a may have a shape that is not aligned with the side surface OS2 of the intermediate layer 500b and protrudes much more than the side surface OS2 of the intermediate layer 500b. An edge portion of the upper surface of the lower layer 500a may not contact the lower surface of the middle layer 500b.

In the step of etching the intermediate layer 500b of the common voltage line 500, the source electrode 1173 and the drain electrode 1175 may not be etched. Since the source electrode 1173 is completely covered with the passivation film 180, the source electrode 1173 may not be etched. Since only the upper surface of the upper layer 1175c of the drain electrode 1175 is exposed through the opening 181, and the intermediate layer 1175b of the drain electrode 1175 is not exposed through the opening 181, the intermediate layer 1175b of the drain electrode 1175 may not be etched.

As shown in fig. 9, a first conductive material layer 1900 may be formed on the passivation film 180. The first conductive material layer 1900 may be formed as a single layer including a transparent conductive oxide film or a metal material, or a multi-layer including a transparent conductive oxide film or a metal material. For example, the first conductive material layer 1900 may be formed by sequentially stacking ITO, silver (Ag), and ITO. The first conductive material layer 1900 may be entirely formed on the substrate 110. The first conductive material layer 1900 may be directly disposed on the passivation film 180. The first conductive material layer 1900 may also be formed in the

openings

181 and 183 of the passivation film 180. In the opening 183 of the passivation film 180, the first conductive material layer 1900 may also be disposed on the common voltage line 500. The first conductive material layer 1900 may be in contact with the upper surface and the side surface OS1 (see fig. 8) of the lower layer 500a of the common voltage line 500, may be in contact with the side surface OS2 (see fig. 8) of the intermediate layer 500b, and may be in contact with the upper surface of the upper layer 500c. A portion 1900 (see fig. 10) of the first conductive material layer 1900 contacting the lower layer 500a and the intermediate layer 500b of the common voltage line 500 may be separated or disconnected from a portion 1900 (see fig. 10) of the first conductive material layer 1900 contacting the upper layer 500c of the common voltage line 500.

As shown in fig. 10, a photoresist 900 may be coated on the first conductive material layer 1900 and a photo process may be performed. The photoresist 900 may be a polymer compound including all of photosensitivity, adhesiveness, and corrosion resistance, and its properties may be changed when light is irradiated on the photoresist 900. By patterning the photoresist 900, the photoresist 900 disposed in some regions may be removed. The photoresist 900 disposed in the peripheral region of the connection portion between the transistor TFT and the first conductive material layer 1900 and the peripheral region of the common voltage line 500 may remain. The photoresist 900 may be formed to fill the opening 183 of the passivation film 180, and the common voltage line 500 may be completely covered by the photoresist 900.

As shown in fig. 11, the first conductive material layer 1900 may be etched by using the patterned photoresist 900 as a mask. By patterning the first conductive material layer 1900, the first electrode 191 and the first auxiliary electrode 600 may be formed. The first electrode 191 may be connected to the drain electrode 1175 of the transistor TFT through the opening 181 of the passivation film 180. The first auxiliary electrode 600 may be disposed within the opening 183 of the passivation film 180. The first auxiliary electrode 600 may also be disposed on the passivation film 180. The first electrode 191 and the first auxiliary electrode 600 may be disposed at the same layer. The first electrode 191 and the first auxiliary electrode 600 may be made of the same material and may be formed in the same process.

The first auxiliary electrode 600 may be disposed on the common voltage line 500, and the first auxiliary electrode 600 may be brought into contact with a side surface SS (see fig. 8) of the common voltage line 500. The first auxiliary electrode 600 may be disposed on the lower layer 500a of the common voltage line 500, and may be in contact with the side surface OS2 of the intermediate layer 500b. The first auxiliary electrode 600 may also be disposed on the upper layer 500c of the common voltage line 500. A portion 600 u 1 of the first auxiliary electrode 600 contacting the lower layer 500a and the middle layer 500b of the common voltage line 500 may be separated or disconnected from a portion 600 u 2 of the first auxiliary electrode 600 disposed on the upper layer 500c of the common voltage line 500.

In the step of etching the first conductive material layer 1900, the common voltage line 500 may be covered with the photoresist 900, and thus the common voltage line 500 may not be affected by an etchant for etching the first conductive material layer 1900. For example, the common voltage line 500 may be protected by a photoresist 900. Accordingly, the photoresist 900 may prevent the intermediate layer 500b of the common voltage line 500 from being damaged by the etchant.

As shown in fig. 12, all of the patterned photoresist 900 may be removed. Accordingly, the first electrode 191 and the first auxiliary electrode 600 disposed under the photoresist 900 may be exposed.

As shown in fig. 13, the bank layer 350 may be formed on the first electrode 191, the first auxiliary electrode 600, and the passivation film 180 by using an organic insulating material. The bank layer 350 may be patterned to form a pixel opening 351 and an opening 353. The pixel opening 351 may overlap the first electrode 191. For example, the first electrode 191 may be exposed through the pixel opening 351. The opening 353 may overlap the common voltage line 500. For example, the common voltage line 500 may be exposed through the opening 353. The opening 353 of the bank layer 350 may also overlap the opening 183 of the passivation film 180. The opening 353 of the bank layer 350 may have a width wider than that of the opening 183 of the passivation film 180. The size of the opening 353 of the bank layer 350 may be larger than that of the common voltage line 500.

As shown in fig. 14, a second conductive material layer 1700 may be formed on the first electrode 191, the first auxiliary electrode 600, and the bank layer 350. The second conductive material layer 1700 may be formed of a transparent conductive oxide film such as Indium Tin Oxide (ITO), poly-ITO, indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), and Indium Tin Zinc Oxide (ITZO). The second conductive material layer 1700 may be entirely formed on the substrate 110. A second conductive material layer 1700 may also be formed in the pixel opening 351 and the opening 353 of the bank layer 350.

As shown in fig. 15, the separator layer 750 and the second auxiliary electrode 700 may be formed by patterning the second conductive material layer 1700. The separator layer 750 and the second auxiliary electrode 700 may be disposed at the same layer. The separator layer 750 and the second auxiliary electrode 700 may be made of the same material and may be formed in the same process.

The separator layer 750 may be formed to surround the pixel opening 351 of the bank layer 350. The edge of the separator layer 750 may be adjacent to the pixel opening 351 of the bank layer 350. In this case, the edge of the separator layer 750 may be disposed outside the pixel opening 351 of the bank layer 350. The lower surface of the separator layer 750 may be in contact with the upper surface of the bank layer 350.

The second auxiliary electrode 700 may be in contact with an upper surface of the first auxiliary electrode 600, and may be in contact with a side surface SS (see fig. 8) of the common voltage line 500. The second auxiliary electrode 700 may be in contact with the side surface OS2 of the middle layer 500b of the common voltage line 500. The second auxiliary electrode 700 may also be disposed on the upper layer 500c of the common voltage line 500. A portion of the second auxiliary electrode 700 contacting the side surface OS2 of the middle layer 500b of the common voltage line 500 may be separated or disconnected from a portion of the second auxiliary electrode 700 disposed on the upper layer 500c of the common voltage line 500.

As shown in fig. 16, the thickness of a portion of the bank layer 350 may be reduced by performing an ashing process. Most of the bank layer 350 may be covered by the separator layer 750 and the second auxiliary electrode 700. A portion of the bank layer 350 disposed around the pixel opening 351 may not be covered by the separator layer 750, but exposed. A portion of the bank layer 350 disposed around the pixel opening 351 may be removed through an ashing process. Accordingly, a thickness of a portion of the bank layer 350 adjacent to the edge of the separator layer 750 may be thinner than a thickness of other portions of the bank layer 350. The lower surface of the edge of the separator layer 750 may not contact the upper surface of the bank layer 350.

As shown in fig. 17, the emission layer 370 may be formed on the first electrode 191, the separator layer 750, and the second auxiliary electrode 700. The emission layer 370 may be formed by sequentially depositing a plurality of layers. Some of the layers may be formed to be disposed only within the pixel opening 351 and other layers of the layers may be entirely formed on the substrate 110. However, embodiments are not limited thereto, and the plurality of layers may be entirely formed on the substrate 110. When the emission layer 370 includes a plurality of light emitting cells, a charge generation layer may be disposed between the plurality of light emitting cells.

The portion of the emission layer 370 disposed on the first electrode 191 may be separated or disconnected from other portions of the emission layer 370 disposed on the remaining portions except the first electrode 191. The emission layer 370 may be separated by a separator layer 750 at an edge portion of the pixel opening 351. The emission layer 370 may be formed as a plurality of layers, some of the emission layer 370 may be divided at edge portions of the pixel opening 351, and some other layers may be connected.

The emission layer 370 may also be disposed on the second auxiliary electrode 700 and the upper layer 500c of the common voltage line 500. A portion 370 u 1 of the emission layer 370 disposed on the second auxiliary electrode 700 may be separated or disconnected from a portion 370 u 2 of the emission layer 370 disposed on an upper layer 500c of the common voltage line 500. The emission layer 370 may be divided at an edge portion of the common voltage line 500. The emission layer 370 may be formed as a plurality of layers, and all layers of the emission layer 370 may be separated at an edge portion of the common voltage line 500. The side surface SS (see fig. 8) of the common voltage line 500 may not be covered by the emission layer 370. In addition, at least a portion of the edge of the second auxiliary electrode 700 may not be covered by the emission layer 370.

As shown in fig. 18, the second electrode 270 may be formed by using a conductive material on the emission layer 370. The second electrode 270 may be formed of a transparent conductive oxide layer or a semi-transparent conductive material.

The second electrode 270 may be directly disposed on the emission layer 370, and the second electrode 270 may be entirely formed on the substrate 110. The second electrode 270 may be connected to the common voltage line 500. A common voltage ELVSS (see fig. 5) may be applied to the second electrode 270 and the common voltage line 500. Therefore, even if the second electrode 270 is not smoothly connected in some regions, a voltage drop can be prevented from occurring.

The second electrode 270 may be in contact with the side surface SS (OS 1, OS2, and OS3 in fig. 2) of the common voltage line 500. The second electrode 270 may or may not directly contact the side surface SS of the common voltage line 500. The first and second

auxiliary electrodes

600 and 700 may be disposed between the second electrode 270 and the common voltage line 500. The first auxiliary electrode 600 may be in contact with the side surface OS2 of the middle layer 500b of the common voltage line 500, and the second auxiliary electrode 700 may be disposed on the first auxiliary electrode 600. The second electrode 270 may be in contact with the second auxiliary electrode 700. In a portion in which the first auxiliary electrode 600 and the side surface SS of the common voltage line 500 contact each other, a first inclination angle θ 1 of the first side surface IS1 of the first auxiliary electrode 600 may be smaller than a second inclination angle θ 2 of the side surface OS2 of the common voltage line 500, and a third inclination angle θ 3 of the second side surface IS2 of the second auxiliary electrode 700 may be smaller than the first inclination angle θ 1 of the first side surface IS1 of the first auxiliary electrode 600 (see fig. 2). Accordingly, the second electrode 270 and the common voltage line 500 may be smoothly connected by the first and second

auxiliary electrodes

600 and 700, and a voltage drop of the common voltage ELVSS in the second electrode 270 may be reduced or prevented, and a display device having substantially uniform luminance as a whole may be implemented.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 19.

Since many portions of the display device of fig. 19 are the same as those of the display device of fig. 1, a repetitive description will be omitted to avoid redundancy. The illustrated embodiment differs from the previously described embodiment of fig. 1 in that: the emission layer is formed of a single light emitting cell, which will be further described below.

Fig. 19 shows a cross-sectional view of another embodiment of an emissive layer of the display device of fig. 1. Fig. 19 illustrates a plurality of layers constructing an emission layer of a display device according to an embodiment.

As shown in fig. 19, the display device may include an emission layer 370. In the previous embodiment, the emission layer 370 may include a plurality of light emitting cells and a charge generation layer disposed between the plurality of light emitting cells, and in the illustrated embodiment, the emission layer 370 may be formed of a single light emitting cell.

The emission layer 370 may include an electron injection layer 370a, an electron transport layer 370b, an organic emission layer 370c, a hole transport layer 370d, and a hole injection layer 370e. The organic emission layer 370c may include a low molecular weight organic material or a high molecular weight organic material that emits light such as red, green, and blue light. In another embodiment, at least some of the electron injection layer 370a, the electron transport layer 370b, the hole transport layer 370d, and the hole injection layer 370e may be omitted. The electron injection layer 370a may be in contact with the first electrode. The hole injection layer 370e may be in contact with the second electrode.

In the illustrated embodiment, the emissive layer 370 may not include a charge generation layer.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 20.

Since many parts of the display device of fig. 20 are the same as those of the display device of fig. 1, a repetitive description will be omitted to avoid redundancy. The illustrated embodiment differs from the previously described embodiment of fig. 1 in that the separator layer is omitted, as will be described further below.

Fig. 20 shows a cross-sectional view of another embodiment of the display device of fig. 1.

As shown in fig. 20, the display device may include a substrate 110, a transistor TFT, a first electrode 191, an emission layer 370, a second electrode 270, a common voltage line 500, a first auxiliary electrode 600, and a second auxiliary electrode 700.

In the previous embodiment, a separator layer 750 may also be included, and the emission layer 370 may be separated by the separator layer 750 in at least a partial region. In the illustrated embodiment, the separator layer 750 may be omitted.

The emission layer 370 is not divided at an edge portion of the pixel opening 351 and may have a connected structure. The emission layer 370 may be formed of a single light emitting unit, and may not include a charge generation layer. A thickness of a portion of the bank layer 350 adjacent to the pixel opening 351 may be substantially the same as a thickness of other portions of the bank layer 350. For example, the thickness of the bank layer 350 may be uniform as a whole.

The second auxiliary electrode 700 may be disposed on the first auxiliary electrode 600 and the bank layer 350. However, the embodiment is not limited thereto, and the second auxiliary electrode 700 may not be disposed on the bank layer 350. The second auxiliary electrode 700 may completely cover the first auxiliary electrode 600. However, the embodiment is not limited thereto, and the second auxiliary electrode 700 may cover a portion of the first auxiliary electrode 600.

While certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but is to be accorded the widest scope consistent with the claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising:

a substrate;

a transistor disposed on the substrate;

a first electrode connected to the transistor;

an emission layer disposed on the first electrode;

a second electrode disposed on the emission layer;

a common voltage line connected to the second electrode; and

and third and fourth electrodes disposed between the common voltage line and the second electrode.

2. The display device according to claim 1,

the third electrode includes a first auxiliary electrode contacting a side surface of the common voltage line, and

the fourth electrode includes a second auxiliary electrode disposed on the first auxiliary electrode.

3. The display device according to claim 2, wherein:

the first auxiliary electrode includes a first inclined surface adjacent to the side surface of the common voltage line; and is provided with

The second auxiliary electrode includes a second inclined surface adjacent to the first inclined surface of the first auxiliary electrode, and wherein:

the first inclined surface of the first auxiliary electrode is disposed at a first inclination angle, the side surface of the common voltage line is disposed at a second inclination angle, and the first inclination angle is smaller than the second inclination angle; and is

The second inclined surface of the second auxiliary electrode is disposed at a third inclination angle smaller than the first inclination angle.

4. The display device according to claim 3,

the second electrode is in contact with the second auxiliary electrode.

5. The display device of claim 1, wherein the common voltage line comprises:

a lower layer of the film is provided,

an intermediate layer disposed on the lower layer, an

An upper layer disposed on the intermediate layer and

the upper layer has a width wider than a width of the intermediate layer.

6. The display device according to claim 5, wherein:

the third electrode is in contact with a side surface of the intermediate layer, and

the fourth electrode is disposed on the third electrode.

7. The display device according to claim 5, wherein the lower layer has a width wider than a width of the intermediate layer.

8. The display device according to claim 2, further comprising:

a first layer disposed on the first electrode, the first layer including a pixel opening overlapping the first electrode; and

a second layer disposed on the first layer,

wherein the second auxiliary electrode and the second layer are disposed at the same layer.

9. The display device according to claim 8, wherein:

the first layer comprises a bank layer having an upper surface,

the second layer comprising a separator layer having an edge adjacent the pixel opening of the bank layer,

the edge of the separator layer has a lower surface adjacent to the pixel opening and not in contact with the upper surface of the bank layer,

the lower surface of the edge of the separator layer adjacent to the pixel opening is in contact with the second electrode, and

a portion of the bank layer adjacent to the pixel opening has a thickness thinner than a thickness of a remaining portion of the bank layer.

10. The display device according to claim 8, wherein a portion of the emission layer overlapping the second layer and a portion of the emission layer not overlapping the second layer are separated from each other.

11. The display device according to claim 8, wherein a portion of the second electrode which overlaps with the second layer and a portion of the second electrode which does not overlap with the second layer are connected to each other.

12. A method of manufacturing a display device, the method comprising the steps of:

forming a transistor on a substrate;

forming a common voltage line on the substrate spaced apart from the transistor;

forming a first electrode connected to the transistor;

forming a third electrode connected to the common voltage line;

forming a fourth electrode on the third electrode;

forming an emission layer on the first electrode; and

forming a second electrode on the emission layer and the fourth electrode.

13. The method of claim 12, wherein the third electrode is in contact with a side surface of the common voltage line,

wherein:

the third electrode includes a first auxiliary electrode having a first inclined surface adjacent to a side surface of the common voltage line; and is

The fourth electrode comprises a second auxiliary electrode having a second inclined surface adjacent to the first inclined surface of the first auxiliary electrode, and wherein:

the first inclined surface of the first auxiliary electrode is disposed at a first inclination angle,

the side surfaces of the common voltage line are disposed at a second inclination angle, the first inclination angle is smaller than the second inclination angle, and

the second inclined surface of the second auxiliary electrode is disposed at a third inclination angle smaller than the first inclination angle, and

wherein the second electrode is in contact with the second auxiliary electrode.

14. The method of claim 12, wherein the common voltage line comprises:

a lower layer of the film is provided,

an intermediate layer disposed on the lower layer, an

An upper layer disposed on the intermediate layer and

the intermediate layer is made of a material different from that of the upper layer, and

the intermediate layer has a width that becomes narrower than a width of the upper layer by etching the intermediate layer after the common voltage line is formed,

wherein the third electrode is in contact with a side surface of the intermediate layer, and

wherein:

the intermediate layer is made of a material different from that of the lower layer, and

the intermediate layer has a width that becomes narrower than a width of the lower layer by an etching process of the intermediate layer.

15. The method of claim 12, further comprising the steps of:

forming a first layer on the first electrode;

forming a pixel opening in the first layer overlapping the first electrode;

forming a second layer on the first layer; and

performing an ashing process on the first layer to remove a portion of the first layer disposed under the second layer,

wherein the fourth electrode and the second layer are made of the same material and are formed by the same process.