CN115544928A - Circuit optimization method based on circuit global information - Google Patents
Circuit optimization method based on circuit global information Download PDFInfo
- Publication number
- CN115544928A CN115544928A CN202211219682.6A CN202211219682A CN115544928A CN 115544928 A CN115544928 A CN 115544928A CN 202211219682 A CN202211219682 A CN 202211219682A CN 115544928 A CN115544928 A CN 115544928A
- Authority
- CN
- China
- Prior art keywords
- circuit
- equivalence
- method based
- global information
- equivalent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/323—Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The invention discloses a circuit optimization method based on circuit global information, which comprises the following steps: rewriting rules by using equivalent saturation reasoning; converting the circuit intermediate format into corresponding equivalent graph e-graphs; applying a rewrite rule by utilizing equivalence saturation to obtain all possible equivalence substitutions; the target solution is searched from all possible equivalent alternatives. The invention has the advantages of simple principle, simple and convenient operation, flexibility, universality and the like.
Description
Technical Field
The invention mainly relates to the technical field of optimization of very large scale integrated circuits, in particular to a circuit optimization method based on circuit global information.
Background
With the increasing complexity of modern VLSI (Very Large Scale Integration) system design, the importance of circuit optimization is becoming more and more apparent. In recent years, based on the existing popular high-level programming languages, such as Scala, python, etc., DSL, a trend of designing a domain-specific language has been. These DSLs heavily borrow on compilation technology and introduce an intermediate format similar to LLVM. However, currently, circuit optimization based on intermediate formats is not yet mature.
The existing circuit optimization method mainly aims at the circuit optimization method with complex calculation problems such as Digital Signal Processing (DSP) and the like. When the circuit is optimized, the data flow is calculated and expressed into a Taylor expansion diagram TED form and the like, and the aim of circuit optimization is achieved by means of decomposition of algebraic expressions, elimination of common subexpressions, replacement of expressions with constant multiplication by addition and shifting and the like.
However, the existing conventional methods still have some technical disadvantages:
1. the traditional method mainly focuses on data stream calculation in a combined circuit, and lacks a means for uniformly optimizing a general circuit.
2. The traditional method is excellent in local optimization of the circuit, but the architecture of the given circuit is hardly changed, and the result of global optimization of the circuit cannot be obtained.
3. The traditional method can not flexibly obtain different optimization results according to optimization targets (such as area, unit number, time delay and the like).
As can be seen from the above, the technical deficiencies summarized above are drawbacks of the conventional circuit optimization. In the design optimization method of the circuit global information, the optimization time directly influences the final optimization effect, and the overhead generated in the optimization by a similar optimization design method based on the circuit global information is inevitable.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a circuit optimization method based on circuit global information, which is simple in principle, simple and convenient to operate, flexible and universal.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method of circuit optimization based on circuit global information, comprising:
rewriting rules by using equivalent saturation reasoning;
converting the intermediate format of the circuit into corresponding equivalent graphs;
applying a rewrite rule by utilizing equivalence saturation to obtain all possible equivalence substitutions;
the target solution is searched from all possible equivalent alternatives.
As a further improvement of the process of the invention: enumerating expressions in the equivalent graph according to the grammatical specification of the intermediate format, extracting the rewrite rule from equivalent nodes, and simplifying the rewrite rule by utilizing equivalent saturation.
As a further improvement of the process of the invention: the topology transformation is carried out on the circuit intermediate format, and then the circuit intermediate format is converted into corresponding equivalent graphs.
As a further improvement of the method of the invention: applying rewrite rules to the equivalence graph adds new nodes and edges, but does not delete anything.
As a further improvement of the process of the invention: when the rewrite rule is applied to the equivalence map, the reading and the writing of the equivalence map are separated, all the matched replacements are saved in each iteration, then the replacements are added to the equivalence map, and the next iteration is carried out until the equivalence map is saturated.
As a further improvement of the method of the invention: and establishing e-nodes from the input according to the topological order, establishing a connection relation for the subsequent e-nodes according to the property of the corresponding operator, and generating the equivalent graph e-graphs.
As a further improvement of the method of the invention: and starting from the root node of the equivalent graph which is subjected to saturation or other constraints by applying the rewrite rule, and carrying out heuristic search on a target solution from top to bottom.
As a further improvement of the process of the invention: different heuristic functions can be designed aiming at different targets, and then an optimization result meeting the corresponding target is obtained.
As a further improvement of the method of the invention: establishing an equivalent graph for the topological transformation of the intermediate format of the circuit, wherein the root node of the equivalent graph is the circuit output, and the leaf node is the precursor node of the equivalent graph; and adding all possible equivalent substitutions by applying a rewriting rule in the equivalent graph, creating a data structure for equivalent nodes, integrating the nodes into the data structure, and finally searching from top to bottom by utilizing a heuristic function to obtain an optimization result meeting the target.
Compared with the prior art, the invention has the advantages that:
1. the circuit optimization method based on the circuit global information has the advantages of simple principle, simple and convenient operation, flexibility and universality, and can be used for uniformly optimizing the combinational logic and the sequential logic of the circuit, word level signals and bit level signals, data flow and control flow.
2. The circuit optimization method based on the circuit global information utilizes the idea of equivalent saturation pairs, retains the information of all the intermediate steps of design optimization, optimizes the circuit based on the global information and is beneficial to finding the optimal framework for the given circuit.
3. The circuit optimization method based on the circuit global information can search according to heuristic functions corresponding to different optimization target designs.
Drawings
FIG. 1 is a schematic flow diagram of the process of the present invention.
FIG. 2 is a schematic illustration of the conversion of FIRRTL to e-grams in an example embodiment of the present invention.
FIG. 3 is a flow chart of the inference rewrite rule in a specific application example of the present invention.
FIG. 4 is an exemplary illustration of rewriting e-grams with saturation equivalence in a specific application example of the present invention.
FIG. 5 is a schematic diagram of an exemplary FIRRTL embodiment of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
The circuit neutral format described herein refers to a neutral representation of a digital circuit, such as FIRRTL, that is designed to write a platform for circuit level conversion. Based on the intermediate format representation, customizations to the RTL can be written as functions that are passed in as parameters using the high-order function mechanism of the host language, recursively applying the customization actions to portions of the design. Because the customization is encapsulated in the function and can be used as a parameter of other functions, the customization and the RTL design are loosely coupled, and the reusability and the quick changeability of the customization are greatly improved. This customization may also be replaced with design optimization, design simplification, area power consumption prediction, mapping to FPGA or ASIC, support for verification. FIRRTL is a very compact intermediate format, an example of which is shown in fig. 5.
The invention utilizes the idea of equivalence saturation, adds equivalence substitution to an equivalence map corresponding to the circuit intermediate format by utilizing a rewriting rule until saturation, and then carries out heuristic search according to an optimization target.
As shown in fig. 1, the circuit optimization method based on circuit global information of the present invention includes:
rewriting rules by using equivalent saturation reasoning;
converting the intermediate format of the circuit into corresponding equivalent graphs;
utilizing the equivalence saturation to apply a rewriting rule to obtain all possible equivalence substitutes;
target solutions are searched from all possible equivalent replacements, and corresponding heuristic functions can be designed according to different optimization targets for searching.
In a specific application example, referring to FIG. 2, the present invention converts intermediate formats into equivalent e-grams.
Furthermore, the invention creates an e-node from the input according to the topological order of the intermediate format, establishes a connection relation for the subsequent e-node according to the property of the corresponding operator, and generates the equivalent graph e-graph.
In a specific application example, referring to fig. 3, the rule is rewritten using equivalent saturation reasoning.
Furthermore, the invention enumerates expressions in the equivalent graph according to the grammatical specification of the intermediate format, extracts the rewrite rule from equivalent nodes, and simplifies the rewrite rule by utilizing equivalent saturation.
In a specific application example, referring to fig. 4, all possible equivalence substitutions are obtained by applying the rewrite rule with equivalence saturation.
Furthermore, when the rewrite rule is applied to the equivalence map, the reading and the writing of the equivalence map are separated, all matched substitutions are stored in each iteration, then the substitutions are added to the equivalence map, and the next iteration is carried out until the equivalence map is saturated.
In a specific application example, searching can be performed according to a heuristic function corresponding to the optimization target design.
The above are only preferred embodiments of the present invention, and the scope of the present invention is not limited to the above examples, and all technical solutions that fall under the spirit of the present invention belong to the scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (9)
1. A circuit optimization method based on circuit global information is characterized by comprising the following steps:
rewriting rules by using equivalent saturation reasoning;
converting the intermediate format of the circuit into corresponding equivalent graphs;
applying a rewrite rule by utilizing equivalence saturation to obtain all possible equivalence substitutions;
the target solution is searched from all possible equivalent alternatives.
2. The circuit optimization method based on circuit global information as claimed in claim 1, wherein expressions are enumerated in the equivalence graph according to grammatical specifications of the intermediate format, rewrite rules are extracted from equivalence nodes, and the rewrite rules are reduced by equivalence saturation.
3. The circuit optimization method based on circuit global information according to claim 2, wherein the topology transformation is performed on the circuit intermediate format, and then the circuit intermediate format is converted into corresponding equivalent graph e-graphs.
4. The circuit optimization method based on circuit global information according to claim 2, wherein new nodes and edges are added without deleting any content when applying the rewrite rule to the equivalence map.
5. The circuit optimization method based on circuit global information as claimed in claim 4, wherein when applying the rewrite rule to the equivalence map, the reading and writing of the equivalence map are separated, all the matched replacements are saved in each iteration, then the replacements are added to the equivalence map, and the next iteration is carried out until the equivalence map is saturated.
6. The circuit optimization method based on circuit global information according to any one of claims 1-5, characterized in that e-nodes are created from the input according to topological order, and connection relation is established for subsequent e-nodes according to the property of corresponding operator, so as to generate the equivalent graph e-graphs.
7. The circuit optimization method based on circuit global information according to any one of claims 1-5, characterized in that, starting from the root node of the equivalence graph where the rewrite rule is applied to reach saturation or other constraints, heuristic search target solution is performed from top to bottom.
8. The circuit optimization method based on circuit global information as claimed in claim 6, wherein different heuristic functions can be designed for different objectives, thereby obtaining an optimization result satisfying the corresponding objective.
9. The circuit optimization method based on circuit global information according to any one of claims 1-6, characterized in that an equivalence graph is established for topology transformation of the intermediate format of the circuit, the root node of the equivalence graph is the circuit output, and the leaf node is its predecessor node; and adding all possible equivalent substitutions by applying a rewriting rule in the equivalent graph, creating a data structure for equivalent nodes, integrating the nodes into the data structure, and finally searching from top to bottom by utilizing a heuristic function to obtain an optimization result meeting the target.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211219682.6A CN115544928A (en) | 2022-09-30 | 2022-09-30 | Circuit optimization method based on circuit global information |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211219682.6A CN115544928A (en) | 2022-09-30 | 2022-09-30 | Circuit optimization method based on circuit global information |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115544928A true CN115544928A (en) | 2022-12-30 |
Family
ID=84731500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211219682.6A Pending CN115544928A (en) | 2022-09-30 | 2022-09-30 | Circuit optimization method based on circuit global information |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115544928A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116933697A (en) * | 2023-09-18 | 2023-10-24 | 上海芯联芯智能科技有限公司 | Method and device for converting natural language into hardware description language |
-
2022
- 2022-09-30 CN CN202211219682.6A patent/CN115544928A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116933697A (en) * | 2023-09-18 | 2023-10-24 | 上海芯联芯智能科技有限公司 | Method and device for converting natural language into hardware description language |
| CN116933697B (en) * | 2023-09-18 | 2023-12-08 | 上海芯联芯智能科技有限公司 | Method and device for converting natural language into hardware description language |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110187885B (en) | Intermediate code generation method and device for quantum program compiling | |
| Harris et al. | Glast: Learning formal grammars to translate natural language specifications into hardware assertions | |
| JP2001209547A (en) | Source code conversion method, recording medium recording source code conversion programs and source code conversion device | |
| US20140350913A1 (en) | Translation device and method | |
| CN115544928A (en) | Circuit optimization method based on circuit global information | |
| CN105138335A (en) | Function call path extracting method and device based on control flow diagram | |
| CN111176656B (en) | Complex data matching method and medium | |
| JP2020140709A (en) | Training method for neural machine translation model, apparatus, and storage medium | |
| CN115509514B (en) | Front-end data simulation method, device, equipment and medium | |
| CN112749522A (en) | RTL output stage number obtaining method, device, equipment and storage medium | |
| CN103064885A (en) | System and method for achieving synchronous inputting of key words | |
| CN117112608A (en) | Antlr 4-based database statement conversion method and device | |
| CN110825433B (en) | Design method of edge control equipment | |
| CN110533162B (en) | Method and system for automatically generating operation mapping between deep learning frames | |
| CN102937910B (en) | System and method for cross-platform conversion of control algorithms | |
| CN112860233B (en) | Method for generating target grammar tree and related equipment | |
| CN115292347A (en) | Active SQL algorithm performance checking device and method based on rules | |
| CN111679809B (en) | Program development and verification method and system based on Noesis logic | |
| CN112115615A (en) | SCR-oriented safety key system model conversion method, device and system | |
| CN109240672B (en) | Artificial intelligence writing method for information transmission source code of single machine component of digital aircraft | |
| US20210097241A1 (en) | Text matching system | |
| Chen et al. | A Conversion Framework of the Continuous Modeling Languages Based on ANTLR4 | |
| CN113157257B (en) | Rapid development device for banking system | |
| CN117763101A (en) | Fuzzy test method based on neural network language model | |
| Rieckhof et al. | Ontology-based Model Synchronisation. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |